Commit f6b43d93 authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle

MIPS: pm-cps: Update comments on barrier instructions

This code makes large use of barriers, which had quite vague
descriptions. Update the comments to make the choice of barrier and
reason for it more clear.
Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14220/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b97d0b90
...@@ -315,7 +315,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl, ...@@ -315,7 +315,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
i * line_size * line_stride, t0); i * line_size * line_stride, t0);
} }
/* Completion barrier */ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(pp, stype_memory); uasm_i_sync(pp, stype_memory);
uasm_i_ehb(pp); uasm_i_ehb(pp);
...@@ -414,7 +414,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -414,7 +414,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_il_beqz(&p, &r, t2, lbl_incready); uasm_il_beqz(&p, &r, t2, lbl_incready);
uasm_i_addiu(&p, t1, t1, 1); uasm_i_addiu(&p, t1, t1, 1);
/* Ordering barrier */ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering); uasm_i_sync(&p, stype_ordering);
/* /*
...@@ -467,7 +467,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -467,7 +467,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache, cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
Index_Writeback_Inv_D, lbl_flushdcache); Index_Writeback_Inv_D, lbl_flushdcache);
/* Completion barrier */ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(&p, stype_memory); uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p); uasm_i_ehb(&p);
...@@ -480,7 +480,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -480,7 +480,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_sw(&p, t0, 0, r_pcohctl); uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl); uasm_i_lw(&p, t0, 0, r_pcohctl);
/* Sync to ensure previous interventions are complete */ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_intervention); uasm_i_sync(&p, stype_intervention);
uasm_i_ehb(&p); uasm_i_ehb(&p);
...@@ -526,7 +526,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -526,7 +526,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
goto gen_done; goto gen_done;
} }
/* Completion barrier */ /* Barrier to ensure write to CPC command is complete */
uasm_i_sync(&p, stype_memory); uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p); uasm_i_ehb(&p);
} }
...@@ -561,7 +561,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -561,7 +561,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_sw(&p, t0, 0, r_pcohctl); uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl); uasm_i_lw(&p, t0, 0, r_pcohctl);
/* Completion barrier */ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_memory); uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p); uasm_i_ehb(&p);
...@@ -575,7 +575,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -575,7 +575,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_il_beqz(&p, &r, t2, lbl_decready); uasm_il_beqz(&p, &r, t2, lbl_decready);
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1); uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
/* Ordering barrier */ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering); uasm_i_sync(&p, stype_ordering);
} }
...@@ -597,7 +597,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -597,7 +597,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
*/ */
uasm_build_label(&l, p, lbl_secondary_cont); uasm_build_label(&l, p, lbl_secondary_cont);
/* Ordering barrier */ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering); uasm_i_sync(&p, stype_ordering);
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment