Commit f81c1d4a authored by Samuel Holland's avatar Samuel Holland Committed by Herbert Xu

crypto: sun8i-ce - Add TRNG clock to the D1 variant

At least the D1 variant requires a separate clock for the TRNG.
Without this clock enabled, reading from /dev/hwrng reports:

   sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3

Experimentation shows that the necessary clock is the SoC's internal
RC oscillator. This makes sense, as noise from the oscillator can be
used as a source of entropy.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: default avatarCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 197286f8
......@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_variant = {
{ "bus", 0, 200000000 },
{ "mod", 300000000, 0 },
{ "ram", 0, 400000000 },
{ "trng", 0, 0 },
},
.esr = ESR_D1,
.prng = CE_ALG_PRNG,
......
......@@ -105,7 +105,7 @@
#define MAX_SG 8
#define CE_MAX_CLOCKS 3
#define CE_MAX_CLOCKS 4
#define MAXFLOW 4
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment