Commit f8408d2b authored by Kai Ye's avatar Kai Ye Committed by Herbert Xu

crypto: hisilicon - add ZIP device using mode parameter

Add 'uacce_mode' parameter for ZIP, which can be set as 0(default) or 1.
'0' means ZIP is only registered to kernel crypto, and '1' means it's
registered to both kernel crypto and UACCE.
Signed-off-by: default avatarKai Ye <yekai13@huawei.com>
Reviewed-by: default avatarZhou Wang <wangzhou1@hisilicon.com>
Reviewed-by: default avatarZaibo Xu <xuzaibo@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 0d61c3f1
...@@ -2206,7 +2206,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm) ...@@ -2206,7 +2206,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm)
if (IS_ERR(uacce)) if (IS_ERR(uacce))
return PTR_ERR(uacce); return PTR_ERR(uacce);
if (uacce->flags & UACCE_DEV_SVA) { if (uacce->flags & UACCE_DEV_SVA && qm->mode == UACCE_MODE_SVA) {
qm->use_sva = true; qm->use_sva = true;
} else { } else {
/* only consider sva case */ /* only consider sva case */
......
...@@ -85,6 +85,11 @@ ...@@ -85,6 +85,11 @@
/* page number for queue file region */ /* page number for queue file region */
#define QM_DOORBELL_PAGE_NR 1 #define QM_DOORBELL_PAGE_NR 1
/* uacce mode of the driver */
#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
#define UACCE_MODE_SVA 1 /* use uacce sva mode */
#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
enum qm_stop_reason { enum qm_stop_reason {
QM_NORMAL, QM_NORMAL,
QM_SOFT_RESET, QM_SOFT_RESET,
...@@ -249,6 +254,7 @@ struct hisi_qm { ...@@ -249,6 +254,7 @@ struct hisi_qm {
resource_size_t phys_base; resource_size_t phys_base;
resource_size_t phys_size; resource_size_t phys_size;
struct uacce_device *uacce; struct uacce_device *uacce;
int mode;
}; };
struct hisi_qp_status { struct hisi_qp_status {
...@@ -333,6 +339,27 @@ static inline int vfs_num_set(const char *val, const struct kernel_param *kp) ...@@ -333,6 +339,27 @@ static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
return param_set_int(val, kp); return param_set_int(val, kp);
} }
static inline int mode_set(const char *val, const struct kernel_param *kp)
{
u32 n;
int ret;
if (!val)
return -EINVAL;
ret = kstrtou32(val, 10, &n);
if (ret != 0 || (n != UACCE_MODE_SVA &&
n != UACCE_MODE_NOUACCE))
return -EINVAL;
return param_set_int(val, kp);
}
static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
return mode_set(val, kp);
}
static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list) static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{ {
INIT_LIST_HEAD(&qm_list->list); INIT_LIST_HEAD(&qm_list->list);
......
...@@ -211,6 +211,19 @@ static const struct debugfs_reg32 hzip_dfx_regs[] = { ...@@ -211,6 +211,19 @@ static const struct debugfs_reg32 hzip_dfx_regs[] = {
{"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull},
}; };
static const struct kernel_param_ops zip_uacce_mode_ops = {
.set = uacce_mode_set,
.get = param_get_int,
};
/*
* uacce_mode = 0 means zip only register to crypto,
* uacce_mode = 1 means zip both register to crypto and uacce.
*/
static u32 uacce_mode = UACCE_MODE_NOUACCE;
module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444);
MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
static int pf_q_num_set(const char *val, const struct kernel_param *kp) static int pf_q_num_set(const char *val, const struct kernel_param *kp)
{ {
return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF); return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF);
...@@ -752,6 +765,7 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) ...@@ -752,6 +765,7 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
qm->pdev = pdev; qm->pdev = pdev;
qm->ver = pdev->revision; qm->ver = pdev->revision;
qm->algs = "zlib\ngzip"; qm->algs = "zlib\ngzip";
qm->mode = uacce_mode;
qm->sqe_size = HZIP_SQE_SIZE; qm->sqe_size = HZIP_SQE_SIZE;
qm->dev_name = hisi_zip_name; qm->dev_name = hisi_zip_name;
......
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