drm/bridge: tc358767: Limit the Pixel PLL input range

According to new configuration spreadsheet from Toshiba for TC9595,
the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
calculates those PLL input clock as reference clock divided by both
pre-dividers. Add the extra limit.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240118220243.203655-1-marex@denx.de

drivers/gpu/drm/bridge/tc358767.c

@@ -617,9 +617,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 			continue;
 		for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 			for (div = 1; div <= 16; div++) {
-				u32 clk;
+				u32 clk, iclk;
 				u64 tmp;
 
+				/* PCLK PLL input unit clock ... 6..40 MHz */
+				iclk = refclk / (div * ext_div[i_pre]);
+				if (iclk < 6000000 || iclk > 40000000)
+					continue;
+
 				tmp = pixelclock * ext_div[i_pre] *
 				      ext_div[i_post] * div;
 				do_div(tmp, refclk);