Commit f86b47be authored by TungYu Lu's avatar TungYu Lu Committed by Alex Deucher

drm/amd/display: resync OTG after DIO FIFO resync

[WHY]
Tiled displays showed not aligned on 8K60hz when system resumed
from S3/S4.

[HOW]
Do dc_trigger_sync to re-sync pipes to ensure OTG become synced.
Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarTungYu Lu <tungyu.lu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a4758aa3
...@@ -1254,6 +1254,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_ ...@@ -1254,6 +1254,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
} }
} }
dc_trigger_sync(dc, dc->current_state);
} }
void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
......
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