Commit f8bdce3e authored by Maruthi Srinivas Bayyavarapu's avatar Maruthi Srinivas Bayyavarapu Committed by Alex Deucher

drm/amdgpu: enable UVD clockgating in Polaris-10/11

UVD clocks are set to be disabled, when not in use.
Signed-off-by: default avatarMaruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarTom StDenis <Tom.StDenis@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 81c1514b
...@@ -934,12 +934,12 @@ static int vi_common_early_init(void *handle) ...@@ -934,12 +934,12 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x14; adev->external_rev_id = adev->rev_id + 0x14;
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
adev->cg_flags = 0; adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x5A; adev->external_rev_id = adev->rev_id + 0x5A;
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
adev->cg_flags = 0; adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x50; adev->external_rev_id = adev->rev_id + 0x50;
break; break;
......
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