Commit f8cc5756 authored by Linus Torvalds's avatar Linus Torvalds

Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6

parents bf7c7dec b4d1b825
...@@ -49,12 +49,6 @@ static void __iommu_flushall(struct pci_iommu *iommu) ...@@ -49,12 +49,6 @@ static void __iommu_flushall(struct pci_iommu *iommu)
/* Ensure completion of previous PIO writes. */ /* Ensure completion of previous PIO writes. */
(void) pci_iommu_read(iommu->write_complete_reg); (void) pci_iommu_read(iommu->write_complete_reg);
/* Now update everyone's flush point. */
for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
iommu->alloc_info[entry].flush =
iommu->alloc_info[entry].next;
}
} }
#define IOPTE_CONSISTENT(CTX) \ #define IOPTE_CONSISTENT(CTX) \
...@@ -80,120 +74,117 @@ static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte) ...@@ -80,120 +74,117 @@ static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
iopte_val(*iopte) = val; iopte_val(*iopte) = val;
} }
void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize) /* Based largely upon the ppc64 iommu allocator. */
{ static long pci_arena_alloc(struct pci_iommu *iommu, unsigned long npages)
int i;
tsbsize /= sizeof(iopte_t);
for (i = 0; i < tsbsize; i++)
iopte_make_dummy(iommu, &iommu->page_table[i]);
}
static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
{ {
iopte_t *iopte, *limit, *first; struct pci_iommu_arena *arena = &iommu->arena;
unsigned long cnum, ent, flush_point; unsigned long n, i, start, end, limit;
int pass;
cnum = 0;
while ((1UL << cnum) < npages) limit = arena->limit;
cnum++; start = arena->hint;
iopte = (iommu->page_table + pass = 0;
(cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
again:
if (cnum == 0) n = find_next_zero_bit(arena->map, limit, start);
limit = (iommu->page_table + end = n + npages;
iommu->lowest_consistent_map); if (unlikely(end >= limit)) {
else if (likely(pass < 1)) {
limit = (iopte + limit = start;
(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS))); start = 0;
iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
flush_point = iommu->alloc_info[cnum].flush;
first = iopte;
for (;;) {
if (IOPTE_IS_DUMMY(iommu, iopte)) {
if ((iopte + (1 << cnum)) >= limit)
ent = 0;
else
ent = ent + 1;
iommu->alloc_info[cnum].next = ent;
if (ent == flush_point)
__iommu_flushall(iommu); __iommu_flushall(iommu);
break; pass++;
goto again;
} else {
/* Scanned the whole thing, give up. */
return -1;
} }
iopte += (1 << cnum);
ent++;
if (iopte >= limit) {
iopte = (iommu->page_table +
(cnum <<
(iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
ent = 0;
} }
if (ent == flush_point)
__iommu_flushall(iommu); for (i = n; i < end; i++) {
if (iopte == first) if (test_bit(i, arena->map)) {
goto bad; start = i + 1;
goto again;
}
} }
/* I've got your streaming cluster right here buddy boy... */ for (i = n; i < end; i++)
return iopte; __set_bit(i, arena->map);
bad: arena->hint = end;
printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
npages); return n;
return NULL;
} }
static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base, static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
unsigned long npages, unsigned long ctx)
{ {
unsigned long cnum, ent; unsigned long i;
cnum = 0;
while ((1UL << cnum) < npages)
cnum++;
ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
>> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
/* If the global flush might not have caught this entry, for (i = base; i < (base + npages); i++)
* adjust the flush point such that we will flush before __clear_bit(i, arena->map);
* ever trying to reuse it.
*/
#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
iommu->alloc_info[cnum].flush = ent;
#undef between
} }
/* We allocate consistent mappings from the end of cluster zero. */ void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
{ {
iopte_t *iopte; unsigned long i, tsbbase, order, sz, num_tsb_entries;
iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)); num_tsb_entries = tsbsize / sizeof(iopte_t);
while (iopte > iommu->page_table) {
iopte--;
if (IOPTE_IS_DUMMY(iommu, iopte)) {
unsigned long tmp = npages;
while (--tmp) { /* Setup initial software IOMMU state. */
iopte--; spin_lock_init(&iommu->lock);
if (!IOPTE_IS_DUMMY(iommu, iopte)) iommu->ctx_lowest_free = 1;
break; iommu->page_table_map_base = dma_offset;
} iommu->dma_addr_mask = dma_addr_mask;
if (tmp == 0) {
u32 entry = (iopte - iommu->page_table);
if (entry < iommu->lowest_consistent_map) /* Allocate and initialize the free area map. */
iommu->lowest_consistent_map = entry; sz = num_tsb_entries / 8;
return iopte; sz = (sz + 7UL) & ~7UL;
iommu->arena.map = kmalloc(sz, GFP_KERNEL);
if (!iommu->arena.map) {
prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
prom_halt();
} }
memset(iommu->arena.map, 0, sz);
iommu->arena.limit = num_tsb_entries;
/* Allocate and initialize the dummy page which we
* set inactive IO PTEs to point to.
*/
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
if (!iommu->dummy_page) {
prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
prom_halt();
} }
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
/* Now allocate and setup the IOMMU page table itself. */
order = get_order(tsbsize);
tsbbase = __get_free_pages(GFP_KERNEL, order);
if (!tsbbase) {
prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
prom_halt();
} }
iommu->page_table = (iopte_t *)tsbbase;
for (i = 0; i < num_tsb_entries; i++)
iopte_make_dummy(iommu, &iommu->page_table[i]);
}
static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npages)
{
long entry;
entry = pci_arena_alloc(iommu, npages);
if (unlikely(entry < 0))
return NULL; return NULL;
return iommu->page_table + entry;
}
static inline void free_npages(struct pci_iommu *iommu, dma_addr_t base, unsigned long npages)
{
pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
} }
static int iommu_alloc_ctx(struct pci_iommu *iommu) static int iommu_alloc_ctx(struct pci_iommu *iommu)
...@@ -233,7 +224,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad ...@@ -233,7 +224,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
struct pcidev_cookie *pcp; struct pcidev_cookie *pcp;
struct pci_iommu *iommu; struct pci_iommu *iommu;
iopte_t *iopte; iopte_t *iopte;
unsigned long flags, order, first_page, ctx; unsigned long flags, order, first_page;
void *ret; void *ret;
int npages; int npages;
...@@ -251,9 +242,10 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad ...@@ -251,9 +242,10 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
iommu = pcp->pbm->iommu; iommu = pcp->pbm->iommu;
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT); iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
if (iopte == NULL) {
spin_unlock_irqrestore(&iommu->lock, flags); spin_unlock_irqrestore(&iommu->lock, flags);
if (unlikely(iopte == NULL)) {
free_pages(first_page, order); free_pages(first_page, order);
return NULL; return NULL;
} }
...@@ -262,31 +254,15 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad ...@@ -262,31 +254,15 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
((iopte - iommu->page_table) << IO_PAGE_SHIFT)); ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
ret = (void *) first_page; ret = (void *) first_page;
npages = size >> IO_PAGE_SHIFT; npages = size >> IO_PAGE_SHIFT;
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
first_page = __pa(first_page); first_page = __pa(first_page);
while (npages--) { while (npages--) {
iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
IOPTE_WRITE | IOPTE_WRITE |
(first_page & IOPTE_PAGE)); (first_page & IOPTE_PAGE));
iopte++; iopte++;
first_page += IO_PAGE_SIZE; first_page += IO_PAGE_SIZE;
} }
{
int i;
u32 daddr = *dma_addrp;
npages = size >> IO_PAGE_SHIFT;
for (i = 0; i < npages; i++) {
pci_iommu_write(iommu->iommu_flush, daddr);
daddr += IO_PAGE_SIZE;
}
}
spin_unlock_irqrestore(&iommu->lock, flags);
return ret; return ret;
} }
...@@ -296,7 +272,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_ ...@@ -296,7 +272,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_
struct pcidev_cookie *pcp; struct pcidev_cookie *pcp;
struct pci_iommu *iommu; struct pci_iommu *iommu;
iopte_t *iopte; iopte_t *iopte;
unsigned long flags, order, npages, i, ctx; unsigned long flags, order, npages;
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
pcp = pdev->sysdata; pcp = pdev->sysdata;
...@@ -306,46 +282,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_ ...@@ -306,46 +282,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
if ((iopte - iommu->page_table) == free_npages(iommu, dvma, npages);
iommu->lowest_consistent_map) {
iopte_t *walk = iopte + npages;
iopte_t *limit;
limit = (iommu->page_table +
(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
while (walk < limit) {
if (!IOPTE_IS_DUMMY(iommu, walk))
break;
walk++;
}
iommu->lowest_consistent_map =
(walk - iommu->page_table);
}
/* Data for consistent mappings cannot enter the streaming
* buffers, so we only need to update the TSB. We flush
* the IOMMU here as well to prevent conflicts with the
* streaming mapping deferred tlb flush scheme.
*/
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
for (i = 0; i < npages; i++, iopte++)
iopte_make_dummy(iommu, iopte);
if (iommu->iommu_ctxflush) {
pci_iommu_write(iommu->iommu_ctxflush, ctx);
} else {
for (i = 0; i < npages; i++) {
u32 daddr = dvma + (i << IO_PAGE_SHIFT);
pci_iommu_write(iommu->iommu_flush, daddr);
}
}
iommu_free_ctx(iommu, ctx);
spin_unlock_irqrestore(&iommu->lock, flags); spin_unlock_irqrestore(&iommu->lock, flags);
...@@ -372,25 +309,27 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct ...@@ -372,25 +309,27 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct
iommu = pcp->pbm->iommu; iommu = pcp->pbm->iommu;
strbuf = &pcp->pbm->stc; strbuf = &pcp->pbm->stc;
if (direction == PCI_DMA_NONE) if (unlikely(direction == PCI_DMA_NONE))
BUG(); goto bad_no_ctx;
oaddr = (unsigned long)ptr; oaddr = (unsigned long)ptr;
npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT; npages >>= IO_PAGE_SHIFT;
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
base = alloc_npages(iommu, npages);
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
spin_unlock_irqrestore(&iommu->lock, flags);
base = alloc_streaming_cluster(iommu, npages); if (unlikely(!base))
if (base == NULL)
goto bad; goto bad;
bus_addr = (iommu->page_table_map_base + bus_addr = (iommu->page_table_map_base +
((base - iommu->page_table) << IO_PAGE_SHIFT)); ((base - iommu->page_table) << IO_PAGE_SHIFT));
ret = bus_addr | (oaddr & ~IO_PAGE_MASK); ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
base_paddr = __pa(oaddr & IO_PAGE_MASK); base_paddr = __pa(oaddr & IO_PAGE_MASK);
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
if (strbuf->strbuf_enabled) if (strbuf->strbuf_enabled)
iopte_protection = IOPTE_STREAMING(ctx); iopte_protection = IOPTE_STREAMING(ctx);
else else
...@@ -401,12 +340,13 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct ...@@ -401,12 +340,13 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct
for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
iopte_val(*base) = iopte_protection | base_paddr; iopte_val(*base) = iopte_protection | base_paddr;
spin_unlock_irqrestore(&iommu->lock, flags);
return ret; return ret;
bad: bad:
spin_unlock_irqrestore(&iommu->lock, flags); iommu_free_ctx(iommu, ctx);
bad_no_ctx:
if (printk_ratelimit())
WARN_ON(1);
return PCI_DMA_ERROR_CODE; return PCI_DMA_ERROR_CODE;
} }
...@@ -481,10 +421,13 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int ...@@ -481,10 +421,13 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int
struct pci_iommu *iommu; struct pci_iommu *iommu;
struct pci_strbuf *strbuf; struct pci_strbuf *strbuf;
iopte_t *base; iopte_t *base;
unsigned long flags, npages, ctx; unsigned long flags, npages, ctx, i;
if (direction == PCI_DMA_NONE) if (unlikely(direction == PCI_DMA_NONE)) {
BUG(); if (printk_ratelimit())
WARN_ON(1);
return;
}
pcp = pdev->sysdata; pcp = pdev->sysdata;
iommu = pcp->pbm->iommu; iommu = pcp->pbm->iommu;
...@@ -510,13 +453,14 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int ...@@ -510,13 +453,14 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int
/* Step 1: Kick data out of streaming buffers if necessary. */ /* Step 1: Kick data out of streaming buffers if necessary. */
if (strbuf->strbuf_enabled) if (strbuf->strbuf_enabled)
pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); pci_strbuf_flush(strbuf, iommu, bus_addr, ctx,
npages, direction);
/* Step 2: Clear out first TSB entry. */ /* Step 2: Clear out TSB entries. */
iopte_make_dummy(iommu, base); for (i = 0; i < npages; i++)
iopte_make_dummy(iommu, base + i);
free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base, free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
npages, ctx);
iommu_free_ctx(iommu, ctx); iommu_free_ctx(iommu, ctx);
...@@ -621,6 +565,8 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int ...@@ -621,6 +565,8 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
pci_map_single(pdev, pci_map_single(pdev,
(page_address(sglist->page) + sglist->offset), (page_address(sglist->page) + sglist->offset),
sglist->length, direction); sglist->length, direction);
if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
return 0;
sglist->dma_length = sglist->length; sglist->dma_length = sglist->length;
return 1; return 1;
} }
...@@ -629,21 +575,29 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int ...@@ -629,21 +575,29 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
iommu = pcp->pbm->iommu; iommu = pcp->pbm->iommu;
strbuf = &pcp->pbm->stc; strbuf = &pcp->pbm->stc;
if (direction == PCI_DMA_NONE) if (unlikely(direction == PCI_DMA_NONE))
BUG(); goto bad_no_ctx;
/* Step 1: Prepare scatter list. */ /* Step 1: Prepare scatter list. */
npages = prepare_sg(sglist, nelems); npages = prepare_sg(sglist, nelems);
/* Step 2: Allocate a cluster. */ /* Step 2: Allocate a cluster and context, if necessary. */
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
base = alloc_streaming_cluster(iommu, npages); base = alloc_npages(iommu, npages);
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
spin_unlock_irqrestore(&iommu->lock, flags);
if (base == NULL) if (base == NULL)
goto bad; goto bad;
dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
dma_base = iommu->page_table_map_base +
((base - iommu->page_table) << IO_PAGE_SHIFT);
/* Step 3: Normalize DMA addresses. */ /* Step 3: Normalize DMA addresses. */
used = nelems; used = nelems;
...@@ -656,30 +610,28 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int ...@@ -656,30 +610,28 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
} }
used = nelems - used; used = nelems - used;
/* Step 4: Choose a context if necessary. */ /* Step 4: Create the mappings. */
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
/* Step 5: Create the mappings. */
if (strbuf->strbuf_enabled) if (strbuf->strbuf_enabled)
iopte_protection = IOPTE_STREAMING(ctx); iopte_protection = IOPTE_STREAMING(ctx);
else else
iopte_protection = IOPTE_CONSISTENT(ctx); iopte_protection = IOPTE_CONSISTENT(ctx);
if (direction != PCI_DMA_TODEVICE) if (direction != PCI_DMA_TODEVICE)
iopte_protection |= IOPTE_WRITE; iopte_protection |= IOPTE_WRITE;
fill_sg (base, sglist, used, nelems, iopte_protection);
fill_sg(base, sglist, used, nelems, iopte_protection);
#ifdef VERIFY_SG #ifdef VERIFY_SG
verify_sglist(sglist, nelems, base, npages); verify_sglist(sglist, nelems, base, npages);
#endif #endif
spin_unlock_irqrestore(&iommu->lock, flags);
return used; return used;
bad: bad:
spin_unlock_irqrestore(&iommu->lock, flags); iommu_free_ctx(iommu, ctx);
return PCI_DMA_ERROR_CODE; bad_no_ctx:
if (printk_ratelimit())
WARN_ON(1);
return 0;
} }
/* Unmap a set of streaming mode DMA translations. */ /* Unmap a set of streaming mode DMA translations. */
...@@ -692,8 +644,10 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, ...@@ -692,8 +644,10 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
unsigned long flags, ctx, i, npages; unsigned long flags, ctx, i, npages;
u32 bus_addr; u32 bus_addr;
if (direction == PCI_DMA_NONE) if (unlikely(direction == PCI_DMA_NONE)) {
BUG(); if (printk_ratelimit())
WARN_ON(1);
}
pcp = pdev->sysdata; pcp = pdev->sysdata;
iommu = pcp->pbm->iommu; iommu = pcp->pbm->iommu;
...@@ -705,7 +659,8 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, ...@@ -705,7 +659,8 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
if (sglist[i].dma_length == 0) if (sglist[i].dma_length == 0)
break; break;
i--; i--;
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT; npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
bus_addr) >> IO_PAGE_SHIFT;
base = iommu->page_table + base = iommu->page_table +
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
...@@ -726,11 +681,11 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, ...@@ -726,11 +681,11 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
if (strbuf->strbuf_enabled) if (strbuf->strbuf_enabled)
pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
/* Step 2: Clear out first TSB entry. */ /* Step 2: Clear out the TSB entries. */
iopte_make_dummy(iommu, base); for (i = 0; i < npages; i++)
iopte_make_dummy(iommu, base + i);
free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base, free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
npages, ctx);
iommu_free_ctx(iommu, ctx); iommu_free_ctx(iommu, ctx);
......
...@@ -1207,13 +1207,9 @@ static void psycho_scan_bus(struct pci_controller_info *p) ...@@ -1207,13 +1207,9 @@ static void psycho_scan_bus(struct pci_controller_info *p)
static void psycho_iommu_init(struct pci_controller_info *p) static void psycho_iommu_init(struct pci_controller_info *p)
{ {
struct pci_iommu *iommu = p->pbm_A.iommu; struct pci_iommu *iommu = p->pbm_A.iommu;
unsigned long tsbbase, i; unsigned long i;
u64 control; u64 control;
/* Setup initial software IOMMU state. */
spin_lock_init(&iommu->lock);
iommu->ctx_lowest_free = 1;
/* Register addresses. */ /* Register addresses. */
iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL; iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE; iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
...@@ -1240,40 +1236,10 @@ static void psycho_iommu_init(struct pci_controller_info *p) ...@@ -1240,40 +1236,10 @@ static void psycho_iommu_init(struct pci_controller_info *p)
/* Leave diag mode enabled for full-flushing done /* Leave diag mode enabled for full-flushing done
* in pci_iommu.c * in pci_iommu.c
*/ */
pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
if (!iommu->dummy_page) { __pa(iommu->page_table));
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
prom_halt();
}
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
/* Using assumed page size 8K with 128K entries we need 1MB iommu page
* table (128K ioptes * 8 bytes per iopte). This is
* page order 7 on UltraSparc.
*/
tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE));
if (!tsbbase) {
prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
prom_halt();
}
iommu->page_table = (iopte_t *)tsbbase;
iommu->page_table_sz_bits = 17;
iommu->page_table_map_base = 0xc0000000;
iommu->dma_addr_mask = 0xffffffff;
pci_iommu_table_init(iommu, IO_TSB_SIZE);
/* We start with no consistent mappings. */
iommu->lowest_consistent_map =
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
for (i = 0; i < PBM_NCLUSTERS; i++) {
iommu->alloc_info[i].flush = 0;
iommu->alloc_info[i].next = 0;
}
psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));
control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL); control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
...@@ -1281,7 +1247,7 @@ static void psycho_iommu_init(struct pci_controller_info *p) ...@@ -1281,7 +1247,7 @@ static void psycho_iommu_init(struct pci_controller_info *p)
psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control); psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
/* If necessary, hook us up for starfire IRQ translations. */ /* If necessary, hook us up for starfire IRQ translations. */
if(this_is_starfire) if (this_is_starfire)
p->starfire_cookie = starfire_hookup(p->pbm_A.portid); p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
else else
p->starfire_cookie = NULL; p->starfire_cookie = NULL;
......
...@@ -1267,13 +1267,9 @@ static void sabre_iommu_init(struct pci_controller_info *p, ...@@ -1267,13 +1267,9 @@ static void sabre_iommu_init(struct pci_controller_info *p,
u32 dma_mask) u32 dma_mask)
{ {
struct pci_iommu *iommu = p->pbm_A.iommu; struct pci_iommu *iommu = p->pbm_A.iommu;
unsigned long tsbbase, i, order; unsigned long i;
u64 control; u64 control;
/* Setup initial software IOMMU state. */
spin_lock_init(&iommu->lock);
iommu->ctx_lowest_free = 1;
/* Register addresses. */ /* Register addresses. */
iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL; iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE; iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
...@@ -1295,26 +1291,10 @@ static void sabre_iommu_init(struct pci_controller_info *p, ...@@ -1295,26 +1291,10 @@ static void sabre_iommu_init(struct pci_controller_info *p,
/* Leave diag mode enabled for full-flushing done /* Leave diag mode enabled for full-flushing done
* in pci_iommu.c * in pci_iommu.c
*/ */
pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
if (!iommu->dummy_page) { __pa(iommu->page_table));
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
prom_halt();
}
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
tsbbase = __get_free_pages(GFP_KERNEL, order = get_order(tsbsize * 1024 * 8));
if (!tsbbase) {
prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");
prom_halt();
}
iommu->page_table = (iopte_t *)tsbbase;
iommu->page_table_map_base = dvma_offset;
iommu->dma_addr_mask = dma_mask;
pci_iommu_table_init(iommu, PAGE_SIZE << order);
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase));
control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL); control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
...@@ -1322,11 +1302,9 @@ static void sabre_iommu_init(struct pci_controller_info *p, ...@@ -1322,11 +1302,9 @@ static void sabre_iommu_init(struct pci_controller_info *p,
switch(tsbsize) { switch(tsbsize) {
case 64: case 64:
control |= SABRE_IOMMU_TSBSZ_64K; control |= SABRE_IOMMU_TSBSZ_64K;
iommu->page_table_sz_bits = 16;
break; break;
case 128: case 128:
control |= SABRE_IOMMU_TSBSZ_128K; control |= SABRE_IOMMU_TSBSZ_128K;
iommu->page_table_sz_bits = 17;
break; break;
default: default:
prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize); prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
...@@ -1334,15 +1312,6 @@ static void sabre_iommu_init(struct pci_controller_info *p, ...@@ -1334,15 +1312,6 @@ static void sabre_iommu_init(struct pci_controller_info *p,
break; break;
} }
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control); sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
/* We start with no consistent mappings. */
iommu->lowest_consistent_map =
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
for (i = 0; i < PBM_NCLUSTERS; i++) {
iommu->alloc_info[i].flush = 0;
iommu->alloc_info[i].next = 0;
}
} }
static void pbm_register_toplevel_resources(struct pci_controller_info *p, static void pbm_register_toplevel_resources(struct pci_controller_info *p,
......
...@@ -1765,7 +1765,7 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) ...@@ -1765,7 +1765,7 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
{ {
struct pci_iommu *iommu = pbm->iommu; struct pci_iommu *iommu = pbm->iommu;
unsigned long tsbbase, i, tagbase, database, order; unsigned long i, tagbase, database;
u32 vdma[2], dma_mask; u32 vdma[2], dma_mask;
u64 control; u64 control;
int err, tsbsize; int err, tsbsize;
...@@ -1800,10 +1800,6 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) ...@@ -1800,10 +1800,6 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
prom_halt(); prom_halt();
}; };
/* Setup initial software IOMMU state. */
spin_lock_init(&iommu->lock);
iommu->ctx_lowest_free = 1;
/* Register addresses, SCHIZO has iommu ctx flushing. */ /* Register addresses, SCHIZO has iommu ctx flushing. */
iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
...@@ -1832,56 +1828,9 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) ...@@ -1832,56 +1828,9 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
/* Leave diag mode enabled for full-flushing done /* Leave diag mode enabled for full-flushing done
* in pci_iommu.c * in pci_iommu.c
*/ */
pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
if (!iommu->dummy_page) {
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
prom_halt();
}
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
/* Using assumed page size 8K with 128K entries we need 1MB iommu page
* table (128K ioptes * 8 bytes per iopte). This is
* page order 7 on UltraSparc.
*/
order = get_order(tsbsize * 8 * 1024);
tsbbase = __get_free_pages(GFP_KERNEL, order);
if (!tsbbase) {
prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name);
prom_halt();
}
iommu->page_table = (iopte_t *)tsbbase;
iommu->page_table_map_base = vdma[0];
iommu->dma_addr_mask = dma_mask;
pci_iommu_table_init(iommu, PAGE_SIZE << order);
switch (tsbsize) {
case 64:
iommu->page_table_sz_bits = 16;
break;
case 128:
iommu->page_table_sz_bits = 17;
break;
default:
prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
prom_halt();
break;
};
/* We start with no consistent mappings. */
iommu->lowest_consistent_map =
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
for (i = 0; i < PBM_NCLUSTERS; i++) {
iommu->alloc_info[i].flush = 0;
iommu->alloc_info[i].next = 0;
}
schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));
control = schizo_read(iommu->iommu_control); control = schizo_read(iommu->iommu_control);
control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
......
...@@ -1001,13 +1001,6 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs) ...@@ -1001,13 +1001,6 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs)
preempt_enable(); preempt_enable();
} }
extern unsigned long xcall_promstop;
void smp_promstop_others(void)
{
smp_cross_call(&xcall_promstop, 0, 0, 0);
}
#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
#define prof_counter(__cpu) cpu_data(__cpu).counter #define prof_counter(__cpu) cpu_data(__cpu).counter
......
...@@ -453,22 +453,6 @@ xcall_flush_dcache_page_spitfire: /* %g1 == physical page address ...@@ -453,22 +453,6 @@ xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
nop nop
nop nop
.globl xcall_promstop
xcall_promstop:
rdpr %pstate, %g2
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
rdpr %pil, %g2
wrpr %g0, 15, %pil
sethi %hi(109f), %g7
b,pt %xcc, etrap_irq
109: or %g7, %lo(109b), %g7
flushw
call prom_stopself
nop
/* We should not return, just spin if we do... */
1: b,a,pt %xcc, 1b
nop
.data .data
errata32_hwbug: errata32_hwbug:
......
...@@ -68,19 +68,11 @@ void prom_cmdline(void) ...@@ -68,19 +68,11 @@ void prom_cmdline(void)
local_irq_restore(flags); local_irq_restore(flags);
} }
#ifdef CONFIG_SMP
extern void smp_promstop_others(void);
#endif
/* Drop into the prom, but completely terminate the program. /* Drop into the prom, but completely terminate the program.
* No chance of continuing. * No chance of continuing.
*/ */
void prom_halt(void) void prom_halt(void)
{ {
#ifdef CONFIG_SMP
smp_promstop_others();
udelay(8000);
#endif
again: again:
p1275_cmd("exit", P1275_INOUT(0, 0)); p1275_cmd("exit", P1275_INOUT(0, 0));
goto again; /* PROM is out to get me -DaveM */ goto again; /* PROM is out to get me -DaveM */
...@@ -88,10 +80,6 @@ void prom_halt(void) ...@@ -88,10 +80,6 @@ void prom_halt(void)
void prom_halt_power_off(void) void prom_halt_power_off(void)
{ {
#ifdef CONFIG_SMP
smp_promstop_others();
udelay(8000);
#endif
p1275_cmd("SUNW,power-off", P1275_INOUT(0, 0)); p1275_cmd("SUNW,power-off", P1275_INOUT(0, 0));
/* if nothing else helps, we just halt */ /* if nothing else helps, we just halt */
......
...@@ -1119,6 +1119,36 @@ static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int ...@@ -1119,6 +1119,36 @@ static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int
host->sg_tablesize = QLOGICPTI_MAX_SG(num_free); host->sg_tablesize = QLOGICPTI_MAX_SG(num_free);
} }
static unsigned int scsi_rbuf_get(struct scsi_cmnd *cmd, unsigned char **buf_out)
{
unsigned char *buf;
unsigned int buflen;
if (cmd->use_sg) {
struct scatterlist *sg;
sg = (struct scatterlist *) cmd->request_buffer;
buf = kmap_atomic(sg->page, KM_IRQ0) + sg->offset;
buflen = sg->length;
} else {
buf = cmd->request_buffer;
buflen = cmd->request_bufflen;
}
*buf_out = buf;
return buflen;
}
static void scsi_rbuf_put(struct scsi_cmnd *cmd, unsigned char *buf)
{
if (cmd->use_sg) {
struct scatterlist *sg;
sg = (struct scatterlist *) cmd->request_buffer;
kunmap_atomic(buf - sg->offset, KM_IRQ0);
}
}
/* /*
* Until we scan the entire bus with inquiries, go throught this fella... * Until we scan the entire bus with inquiries, go throught this fella...
*/ */
...@@ -1145,11 +1175,9 @@ static void ourdone(struct scsi_cmnd *Cmnd) ...@@ -1145,11 +1175,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
int ok = host_byte(Cmnd->result) == DID_OK; int ok = host_byte(Cmnd->result) == DID_OK;
if (Cmnd->cmnd[0] == 0x12 && ok) { if (Cmnd->cmnd[0] == 0x12 && ok) {
unsigned char *iqd; unsigned char *iqd;
unsigned int iqd_len;
if (Cmnd->use_sg != 0) iqd_len = scsi_rbuf_get(Cmnd, &iqd);
BUG();
iqd = ((unsigned char *)Cmnd->buffer);
/* tags handled in midlayer */ /* tags handled in midlayer */
/* enable sync mode? */ /* enable sync mode? */
...@@ -1163,6 +1191,9 @@ static void ourdone(struct scsi_cmnd *Cmnd) ...@@ -1163,6 +1191,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
if (iqd[7] & 0x20) { if (iqd[7] & 0x20) {
qpti->dev_param[tgt].device_flags |= 0x20; qpti->dev_param[tgt].device_flags |= 0x20;
} }
scsi_rbuf_put(Cmnd, iqd);
qpti->sbits |= (1 << tgt); qpti->sbits |= (1 << tgt);
} else if (!ok) { } else if (!ok) {
qpti->sbits |= (1 << tgt); qpti->sbits |= (1 << tgt);
......
...@@ -27,23 +27,27 @@ ...@@ -27,23 +27,27 @@
* PCI bus. * PCI bus.
*/ */
#define PBM_LOGCLUSTERS 3
#define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
struct pci_controller_info; struct pci_controller_info;
/* This contains the software state necessary to drive a PCI /* This contains the software state necessary to drive a PCI
* controller's IOMMU. * controller's IOMMU.
*/ */
struct pci_iommu_arena {
unsigned long *map;
unsigned int hint;
unsigned int limit;
};
struct pci_iommu { struct pci_iommu {
/* This protects the controller's IOMMU and all /* This protects the controller's IOMMU and all
* streaming buffers underneath. * streaming buffers underneath.
*/ */
spinlock_t lock; spinlock_t lock;
struct pci_iommu_arena arena;
/* IOMMU page table, a linear array of ioptes. */ /* IOMMU page table, a linear array of ioptes. */
iopte_t *page_table; /* The page table itself. */ iopte_t *page_table; /* The page table itself. */
int page_table_sz_bits; /* log2 of ow many pages does it map? */
/* Base PCI memory space address where IOMMU mappings /* Base PCI memory space address where IOMMU mappings
* begin. * begin.
...@@ -62,12 +66,6 @@ struct pci_iommu { ...@@ -62,12 +66,6 @@ struct pci_iommu {
*/ */
unsigned long write_complete_reg; unsigned long write_complete_reg;
/* The lowest used consistent mapping entry. Since
* we allocate consistent maps out of cluster 0 this
* is relative to the beginning of closter 0.
*/
u32 lowest_consistent_map;
/* In order to deal with some buggy third-party PCI bridges that /* In order to deal with some buggy third-party PCI bridges that
* do wrong prefetching, we never mark valid mappings as invalid. * do wrong prefetching, we never mark valid mappings as invalid.
* Instead we point them at this dummy page. * Instead we point them at this dummy page.
...@@ -75,16 +73,6 @@ struct pci_iommu { ...@@ -75,16 +73,6 @@ struct pci_iommu {
unsigned long dummy_page; unsigned long dummy_page;
unsigned long dummy_page_pa; unsigned long dummy_page_pa;
/* If PBM_NCLUSTERS is ever decreased to 4 or lower,
* or if largest supported page_table_sz * 8K goes above
* 2GB, you must increase the size of the type of
* these counters. You have been duly warned. -DaveM
*/
struct {
u16 next;
u16 flush;
} alloc_info[PBM_NCLUSTERS];
/* CTX allocation. */ /* CTX allocation. */
unsigned long ctx_lowest_free; unsigned long ctx_lowest_free;
unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)]; unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
...@@ -102,7 +90,7 @@ struct pci_iommu { ...@@ -102,7 +90,7 @@ struct pci_iommu {
u32 dma_addr_mask; u32 dma_addr_mask;
}; };
extern void pci_iommu_table_init(struct pci_iommu *, int); extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
/* This describes a PCI bus module's streaming buffer. */ /* This describes a PCI bus module's streaming buffer. */
struct pci_strbuf { struct pci_strbuf {
......
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