Commit f901b6bc authored by Marc Kleine-Budde's avatar Marc Kleine-Budde

can: sja1000: fix define conflict on SH

Thias patch fixes a define conflict between the SH architecture and the sja1000
driver:

    drivers/net/can/sja1000/sja1000.h:59:0: warning:
        "REG_SR" redefined [enabled by default]
    arch/sh/include/asm/ptrace_32.h:25:0: note:
         this is the location of the previous definition

A SJA1000_ prefix is added to the offending sja1000 define only, to make a
minimal patch suited for stable. A later patch will add a SJA1000_ prefix to
all defines in sja1000.h.

Cc: linux-stable <stable@vger.kernel.org>
Reported-by: default avatarFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent b175293c
...@@ -348,7 +348,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) ...@@ -348,7 +348,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
*/ */
if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
REG_CR_BASICCAN_INITIAL && REG_CR_BASICCAN_INITIAL &&
(priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) && (priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) &&
(priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL)) (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
flag = 1; flag = 1;
...@@ -360,7 +360,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) ...@@ -360,7 +360,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
* See states on p. 23 of the Datasheet. * See states on p. 23 of the Datasheet.
*/ */
if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL && if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL && priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL &&
priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL) priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
return flag; return flag;
......
...@@ -92,7 +92,7 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val) ...@@ -92,7 +92,7 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
*/ */
spin_lock_irqsave(&priv->cmdreg_lock, flags); spin_lock_irqsave(&priv->cmdreg_lock, flags);
priv->write_reg(priv, REG_CMR, val); priv->write_reg(priv, REG_CMR, val);
priv->read_reg(priv, REG_SR); priv->read_reg(priv, SJA1000_REG_SR);
spin_unlock_irqrestore(&priv->cmdreg_lock, flags); spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
} }
...@@ -502,7 +502,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) ...@@ -502,7 +502,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) { while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
n++; n++;
status = priv->read_reg(priv, REG_SR); status = priv->read_reg(priv, SJA1000_REG_SR);
/* check for absent controller due to hw unplug */ /* check for absent controller due to hw unplug */
if (status == 0xFF && sja1000_is_absent(priv)) if (status == 0xFF && sja1000_is_absent(priv))
return IRQ_NONE; return IRQ_NONE;
...@@ -530,7 +530,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) ...@@ -530,7 +530,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
/* receive interrupt */ /* receive interrupt */
while (status & SR_RBS) { while (status & SR_RBS) {
sja1000_rx(dev); sja1000_rx(dev);
status = priv->read_reg(priv, REG_SR); status = priv->read_reg(priv, SJA1000_REG_SR);
/* check for absent controller */ /* check for absent controller */
if (status == 0xFF && sja1000_is_absent(priv)) if (status == 0xFF && sja1000_is_absent(priv))
return IRQ_NONE; return IRQ_NONE;
......
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
/* SJA1000 registers - manual section 6.4 (Pelican Mode) */ /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
#define REG_MOD 0x00 #define REG_MOD 0x00
#define REG_CMR 0x01 #define REG_CMR 0x01
#define REG_SR 0x02 #define SJA1000_REG_SR 0x02
#define REG_IR 0x03 #define REG_IR 0x03
#define REG_IER 0x04 #define REG_IER 0x04
#define REG_ALC 0x0B #define REG_ALC 0x0B
......
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