Commit f9d2d86d authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Moritz Fischer

dt-bindings: fpga: fpga-region: Convert to sugar syntax

Using overlay sugar syntax makes the DTS files easier to read (and
write).

While at it, fix two build issues:
  - "/dts-v1/" and "/plugin/" must be separate statements.
  - Add a missing closing curly brace.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>
parent 9a8d3cda
...@@ -245,13 +245,10 @@ Base tree contains: ...@@ -245,13 +245,10 @@ Base tree contains:
Overlay contains: Overlay contains:
/dts-v1/ /plugin/; /dts-v1/;
/ { /plugin/;
fragment@0 {
target = <&fpga_region0>; &fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -274,8 +271,6 @@ Overlay contains: ...@@ -274,8 +271,6 @@ Overlay contains:
compatible = "altr,onchipmem-15.1"; compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>; reg = <0x0 0x10000>;
}; };
};
};
}; };
...@@ -371,13 +366,11 @@ Live Device Tree contains: ...@@ -371,13 +366,11 @@ Live Device Tree contains:
}; };
DT Overlay contains: DT Overlay contains:
/dts-v1/ /plugin/;
/ { /dts-v1/;
fragment@0 { /plugin/;
target = <&fpga_region0>;
#address-cells = <1>; &fpga_region0 {
#size-cells = <1>;
__overlay__ {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -390,7 +383,6 @@ fragment@0 { ...@@ -390,7 +383,6 @@ fragment@0 {
#gpio-cells = <0x2>; #gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>; xlnx,gpio-width= <0x6>;
}; };
};
}; };
Device Tree Example: Full Reconfiguration to add PRR's Device Tree Example: Full Reconfiguration to add PRR's
...@@ -402,13 +394,11 @@ This example programs the FPGA to have two regions that can later be partially ...@@ -402,13 +394,11 @@ This example programs the FPGA to have two regions that can later be partially
configured. Each region has its own bridge in the FPGA fabric. configured. Each region has its own bridge in the FPGA fabric.
DT Overlay contains: DT Overlay contains:
/dts-v1/ /plugin/;
/ { /dts-v1/;
fragment@0 { /plugin/;
target = <&fpga_region0>;
#address-cells = <1>; &fpga_region0 {
#size-cells = <1>;
__overlay__ {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -437,8 +427,6 @@ DT Overlay contains: ...@@ -437,8 +427,6 @@ DT Overlay contains:
ranges; ranges;
}; };
}; };
};
};
}; };
Device Tree Example: Partial Reconfiguration Device Tree Example: Partial Reconfiguration
...@@ -451,13 +439,10 @@ differences are that the FPGA is partially reconfigured due to the ...@@ -451,13 +439,10 @@ differences are that the FPGA is partially reconfigured due to the
"partial-fpga-config" boolean and the only bridge that is controlled during "partial-fpga-config" boolean and the only bridge that is controlled during
programming is the FPGA based bridge of fpga_region1. programming is the FPGA based bridge of fpga_region1.
/dts-v1/ /plugin/; /dts-v1/;
/ { /plugin/;
fragment@0 {
target = <&fpga_region1>; &fpga_region1 {
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -472,8 +457,6 @@ programming is the FPGA based bridge of fpga_region1. ...@@ -472,8 +457,6 @@ programming is the FPGA based bridge of fpga_region1.
#gpio-cells = <0x2>; #gpio-cells = <0x2>;
gpio-controller; gpio-controller;
}; };
};
};
}; };
Constraints Constraints
......
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