Commit fa142ff5 authored by Russell King's avatar Russell King Committed by Wim Van Sebroeck

Watchdog: allow orion_wdt to be built for Dove

The watchdog infrastructure in Dove is no different from that in
Orion5x or Kirkwood, so let's enable it for Dove.  The only things
missing are a few register settings in Dove's bridge-regs.h.

Rather than duplicating the same register bit masks for the RSTOUTn_MASK
and BRIDGE_CAUSE registers, move the definitions into the watchdog
driver itself.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
parent 938d0a84
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001 #define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
......
...@@ -21,14 +21,12 @@ ...@@ -21,14 +21,12 @@
#define CPU_RESET 0x00000002 #define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define WDT_RESET_OUT_EN 0x00000002
#define SOFT_RESET_OUT_EN 0x00000004 #define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001 #define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define BRIDGE_INT_TIMER1_CLR (~0x0004)
......
...@@ -18,7 +18,6 @@ ...@@ -18,7 +18,6 @@
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
#define WDT_RESET_OUT_EN 0x0002
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
...@@ -26,8 +25,6 @@ ...@@ -26,8 +25,6 @@
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
#define WDT_INT_REQ 0x0008
#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
......
...@@ -282,7 +282,7 @@ config DAVINCI_WATCHDOG ...@@ -282,7 +282,7 @@ config DAVINCI_WATCHDOG
config ORION_WATCHDOG config ORION_WATCHDOG
tristate "Orion watchdog" tristate "Orion watchdog"
depends on ARCH_ORION5X || ARCH_KIRKWOOD depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE
select WATCHDOG_CORE select WATCHDOG_CORE
help help
Say Y here if to include support for the watchdog timer Say Y here if to include support for the watchdog timer
......
...@@ -38,6 +38,9 @@ ...@@ -38,6 +38,9 @@
#define WDT_IN_USE 0 #define WDT_IN_USE 0
#define WDT_OK_TO_CLOSE 1 #define WDT_OK_TO_CLOSE 1
#define WDT_RESET_OUT_EN BIT(1)
#define WDT_INT_REQ BIT(3)
static bool nowayout = WATCHDOG_NOWAYOUT; static bool nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat = -1; /* module parameter (seconds) */ static int heartbeat = -1; /* module parameter (seconds) */
static unsigned int wdt_max_duration; /* (seconds) */ static unsigned int wdt_max_duration; /* (seconds) */
......
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