Commit fa5270ec authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Vinod Koul

dmaengine: at_xdmac: call at_xdmac_axi_config() on resume path

at_xdmac could be used on SoCs which supports backup mode (where most
of the SoC power, including power to DMA controller, is closed at suspend
time). Thus, on resume, the settings which were previously done need to be
restored. Do the same for axi configuration.

Fixes: f40566f2 ("dmaengine: at_xdmac: add AXI priority support and recommended settings")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20211007111230.2331837-2-claudiu.beznea@microchip.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 1f6a89ef
...@@ -1926,6 +1926,30 @@ static void at_xdmac_free_chan_resources(struct dma_chan *chan) ...@@ -1926,6 +1926,30 @@ static void at_xdmac_free_chan_resources(struct dma_chan *chan)
return; return;
} }
static void at_xdmac_axi_config(struct platform_device *pdev)
{
struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
bool dev_m2m = false;
u32 dma_requests;
if (!atxdmac->layout->axi_config)
return; /* Not supported */
if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
&dma_requests)) {
dev_info(&pdev->dev, "controller in mem2mem mode.\n");
dev_m2m = true;
}
if (dev_m2m) {
at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
} else {
at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
}
}
#ifdef CONFIG_PM #ifdef CONFIG_PM
static int atmel_xdmac_prepare(struct device *dev) static int atmel_xdmac_prepare(struct device *dev)
{ {
...@@ -1975,6 +1999,7 @@ static int atmel_xdmac_resume(struct device *dev) ...@@ -1975,6 +1999,7 @@ static int atmel_xdmac_resume(struct device *dev)
struct at_xdmac *atxdmac = dev_get_drvdata(dev); struct at_xdmac *atxdmac = dev_get_drvdata(dev);
struct at_xdmac_chan *atchan; struct at_xdmac_chan *atchan;
struct dma_chan *chan, *_chan; struct dma_chan *chan, *_chan;
struct platform_device *pdev = container_of(dev, struct platform_device, dev);
int i; int i;
int ret; int ret;
...@@ -1982,6 +2007,8 @@ static int atmel_xdmac_resume(struct device *dev) ...@@ -1982,6 +2007,8 @@ static int atmel_xdmac_resume(struct device *dev)
if (ret) if (ret)
return ret; return ret;
at_xdmac_axi_config(pdev);
/* Clear pending interrupts. */ /* Clear pending interrupts. */
for (i = 0; i < atxdmac->dma.chancnt; i++) { for (i = 0; i < atxdmac->dma.chancnt; i++) {
atchan = &atxdmac->chan[i]; atchan = &atxdmac->chan[i];
...@@ -2007,30 +2034,6 @@ static int atmel_xdmac_resume(struct device *dev) ...@@ -2007,30 +2034,6 @@ static int atmel_xdmac_resume(struct device *dev)
} }
#endif /* CONFIG_PM_SLEEP */ #endif /* CONFIG_PM_SLEEP */
static void at_xdmac_axi_config(struct platform_device *pdev)
{
struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
bool dev_m2m = false;
u32 dma_requests;
if (!atxdmac->layout->axi_config)
return; /* Not supported */
if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
&dma_requests)) {
dev_info(&pdev->dev, "controller in mem2mem mode.\n");
dev_m2m = true;
}
if (dev_m2m) {
at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
} else {
at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
}
}
static int at_xdmac_probe(struct platform_device *pdev) static int at_xdmac_probe(struct platform_device *pdev)
{ {
struct at_xdmac *atxdmac; struct at_xdmac *atxdmac;
......
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