Commit fb6842a7 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'omap-for-v3.8/clock-signed' of...

Merge tag 'omap-for-v3.8/clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/clk

From Tony Lindgren <tony@atomide.com>:

Common clock framework for omap2+ via Paul Walmsley <paul@pwsan.com>:

Convert the OMAP2+ clock code and data to rely on the common
clock framework for internal bookkeeping and the driver API.

Basic test logs for this branch on top of Tony's cleanup-prcm branch
at commit c9d501e5 are here:

http://www.pwsan.com/omap/testlogs/common_clk_devel_3.8_rebase/20121112192516/

However, cleanup-prcm at c9d501e5 does not include some fixes
that are needed for a successful test.  With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:

http://www.pwsan.com/omap/testlogs/TEST_common_clk_devel_3.8_rebase/20121112192300/

which indicate that the series tests cleanly.

N.B. The common clock data addition patches result in many
checkpatch warnings of the form "WARNING: static const char *
array should probably be static const char * const".  However, it
appears that resolving these would require changes to the CCF
itself.  So the resolution of these warnings is being postponed
until that can be coordinated.

These patches result in a ~55KiB increase in runtime kernel memory
usage when booting omap2plus_defconfig kernels.

Conflicts:
	arch/arm/mach-omap2/clock33xx_data.c
	arch/arm/mach-omap2/clock3xxx_data.c
	arch/arm/mach-omap2/clock44xx_data.c

Note that this is based on a merge of the omap-for-v3.8/cleanup-prcm
and omap-for-v3.8/pm as otherwise merged in with the pm changes it
would automatically resolve into a non-booting merge for omap3 as
the smartreflex clock names were changed in the pm branch.

* tag 'omap-for-v3.8/clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits)
  ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP2xxx: clock: drop obsolete clock data
  ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
  ARM: AM33xx: clock: drop obsolete clock data
  ARM: OMAP3xxx: clk: drop obsolete clock data
  ARM: OMAP3: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP44xx: clock: drop obsolete clock data
  ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP: clock: Switch to COMMON clk
  ARM: OMAP2: clock: Add 24xx data using common struct clk
  ARM: OMAP3: clock: Add 3xxx data using common struct clk
  ARM: AM33XX: clock: add clock data in common clock format
  ARM: OMAP4: clock: Add 44xx data using common struct clk
  ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h
  ARM: OMAP: clock: Get rid of some clkdm assocations within clks
  ARM: OMAP2+: clockdomain: bypass clockdomain handling when disabling unused clks
  ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
  ARM: OMAP: clock: Define a function to enable clocks at init
  ...
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 89ab216b 558a0780
...@@ -34,6 +34,7 @@ config ARCH_OMAP2 ...@@ -34,6 +34,7 @@ config ARCH_OMAP2
select CPU_V6 select CPU_V6
select MULTI_IRQ_HANDLER select MULTI_IRQ_HANDLER
select SOC_HAS_OMAP2_SDRC select SOC_HAS_OMAP2_SDRC
select COMMON_CLK
config ARCH_OMAP3 config ARCH_OMAP3
bool "TI OMAP3" bool "TI OMAP3"
...@@ -47,6 +48,7 @@ config ARCH_OMAP3 ...@@ -47,6 +48,7 @@ config ARCH_OMAP3
select PM_OPP if PM select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE select PM_RUNTIME if CPU_IDLE
select SOC_HAS_OMAP2_SDRC select SOC_HAS_OMAP2_SDRC
select COMMON_CLK
select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ARCH_HAS_EHCI if USB_SUPPORT
config ARCH_OMAP4 config ARCH_OMAP4
...@@ -68,6 +70,7 @@ config ARCH_OMAP4 ...@@ -68,6 +70,7 @@ config ARCH_OMAP4
select PM_OPP if PM select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE select PM_RUNTIME if CPU_IDLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ARCH_HAS_EHCI if USB_SUPPORT
select COMMON_CLK
config SOC_OMAP5 config SOC_OMAP5
bool "TI OMAP5" bool "TI OMAP5"
...@@ -77,6 +80,7 @@ config SOC_OMAP5 ...@@ -77,6 +80,7 @@ config SOC_OMAP5
select CPU_V7 select CPU_V7
select HAVE_SMP select HAVE_SMP
select SOC_HAS_REALTIME_COUNTER select SOC_HAS_REALTIME_COUNTER
select COMMON_CLK
comment "OMAP Core Type" comment "OMAP Core Type"
depends on ARCH_OMAP2 depends on ARCH_OMAP2
...@@ -111,6 +115,7 @@ config SOC_AM33XX ...@@ -111,6 +115,7 @@ config SOC_AM33XX
select ARM_CPU_SUSPEND if PM select ARM_CPU_SUSPEND if PM
select CPU_V7 select CPU_V7
select MULTI_IRQ_HANDLER select MULTI_IRQ_HANDLER
select COMMON_CLK
config OMAP_PACKAGE_ZAF config OMAP_PACKAGE_ZAF
bool bool
......
...@@ -158,17 +158,17 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o ...@@ -158,17 +158,17 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
......
This diff is collapsed.
...@@ -38,62 +38,88 @@ ...@@ -38,62 +38,88 @@
/* Private functions */ /* Private functions */
static int _apll96_enable(struct clk *clk) /**
* omap2xxx_clk_apll_locked - is the APLL locked?
* @hw: struct clk_hw * of the APLL to check
*
* If the APLL IP block referred to by @hw indicates that it's locked,
* return true; otherwise, return false.
*/
static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 r, apll_mask;
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
return ((r & apll_mask) == apll_mask) ? true : false;
}
int omap2_clk_apll96_enable(struct clk_hw *hw)
{ {
return omap2xxx_cm_apll96_enable(); return omap2xxx_cm_apll96_enable();
} }
static int _apll54_enable(struct clk *clk) int omap2_clk_apll54_enable(struct clk_hw *hw)
{ {
return omap2xxx_cm_apll54_enable(); return omap2xxx_cm_apll54_enable();
} }
static void _apll96_allow_idle(struct clk *clk) static void _apll96_allow_idle(struct clk_hw_omap *clk)
{ {
omap2xxx_cm_set_apll96_auto_low_power_stop(); omap2xxx_cm_set_apll96_auto_low_power_stop();
} }
static void _apll96_deny_idle(struct clk *clk) static void _apll96_deny_idle(struct clk_hw_omap *clk)
{ {
omap2xxx_cm_set_apll96_disable_autoidle(); omap2xxx_cm_set_apll96_disable_autoidle();
} }
static void _apll54_allow_idle(struct clk *clk) static void _apll54_allow_idle(struct clk_hw_omap *clk)
{ {
omap2xxx_cm_set_apll54_auto_low_power_stop(); omap2xxx_cm_set_apll54_auto_low_power_stop();
} }
static void _apll54_deny_idle(struct clk *clk) static void _apll54_deny_idle(struct clk_hw_omap *clk)
{ {
omap2xxx_cm_set_apll54_disable_autoidle(); omap2xxx_cm_set_apll54_disable_autoidle();
} }
static void _apll96_disable(struct clk *clk) void omap2_clk_apll96_disable(struct clk_hw *hw)
{ {
omap2xxx_cm_apll96_disable(); omap2xxx_cm_apll96_disable();
} }
static void _apll54_disable(struct clk *clk) void omap2_clk_apll54_disable(struct clk_hw *hw)
{ {
omap2xxx_cm_apll54_disable(); omap2xxx_cm_apll54_disable();
} }
/* Public data */ unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
}
const struct clkops clkops_apll96 = { unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
.enable = _apll96_enable, unsigned long parent_rate)
.disable = _apll96_disable, {
.allow_idle = _apll96_allow_idle, return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
.deny_idle = _apll96_deny_idle, }
};
const struct clkops clkops_apll54 = { /* Public data */
.enable = _apll54_enable, const struct clk_hw_omap_ops clkhwops_apll54 = {
.disable = _apll54_disable,
.allow_idle = _apll54_allow_idle, .allow_idle = _apll54_allow_idle,
.deny_idle = _apll54_deny_idle, .deny_idle = _apll54_deny_idle,
}; };
const struct clk_hw_omap_ops clkhwops_apll96 = {
.allow_idle = _apll96_allow_idle,
.deny_idle = _apll96_deny_idle,
};
/* Public functions */ /* Public functions */
u32 omap2xxx_get_apll_clkin(void) u32 omap2xxx_get_apll_clkin(void)
......
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
* instead. Add some mechanism to optionally enter this mode. * instead. Add some mechanism to optionally enter this mode.
*/ */
static void _allow_idle(struct clk *clk) static void _allow_idle(struct clk_hw_omap *clk)
{ {
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
...@@ -43,7 +43,7 @@ static void _allow_idle(struct clk *clk) ...@@ -43,7 +43,7 @@ static void _allow_idle(struct clk *clk)
* *
* Disable DPLL automatic idle control. No return value. * Disable DPLL automatic idle control. No return value.
*/ */
static void _deny_idle(struct clk *clk) static void _deny_idle(struct clk_hw_omap *clk)
{ {
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
...@@ -53,9 +53,7 @@ static void _deny_idle(struct clk *clk) ...@@ -53,9 +53,7 @@ static void _deny_idle(struct clk *clk)
/* Public data */ /* Public data */
const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
const struct clkops clkops_omap2xxx_dpll_ops = {
.allow_idle = _allow_idle, .allow_idle = _allow_idle,
.deny_idle = _deny_idle, .deny_idle = _deny_idle,
}; };
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
* (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
* during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
*/ */
static struct clk *dpll_core_ck; static struct clk_hw_omap *dpll_core_ck;
/** /**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
...@@ -105,13 +105,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) ...@@ -105,13 +105,16 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
} }
unsigned long omap2_dpllcore_recalc(struct clk *clk) unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{ {
return omap2xxx_clk_get_core_rate(); return omap2xxx_clk_get_core_rate();
} }
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{ {
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 cur_rate, low, mult, div, valid_rate, done_rate;
u32 bypass = 0; u32 bypass = 0;
struct prcm_config tmpset; struct prcm_config tmpset;
...@@ -189,8 +192,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) ...@@ -189,8 +192,8 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
* statically defined, this code may need to change to increment some * statically defined, this code may need to change to increment some
* kind of use count on dpll_ck. * kind of use count on dpll_ck.
*/ */
void omap2xxx_clkt_dpllcore_init(struct clk *clk) void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
{ {
WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
dpll_core_ck = clk; dpll_core_ck = to_clk_hw_omap(hw);
} }
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
* clk_enable/clk_disable()-based usecounting for osc_ck should be * clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting. * replaced with autoidle-based usecounting.
*/ */
static int omap2_enable_osc_ck(struct clk *clk) int omap2_enable_osc_ck(struct clk_hw *clk)
{ {
u32 pcc; u32 pcc;
...@@ -53,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk) ...@@ -53,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk)
* clk_enable/clk_disable()-based usecounting for osc_ck should be * clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting. * replaced with autoidle-based usecounting.
*/ */
static void omap2_disable_osc_ck(struct clk *clk) void omap2_disable_osc_ck(struct clk_hw *clk)
{ {
u32 pcc; u32 pcc;
...@@ -62,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk) ...@@ -62,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk)
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
} }
const struct clkops clkops_oscck = { unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
.enable = omap2_enable_osc_ck, unsigned long parent_rate)
.disable = omap2_disable_osc_ck,
};
unsigned long omap2_osc_clk_recalc(struct clk *clk)
{ {
return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
} }
...@@ -40,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void) ...@@ -40,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void)
return div; return div;
} }
unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{ {
return clk->parent->rate / omap2xxx_get_sysclkdiv(); return parent_rate / omap2xxx_get_sysclkdiv();
} }
...@@ -59,7 +59,8 @@ static unsigned long sys_ck_rate; ...@@ -59,7 +59,8 @@ static unsigned long sys_ck_rate;
* *
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/ */
unsigned long omap2_table_mpu_recalc(struct clk *clk) unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{ {
return curr_prcm_set->mpu_speed; return curr_prcm_set->mpu_speed;
} }
...@@ -71,7 +72,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) ...@@ -71,7 +72,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates. * just uses the ARM rates.
*/ */
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{ {
const struct prcm_config *ptr; const struct prcm_config *ptr;
long highest_rate; long highest_rate;
...@@ -94,7 +96,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) ...@@ -94,7 +96,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
} }
/* Sets basic clocks based on the specified rate */ /* Sets basic clocks based on the specified rate */
int omap2_select_table_rate(struct clk *clk, unsigned long rate) int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{ {
u32 cur_rate, done_rate, bypass = 0, tmp; u32 cur_rate, done_rate, bypass = 0, tmp;
const struct prcm_config *prcm; const struct prcm_config *prcm;
......
...@@ -45,8 +45,10 @@ ...@@ -45,8 +45,10 @@
* Program the DPLL M2 divider with the rounded target rate. Returns * Program the DPLL M2 divider with the rounded target rate. Returns
* -EINVAL upon error, or 0 upon success. * -EINVAL upon error, or 0 upon success.
*/ */
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{ {
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 new_div = 0; u32 new_div = 0;
u32 unlock_dll = 0; u32 unlock_dll = 0;
u32 c; u32 c;
...@@ -64,7 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -64,7 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
return -EINVAL; return -EINVAL;
sdrcrate = __clk_get_rate(sdrc_ick_p); sdrcrate = __clk_get_rate(sdrc_ick_p);
clkrate = __clk_get_rate(clk); clkrate = __clk_get_rate(hw->clk);
if (rate > clkrate) if (rate > clkrate)
sdrcrate <<= ((rate / clkrate) >> 1); sdrcrate <<= ((rate / clkrate) >> 1);
else else
...@@ -113,8 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -113,8 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0); 0, 0, 0, 0);
clk->rate = rate;
return 0; return 0;
} }
This diff is collapsed.
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/clk.h> #include <linux/clk-provider.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/div64.h> #include <asm/div64.h>
...@@ -76,7 +76,7 @@ ...@@ -76,7 +76,7 @@
* (assuming that it is counting N upwards), or -2 if the enclosing loop * (assuming that it is counting N upwards), or -2 if the enclosing loop
* should skip to the next iteration (again assuming N is increasing). * should skip to the next iteration (again assuming N is increasing).
*/ */
static int _dpll_test_fint(struct clk *clk, u8 n) static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
{ {
struct dpll_data *dd; struct dpll_data *dd;
long fint, fint_min, fint_max; long fint, fint_min, fint_max;
...@@ -85,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) ...@@ -85,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data; dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */ /* DPLL divider must result in a valid jitter correction val */
fint = __clk_get_rate(__clk_get_parent(clk)) / n; fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */ /* Should not be called for OMAP2, so warn if it is called */
...@@ -186,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, ...@@ -186,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
} }
/* Public functions */ /* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw)
void omap2_init_dpll_parent(struct clk *clk)
{ {
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 v; u32 v;
struct dpll_data *dd; struct dpll_data *dd;
dd = clk->dpll_data; dd = clk->dpll_data;
if (!dd) if (!dd)
return; return -EINVAL;
v = __raw_readl(dd->control_reg); v = __raw_readl(dd->control_reg);
v &= dd->enable_mask; v &= dd->enable_mask;
...@@ -204,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk) ...@@ -204,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS || if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS) v == OMAP2XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass); return 1;
} else if (cpu_is_omap34xx()) { } else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS || if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS) v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass); return 1;
} else if (soc_is_am33xx() || cpu_is_omap44xx()) { } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS || if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS) v == OMAP4XXX_EN_DPLL_MNBYPASS)
clk_reparent(clk, dd->clk_bypass); return 1;
} }
return; return 0;
} }
/** /**
...@@ -232,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk) ...@@ -232,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
* if the clock @clk is not a DPLL. * if the clock @clk is not a DPLL.
*/ */
u32 omap2_get_dpll_rate(struct clk *clk) unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
{ {
long long dpll_clk; long long dpll_clk;
u32 dpll_mult, dpll_div, v; u32 dpll_mult, dpll_div, v;
...@@ -288,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk) ...@@ -288,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
* (expensive) function again. Returns ~0 if the target rate cannot * (expensive) function again. Returns ~0 if the target rate cannot
* be rounded, or the rounded rate upon success. * be rounded, or the rounded rate upon success.
*/ */
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
unsigned long *parent_rate)
{ {
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int m, n, r, scaled_max_m; int m, n, r, scaled_max_m;
unsigned long scaled_rt_rp; unsigned long scaled_rt_rp;
unsigned long new_rate = 0; unsigned long new_rate = 0;
...@@ -303,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) ...@@ -303,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
dd = clk->dpll_data; dd = clk->dpll_data;
ref_rate = __clk_get_rate(dd->clk_ref); ref_rate = __clk_get_rate(dd->clk_ref);
clk_name = __clk_get_name(clk); clk_name = __clk_get_name(hw->clk);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
clk_name, target_rate); clk_name, target_rate);
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#undef DEBUG #undef DEBUG
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/clk.h> #include <linux/clk-provider.h>
#include <linux/io.h> #include <linux/io.h>
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
/* Private functions */ /* Private functions */
/* XXX */ /* XXX */
void omap2_clkt_iclk_allow_idle(struct clk *clk) void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
{ {
u32 v, r; u32 v, r;
...@@ -35,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk) ...@@ -35,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk)
} }
/* XXX */ /* XXX */
void omap2_clkt_iclk_deny_idle(struct clk *clk) void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
{ {
u32 v, r; u32 v, r;
...@@ -48,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) ...@@ -48,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk)
/* Public data */ /* Public data */
const struct clkops clkops_omap2_iclk_dflt_wait = { const struct clk_hw_omap_ops clkhwops_iclk = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
.allow_idle = omap2_clkt_iclk_allow_idle, .allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle, .deny_idle = omap2_clkt_iclk_deny_idle,
}; };
const struct clkops clkops_omap2_iclk_dflt = { const struct clk_hw_omap_ops clkhwops_iclk_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.allow_idle = omap2_clkt_iclk_allow_idle, .allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle, .deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = omap2_clk_dflt_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
}; };
const struct clkops clkops_omap2_iclk_idle_only = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
const struct clkops clkops_omap2_mdmclk_dflt_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
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...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
* passes back the correct CM_IDLEST register address for I2CHS * passes back the correct CM_IDLEST register address for I2CHS
* modules. No return value. * modules. No return value.
*/ */
static void omap2430_clk_i2chs_find_idlest(struct clk *clk, static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
void __iomem **idlest_reg, void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_bit,
u8 *idlest_val) u8 *idlest_val)
...@@ -51,9 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, ...@@ -51,9 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
} }
/* 2430 I2CHS has non-standard IDLEST register */ /* 2430 I2CHS has non-standard IDLEST register */
const struct clkops clkops_omap2430_i2chs_wait = { const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest, .find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion, .find_companion = omap2_clk_dflt_find_companion,
}; };
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "cm.h" #include "cm.h"
#include "cm-regbits-24xx.h" #include "cm-regbits-24xx.h"
struct clk_hw *dclk_hw;
/* /*
* Omap24xx specific clock functions * Omap24xx specific clock functions
*/ */
......
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...@@ -8,6 +8,6 @@ ...@@ -8,6 +8,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw);
#endif #endif
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...@@ -108,6 +108,7 @@ extern void omap2xxx_cm_apll96_disable(void); ...@@ -108,6 +108,7 @@ extern void omap2xxx_cm_apll96_disable(void);
/* CM_CLKSEL_GFX */ /* CM_CLKSEL_GFX */
#define OMAP_CLKSEL_GFX_SHIFT 0 #define OMAP_CLKSEL_GFX_SHIFT 0
#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) #define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
#define OMAP_CLKSEL_GFX_WIDTH 3
/* CM_ICLKEN_GFX */ /* CM_ICLKEN_GFX */
#define OMAP_EN_GFX_SHIFT 0 #define OMAP_EN_GFX_SHIFT 0
......
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