Commit fb7267ac authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
  Blackfin arch: use a less common define name in BF549
  Blackfin arch: Add missing definitions for BF561
  Blackfin arch: reclaim a few bytes from the end of our init section
  Blackfin arch: fix libata data struct member from irq_type to irq_flags
  Blackfin arch: Do not pollute name space used in linux-2.6.x/sound
  Blackfin arch: Fix bug set correct baud for spi mmc and enable SPI after DMA.
  Blackfin arch: update board defconfig files according to latest information from ADI datasheet
  Blackfin arch: ensure that speculative loads of bad pointers don't cause us to do bad things.
  Blackfin arch: Add missing definitions of BF54x
  Blackfin arch: Fix random crash issue found by Michael.
  Blackfin arch: fix bug: tell users if the kernel is recovering from a fault condition
  Blackfin arch: add support for checking/clearing overruns in generic purpose Timer API
  Blackfin arch: cleanup arch/blackfin/kernel/traps.c handling code.
  Blackfin arch: Apply Bluetchnix vendor patch provided by Harald Krapfenbauer
  Blackfin arch: fix bug BlueTechnix CM-BF537 board config uses wrong IRQ for net2272 driver
  Blackfin arch: fix bug: kernel prints out error message twice
  Blackfin arch: add NFC driver support in BF527-EZKIT board
  Blackfin arch: Added support for HV Sistemas H8606 board
parents 2d175d43 2ea4649b
......@@ -295,6 +295,12 @@ config PNAV10
help
PNAV 1.0 board Support.
config H8606_HVSISTEMAS
bool "HV Sistemas H8606"
depends on (BF532)
help
HV Sistemas H8606 board support.
config GENERIC_BOARD
bool "Custom"
depends on (BF537 || BF536 \
......@@ -317,7 +323,8 @@ config MEM_MT48LC64M4A2FB_7E
config MEM_MT48LC16M16A2TG_75
bool
depends on (BFIN533_EZKIT || BFIN561_EZKIT \
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM)
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
|| H8606_HVSISTEMAS)
default y
config MEM_MT48LC32M8A2_75
......@@ -366,7 +373,7 @@ config CLKIN_HZ
int "Crystal Frequency in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT)
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
help
......@@ -404,6 +411,7 @@ config VCO_MULT
default "20" if BFIN537_BLUETECHNIX_CM
default "20" if BFIN561_BLUETECHNIX_CM
default "20" if BFIN561_EZKIT
default "16" if H8606_HVSISTEMAS
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
......@@ -440,6 +448,7 @@ config SCLK_DIV
default 4 if BFIN537_BLUETECHNIX_CM
default 4 if BFIN561_BLUETECHNIX_CM
default 5 if BFIN561_EZKIT
default 3 if H8606_HVSISTEMAS
help
This sets the frequency of the system clock (including SDRAM or DDR).
This can be between 1 and 15
......@@ -492,11 +501,13 @@ config MEM_SIZE
default 64 if BFIN561_EZKIT
default 128 if BFIN533_STAMP
default 64 if PNAV10
default 32 if H8606_HVSISTEMAS
config MEM_ADD_WIDTH
int "SDRAM Memory Address Width"
default 9 if BFIN533_EZKIT
default 9 if BFIN561_EZKIT
default 9 if H8606_HVSISTEMAS
default 10 if BFIN527_EZKIT
default 10 if BFIN537_STAMP
default 11 if BFIN533_STAMP
......
......@@ -244,7 +244,7 @@ CONFIG_CLKIN_HZ=25000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
......@@ -198,7 +198,7 @@ CONFIG_CLKIN_HZ=27000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=750000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
......@@ -199,7 +199,7 @@ CONFIG_CLKIN_HZ=11059200
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=750000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
......@@ -206,7 +206,7 @@ CONFIG_CLKIN_HZ=25000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
This diff is collapsed.
......@@ -243,7 +243,7 @@ CONFIG_CLKIN_HZ=30000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
......@@ -204,7 +204,7 @@ CONFIG_CLKIN_HZ=24576000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......
......@@ -55,8 +55,10 @@ ENTRY(_ret_from_fork)
/* do a 'fake' RTI by jumping to [RETI]
* to avoid clearing supervisor mode in child
*/
r0 = [sp + PT_PC];
[sp + PT_P0] = r0;
RESTORE_ALL_SYS
p0 = reti;
jump (p0);
ENDPROC(_ret_from_fork)
......
......@@ -129,4 +129,18 @@ ENTRY(_atomic_xor32)
rts;
ENDPROC (_atomic_ior32)
.align 16
/*
* safe_user_instruction
* Four NOPS are enough to allow the pipeline to speculativily load
* execute anything it wants. After that, things have gone bad, and
* we are stuck - so panic. Since we might be in user space, we can't
* call panic, so just cause a unhandled exception, this should cause
* a dump of the trace buffer so we can tell were we are, and a reboot
*/
ENTRY(_safe_user_instruction)
NOP; NOP; NOP; NOP;
EXCPT 0x4;
ENDPROC(_safe_user_instruction)
ENTRY(_fixed_code_end)
......@@ -20,8 +20,7 @@
#else
# define tassert(expr) \
if (!(expr)) \
printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", \
__FILE__, __func__, __LINE__);
printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
#endif
#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
......@@ -70,7 +69,7 @@ static volatile GPTIMER_group_regs *const group_regs[BFIN_TIMER_NUM_GROUP] =
#endif
};
static uint32_t const dis_mask[MAX_BLACKFIN_GPTIMERS] =
static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] =
{
TIMER_STATUS_TRUN0,
TIMER_STATUS_TRUN1,
......@@ -90,7 +89,27 @@ static uint32_t const dis_mask[MAX_BLACKFIN_GPTIMERS] =
#endif
};
static uint32_t const irq_mask[MAX_BLACKFIN_GPTIMERS] =
static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] =
{
TIMER_STATUS_TOVF0,
TIMER_STATUS_TOVF1,
TIMER_STATUS_TOVF2,
#if (MAX_BLACKFIN_GPTIMERS > 3)
TIMER_STATUS_TOVF3,
TIMER_STATUS_TOVF4,
TIMER_STATUS_TOVF5,
TIMER_STATUS_TOVF6,
TIMER_STATUS_TOVF7,
#endif
#if (MAX_BLACKFIN_GPTIMERS > 8)
TIMER_STATUS_TOVF8,
TIMER_STATUS_TOVF9,
TIMER_STATUS_TOVF10,
TIMER_STATUS_TOVF11,
#endif
};
static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
{
TIMER_STATUS_TIMIL0,
TIMER_STATUS_TIMIL1,
......@@ -165,17 +184,31 @@ EXPORT_SYMBOL(set_gptimer_status);
uint16_t get_gptimer_intr(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & irq_mask[timer_id]) ? 1 : 0;
return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]) ? 1 : 0;
}
EXPORT_SYMBOL(get_gptimer_intr);
void clear_gptimer_intr(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
group_regs[BFIN_TIMER_OCTET(timer_id)]->status = irq_mask[timer_id];
group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
}
EXPORT_SYMBOL(clear_gptimer_intr);
uint16_t get_gptimer_over(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]) ? 1 : 0;
}
EXPORT_SYMBOL(get_gptimer_over);
void clear_gptimer_over(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
}
EXPORT_SYMBOL(clear_gptimer_over);
void set_gptimer_config(int timer_id, uint16_t config)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
......@@ -214,7 +247,7 @@ void disable_gptimers(uint16_t mask)
}
for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
if (mask & (1 << i))
group_regs[BFIN_TIMER_OCTET(i)]->status |= dis_mask[i];
group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i];
SSYNC();
}
EXPORT_SYMBOL(disable_gptimers);
......
......@@ -316,6 +316,15 @@ void __init setup_arch(char **cmdline_p)
init_leds();
_bfin_swrst = bfin_read_SWRST();
if (_bfin_swrst & RESET_DOUBLE)
printk(KERN_INFO "Recovering from Double Fault event\n");
else if (_bfin_swrst & RESET_WDOG)
printk(KERN_INFO "Recovering from Watchdog event\n");
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
if (bfin_compiled_revid() == 0xffff)
printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
......@@ -402,8 +411,6 @@ void __init setup_arch(char **cmdline_p)
if (l1_length > L1_DATA_A_LENGTH)
panic("L1 data memory overflow\n");
_bfin_swrst = bfin_read_SWRST();
/* Copy atomic sequences to their fixed location, and sanity check that
these locations are the ones that we advertise to userspace. */
memcpy((void *)FIXED_CODE_START, &fixed_code_start,
......@@ -424,6 +431,8 @@ void __init setup_arch(char **cmdline_p)
!= ATOMIC_AND32 - FIXED_CODE_START);
BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
!= ATOMIC_XOR32 - FIXED_CODE_START);
BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
!= SAFE_USER_INSTRUCTION - FIXED_CODE_START);
init_exception_vectors();
bf53x_cache_init();
......
This diff is collapsed.
......@@ -172,9 +172,14 @@ SECTIONS
__ebss_b_l1 = .;
}
___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
/* Force trailing alignment of our init section so that when we
* free our init memory, we don't leave behind a partial page.
*/
. = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
. = ALIGN(PAGE_SIZE);
___init_end = .;
.bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) :
.bss :
{
. = ALIGN(4);
___bss_start = .;
......
......@@ -41,9 +41,11 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb_sl811.h>
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
#include <asm/nand.h>
#include <linux/spi/ad7877.h>
/*
......@@ -102,6 +104,53 @@ void __exit bfin_isp1761_exit(void)
arch_initcall(bfin_isp1761_init);
#endif
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
.name = "Linux Kernel",
.offset = 0,
.size = 4 * SIZE_1M,
},
{
.name = "File System",
.offset = 4 * SIZE_1M,
.size = (256 - 4) * SIZE_1M,
},
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
.rd_dly = 3,
.wr_dly = 3,
};
static struct resource bf5xx_nand_resources[] = {
{
.start = NFC_CTL,
.end = NFC_DATA_RD + 2,
.flags = IORESOURCE_MEM,
},
{
.start = CH_NFC,
.end = CH_NFC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bf5xx_nand_device = {
.name = "bf5xx-nand",
.id = 0,
.num_resources = ARRAY_SIZE(bf5xx_nand_resources),
.resource = bf5xx_nand_resources,
.dev = {
.platform_data = &bf5xx_nand_platform,
},
};
#endif
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
static struct resource bfin_pcmcia_cf_resources[] = {
{
......@@ -650,6 +699,10 @@ static struct platform_device bfin_pata_device = {
#endif
static struct platform_device *stamp_devices[] __initdata = {
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
&bf5xx_nand_device,
#endif
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
&bfin_pcmcia_cf_device,
#endif
......
/*
* File: arch/blackfin/mach-bf533/H8606.c
* Based on: arch/blackfin/mach-bf533/stamp.c
* Author: Javier Herrero <jherrero@hvsistemas.es>
*
* Created: 2007
* Description: Board Info File for the HV Sistemas H8606 board
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2006 Analog Devices Inc
* Copyright 2007 HV Sistemas S.L.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb_isp1362.h>
#endif
#include <linux/pata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
/*
* Name the Board for the /proc/cpuinfo
*/
const char bfin_board_name[] = "HV Sistemas H8606";
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
/*
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource dm9000_resources[] = {
[0] = {
.start = 0x20300000,
.end = 0x20300000 + 8,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
},
};
static struct platform_device dm9000_device = {
.id = 0,
.name = "dm9000",
.resource = dm9000_resources,
.num_resources = ARRAY_SIZE(dm9000_resources),
};
#endif
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
static struct resource smc91x_resources[] = {
{
.name = "smc91x-regs",
.start = 0x20300300,
.end = 0x20300300 + 16,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PROG_INTB,
.end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
}, {
/*
* denotes the flag pin and is used directly if
* CONFIG_IRQCHIP_DEMUX_GPIO is defined.
*/
.start = IRQ_PF7,
.end = IRQ_PF7,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
static struct resource net2272_bfin_resources[] = {
{
.start = 0x20300000,
.end = 0x20300000 + 0x100,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device net2272_bfin_device = {
.name = "net2272",
.id = -1,
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
.resource = net2272_bfin_resources,
};
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
.name = "bootloader",
.size = 0x00060000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
.name = "kernel",
.size = 0x100000,
.offset = 0x60000
}, {
.name = "file system",
.size = 0x6a0000,
.offset = 0x00160000,
}
};
static struct flash_platform_data bfin_spi_flash_data = {
.name = "m25p80",
.parts = bfin_spi_flash_partitions,
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
.type = "m25p64",
};
/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.ctl_reg = 0x1000,
.enable_dma = 1, /* use dma transfer with this chip*/
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.ctl_reg = 0x1000,
.enable_dma = 0,
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_PBX)
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
.ctl_reg = 0x1c04,
.enable_dma = 0,
.bits_per_word = 8,
.cs_change_per_word = 1,
};
#endif
/* Notice: for blackfin, the speed_hz is the value of register
* SPI_BAUD, not the real baudrate */
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
/* the modalias must be the same as spi device driver name */
.modalias = "m25p80", /* Name of spi_driver for this device */
/* this value is the baudrate divisor */
.max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
.bus_num = 0, /* Framework bus number */
.chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */
.bus_num = 1, /* Framework bus number */
.chip_select = 1, /* Framework chip select. */
.platform_data = NULL, /* No spi_driver specific config */
.controller_data = &spi_adc_chip_info,
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
{
.modalias = "ad1836-spi",
.max_speed_hz = 16,
.bus_num = 1,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.controller_data = &ad1836_spi_chip_info,
},
#endif
#if defined(CONFIG_PBX)
{
.modalias = "fxs-spi",
.max_speed_hz = 4,
.bus_num = 1,
.chip_select = 3,
.controller_data = &spi_si3xxx_chip_info,
},
{
.modalias = "fxo-spi",
.max_speed_hz = 4,
.bus_num = 1,
.chip_select = 2,
.controller_data = &spi_si3xxx_chip_info,
},
#endif
};
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
[0] = {
.start = SPI0_REGBASE,
.end = SPI0_REGBASE + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CH_SPI,
.end = CH_SPI,
.flags = IORESOURCE_IRQ,
}
};
/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
.num_chipselect = 8,
.enable_dma = 1, /* master has the ability to do dma transfer */
};
static struct platform_device bfin_spi0_device = {
.name = "bfin-spi",
.id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource,
.dev = {
.platform_data = &bfin_spi0_info, /* Passed to driver */
},
};
#endif /* spi master and devices */
#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
static struct platform_device bfin_fb_device = {
.name = "bf537-fb",
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device bfin_uart_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart_resources),
.resource = bfin_uart_resources,
};
#endif
static struct platform_device *stamp_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
&dm9000_device,
#endif
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
&smc91x_device,
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
&net2272_bfin_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
};
static int __init H8606_init(void)
{
printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif
return 0;
}
arch_initcall(H8606_init);
\ No newline at end of file
......@@ -6,3 +6,4 @@ obj-$(CONFIG_GENERIC_BOARD) += generic_board.o
obj-$(CONFIG_BFIN533_STAMP) += stamp.o
obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
......@@ -46,7 +46,7 @@ const char bfin_board_name[] = "Bluetechnix CM BF533";
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
.name = "bootloader",
......@@ -76,12 +76,15 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
.bits_per_word = 8,
};
#endif
/* SPI ADC chip */
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
......@@ -90,7 +93,15 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
};
#endif
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
.enable_dma = 1,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
/* the modalias must be the same as spi device driver name */
.modalias = "m25p80", /* Name of spi_driver for this device */
......@@ -100,7 +111,11 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
}, {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
......@@ -108,6 +123,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.platform_data = NULL, /* No spi_driver specific config */
.controller_data = &spi_adc_chip_info,
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
{
.modalias = "ad1836-spi",
......@@ -117,6 +134,27 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad1836_spi_chip_info,
},
#endif
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
{
.modalias = "spi_mmc_dummy",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 0,
.platform_data = NULL,
.controller_data = &spi_mmc_chip_info,
.mode = SPI_MODE_3,
},
{
.modalias = "spi_mmc",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
.platform_data = NULL,
.controller_data = &spi_mmc_chip_info,
.mode = SPI_MODE_3,
},
#endif
};
/* SPI (0) */
......
......@@ -218,7 +218,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
{
.modalias = "spi_mmc_dummy",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 0,
.platform_data = NULL,
......@@ -227,7 +227,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
{
.modalias = "spi_mmc",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
.platform_data = NULL,
......
......@@ -281,8 +281,8 @@ static struct resource net2272_bfin_resources[] = {
.end = 0x20200000 + 0x100,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF7,
.end = IRQ_PF7,
.start = IRQ_PH14,
.end = IRQ_PH14,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
......
......@@ -450,7 +450,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
{
.modalias = "spi_mmc_dummy",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 0,
.platform_data = NULL,
......@@ -459,7 +459,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
{
.modalias = "spi_mmc",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
.platform_data = NULL,
......@@ -612,7 +612,7 @@ static struct platform_device bfin_sport1_uart_device = {
static struct pata_platform_info bfin_pata_platform_data = {
.ioport_shift = 1,
.irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
.irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
};
static struct resource bfin_pata_resources[] = {
......
......@@ -917,7 +917,7 @@ ENTRY(_ex_table)
.long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
.long _ex_replaceable /* 0x02 - User Defined */
.long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
.long _ex_replaceable /* 0x04 - User Defined */
.long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
.long _ex_replaceable /* 0x05 - User Defined */
.long _ex_replaceable /* 0x06 - User Defined */
.long _ex_replaceable /* 0x07 - User Defined */
......
......@@ -80,6 +80,7 @@ extern int atomic_sub32(void);
extern int atomic_ior32(void);
extern int atomic_and32(void);
extern int atomic_xor32(void);
extern void safe_user_instruction(void);
extern void sigreturn_stub(void);
extern void *l1_data_A_sram_alloc(size_t);
......
......@@ -17,4 +17,6 @@
#define ATOMIC_SEQS_END 0x480
#define FIXED_CODE_END 0x480
#define SAFE_USER_INSTRUCTION 0x480
#define FIXED_CODE_END 0x490
......@@ -197,6 +197,8 @@ uint32_t get_gptimer_period (int timer_id);
uint32_t get_gptimer_count (int timer_id);
uint16_t get_gptimer_intr (int timer_id);
void clear_gptimer_intr (int timer_id);
uint16_t get_gptimer_over (int timer_id);
void clear_gptimer_over (int timer_id);
void set_gptimer_config (int timer_id, uint16_t config);
uint16_t get_gptimer_config (int timer_id);
void set_gptimer_pulse_hi (int timer_id);
......
......@@ -1718,55 +1718,55 @@
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */
#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */
#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */
#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */
#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
#define nBDR 0x0
#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
#define HOST_CNTR_nHOST_EN 0x0
#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
#define HOST_CNTR_nHOST_END 0x0
#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
#define HOST_CNTR_nDATA_SIZE 0x0
#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
#define HOST_CNTR_nHOST_RST 0x0
#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
#define HOST_CNTR_nHRDY_OVR 0x0
#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
#define HOST_CNTR_nINT_MODE 0x0
#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
#define HOST_CNTR_ nBT_EN 0x0
#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
#define HOST_CNTR_nEHW 0x0
#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
#define HOST_CNTR_nEHR 0x0
#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
#define HOST_CNTR_nBDR 0x0
/* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */
#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */
#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */
#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */
#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
#define nBTE 0x0
#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
#define nHOSTRD_DONE 0x0
#define HOST_STAT_READY 0x1 /* DMA Ready */
#define HOST_STAT_nREADY 0x0
#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
#define HOST_STAT_nFIFOFULL 0x0
#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
#define HOST_STAT_nFIFOEMPTY 0x0
#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
#define HOST_STAT_nCOMPLETE 0x0
#define HOST_STAT_HSHK 0x10 /* Host Handshake */
#define HOST_STAT_nHSHK 0x0
#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
#define HOST_STAT_nTIMEOUT 0x0
#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
#define HOST_STAT_nHIRQ 0x0
#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
#define HOST_STAT_nALLOW_CNFG 0x0
#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
#define HOST_STAT_nDMA_DIR 0x0
#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
#define HOST_STAT_nBTE 0x0
#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
#define HOST_STAT_nHOSTRD_DONE 0x0
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for CNT_CONFIG */
......
......@@ -35,7 +35,6 @@
#define MAX_BLACKFIN_DMA_CHANNEL 16
#define CH_PPI 0 /* PPI receive/transmit or NFC */
#define CH_NFC 0 /* PPI receive/transmit or NFC */
#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
......@@ -54,6 +53,12 @@
#define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */
#if defined(CONFIG_BF527_NAND_D_PORTF)
#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
#elif defined(CONFIG_BF527_NAND_D_PORTH)
#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
#endif
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
......
......@@ -1671,7 +1671,7 @@
/* Bit masks for MXVR_DMAx_CONFIG */
#define MDMAEN 0x1 /* DMA Channel Enable */
#define DD 0x2 /* DMA Channel Direction */
#define DMADD 0x2 /* DMA Channel Direction */
#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
......
......@@ -2252,6 +2252,13 @@
#define PLL_OFF 0x2 /* Disable PLL */
#define DF 0x1 /* Divide Frequency */
/* SWRST Masks */
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* Bit masks for PLL_STAT */
#define PLL_LOCKED 0x20 /* PLL Locked Status */
......
......@@ -267,4 +267,18 @@
#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
#define P_NAND_D0 (P_DONTCARE)
#define P_NAND_D1 (P_DONTCARE)
#define P_NAND_D2 (P_DONTCARE)
#define P_NAND_D3 (P_DONTCARE)
#define P_NAND_D4 (P_DONTCARE)
#define P_NAND_D5 (P_DONTCARE)
#define P_NAND_D6 (P_DONTCARE)
#define P_NAND_D7 (P_DONTCARE)
#define P_NAND_WE (P_DONTCARE)
#define P_NAND_RE (P_DONTCARE)
#define P_NAND_CLE (P_DONTCARE)
#define P_NAND_ALE (P_DONTCARE)
#endif /* _MACH_PORTMUX_H_ */
......@@ -55,6 +55,9 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
#define RESET_SOFTWARE (SWRST_OCCURRED)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
......
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