Commit fbb89d02 authored by Casper Andersson's avatar Casper Andersson Committed by David S. Miller

net: sparx5: Allow mdb entries to both CPU and ports

Allow mdb entries to be forwarded to CPU and be switched at the same
time. Only remove entry when no port and the CPU isn't part of the group
anymore.
Signed-off-by: default avatarCasper Andersson <casper.casan@gmail.com>
Acked-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c63c615e
...@@ -394,12 +394,10 @@ static int sparx5_handle_port_mdb_add(struct net_device *dev, ...@@ -394,12 +394,10 @@ static int sparx5_handle_port_mdb_add(struct net_device *dev,
struct sparx5 *spx5 = port->sparx5; struct sparx5 *spx5 = port->sparx5;
u16 pgid_idx, vid; u16 pgid_idx, vid;
u32 mact_entry; u32 mact_entry;
bool is_host;
int res, err; int res, err;
if (netif_is_bridge_master(v->obj.orig_dev)) { is_host = netif_is_bridge_master(v->obj.orig_dev);
sparx5_mact_learn(spx5, PGID_CPU, v->addr, v->vid);
return 0;
}
/* When VLAN unaware the vlan value is not parsed and we receive vid 0. /* When VLAN unaware the vlan value is not parsed and we receive vid 0.
* Fall back to bridge vid 1. * Fall back to bridge vid 1.
...@@ -416,17 +414,33 @@ static int sparx5_handle_port_mdb_add(struct net_device *dev, ...@@ -416,17 +414,33 @@ static int sparx5_handle_port_mdb_add(struct net_device *dev,
/* MC_IDX starts after the port masks in the PGID table */ /* MC_IDX starts after the port masks in the PGID table */
pgid_idx += SPX5_PORTS; pgid_idx += SPX5_PORTS;
sparx5_pgid_update_mask(port, pgid_idx, true);
if (is_host)
spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, spx5,
ANA_AC_PGID_MISC_CFG(pgid_idx));
else
sparx5_pgid_update_mask(port, pgid_idx, true);
} else { } else {
err = sparx5_pgid_alloc_mcast(spx5, &pgid_idx); err = sparx5_pgid_alloc_mcast(spx5, &pgid_idx);
if (err) { if (err) {
netdev_warn(dev, "multicast pgid table full\n"); netdev_warn(dev, "multicast pgid table full\n");
return err; return err;
} }
sparx5_pgid_update_mask(port, pgid_idx, true);
if (is_host)
spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, spx5,
ANA_AC_PGID_MISC_CFG(pgid_idx));
else
sparx5_pgid_update_mask(port, pgid_idx, true);
err = sparx5_mact_learn(spx5, pgid_idx, v->addr, vid); err = sparx5_mact_learn(spx5, pgid_idx, v->addr, vid);
if (err) { if (err) {
netdev_warn(dev, "could not learn mac address %pM\n", v->addr); netdev_warn(dev, "could not learn mac address %pM\n", v->addr);
sparx5_pgid_free(spx5, pgid_idx);
sparx5_pgid_update_mask(port, pgid_idx, false); sparx5_pgid_update_mask(port, pgid_idx, false);
return err; return err;
} }
...@@ -463,13 +477,8 @@ static int sparx5_handle_port_mdb_del(struct net_device *dev, ...@@ -463,13 +477,8 @@ static int sparx5_handle_port_mdb_del(struct net_device *dev,
struct sparx5_port *port = netdev_priv(dev); struct sparx5_port *port = netdev_priv(dev);
struct sparx5 *spx5 = port->sparx5; struct sparx5 *spx5 = port->sparx5;
u16 pgid_idx, vid; u16 pgid_idx, vid;
u32 mact_entry, res, pgid_entry[3]; u32 mact_entry, res, pgid_entry[3], misc_cfg;
int err; bool host_ena;
if (netif_is_bridge_master(v->obj.orig_dev)) {
sparx5_mact_forget(spx5, v->addr, v->vid);
return 0;
}
if (!br_vlan_enabled(spx5->hw_bridge_dev)) if (!br_vlan_enabled(spx5->hw_bridge_dev))
vid = 1; vid = 1;
...@@ -483,15 +492,21 @@ static int sparx5_handle_port_mdb_del(struct net_device *dev, ...@@ -483,15 +492,21 @@ static int sparx5_handle_port_mdb_del(struct net_device *dev,
/* MC_IDX starts after the port masks in the PGID table */ /* MC_IDX starts after the port masks in the PGID table */
pgid_idx += SPX5_PORTS; pgid_idx += SPX5_PORTS;
sparx5_pgid_update_mask(port, pgid_idx, false);
if (netif_is_bridge_master(v->obj.orig_dev))
spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(0),
ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, spx5,
ANA_AC_PGID_MISC_CFG(pgid_idx));
else
sparx5_pgid_update_mask(port, pgid_idx, false);
misc_cfg = spx5_rd(spx5, ANA_AC_PGID_MISC_CFG(pgid_idx));
host_ena = ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(misc_cfg);
sparx5_pgid_read_mask(spx5, pgid_idx, pgid_entry); sparx5_pgid_read_mask(spx5, pgid_idx, pgid_entry);
if (bitmap_empty((unsigned long *)pgid_entry, SPX5_PORTS)) { if (bitmap_empty((unsigned long *)pgid_entry, SPX5_PORTS) && !host_ena)
/* No ports are in MC group. Remove entry */ /* No ports or CPU are in MC group. Remove entry */
err = sparx5_mdb_del_entry(dev, spx5, v->addr, vid, pgid_idx); return sparx5_mdb_del_entry(dev, spx5, v->addr, vid, pgid_idx);
if (err)
return err;
}
} }
return 0; return 0;
......
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