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Commit fbe6f8f2 authored by Yaodong Li's avatar Yaodong Li Committed by Joonas Lahtinen
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drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams 

GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
sphinx build if not using proper reST syntax.

This patch uses reST literal blocks to make sure GuC Address Space and
WOPCM Layout diagrams to be generated correctly, and it also corrects some
errors in the diagram description.

v2:
 - Fixed errors in diagram description

v3:
 - Updated GuC Address Space kernel-doc based on Michal's suggestion

v4:
 - Added WOPCM layout and GuC address space docs into i915.rst (Joonas)
Signed-off-by: default avatarJackie Li <yaodong.li@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1521763162-11424-1-git-send-email-yaodong.li@intel.com
parent 7fd9e829
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Showing with 67 additions and 48 deletions
Documentation/gpu/i915.rst
View file @ fbe6f8f2
......@@ -335,6 +335,15 @@ objects, which has the goal to make space in gpu virtual address spaces.
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
:internal:
WOPCM
=====
WOPCM Layout
------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
:doc: WOPCM Layout
GuC
===
......@@ -359,6 +368,12 @@ GuC Firmware Layout
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
:doc: GuC Firmware Layout
GuC Address Space
-----------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
:doc: GuC Address Space
Tracing
=======
......
drivers/gpu/drm/i915/intel_guc.c
View file @ fbe6f8f2
......@@ -494,35 +494,37 @@ int intel_guc_resume(struct intel_guc *guc)
/**
* DOC: GuC Address Space
*
* The layout of GuC address space is shown as below:
* The layout of GuC address space is shown below:
*
* +==============> +====================+ <== GUC_GGTT_TOP
* ^ | |
* | | |
* | | DRAM |
* | | Memory |
* | | |
* GuC | |
* Address +========> +====================+ <== WOPCM Top
* Space ^ | HW contexts RSVD |
* | | | WOPCM |
* | | +==> +--------------------+ <== GuC WOPCM Top
* | GuC ^ | |
* | GGTT | | |
* | Pin GuC | GuC |
* | Bias WOPCM | WOPCM |
* | | Size | |
* | | | | |
* v v v | |
* +=====+=====+==> +====================+ <== GuC WOPCM Base
* | Non-GuC WOPCM |
* | (HuC/Reserved) |
* +====================+ <== WOPCM Base
* ::
*
* The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of
* GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of
* the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is
* set in GUC_WOPCM_SIZE register.
* +==============> +====================+ <== GUC_GGTT_TOP
* ^ | |
* | | |
* | | DRAM |
* | | Memory |
* | | |
* GuC | |
* Address +========> +====================+ <== WOPCM Top
* Space ^ | HW contexts RSVD |
* | | | WOPCM |
* | | +==> +--------------------+ <== GuC WOPCM Top
* | GuC ^ | |
* | GGTT | | |
* | Pin GuC | GuC |
* | Bias WOPCM | WOPCM |
* | | Size | |
* | | | | |
* v v v | |
* +=====+=====+==> +====================+ <== GuC WOPCM Base
* | Non-GuC WOPCM |
* | (HuC/Reserved) |
* +====================+ <== WOPCM Base
*
* The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
* while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
* to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
* actual GuC WOPCM size.
*/
/**
......
drivers/gpu/drm/i915/intel_wopcm.c
View file @ fbe6f8f2
......@@ -11,28 +11,30 @@
* DOC: WOPCM Layout
*
* The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
* offset registers whose are calculated are determined by size of HuC/GuC
* firmware size and set of hw requirements/restrictions as shown below:
* offset registers whose values are calculated and determined by HuC/GuC
* firmware size and set of hardware requirements/restrictions as shown below:
*
* +=========> +====================+ <== WOPCM Top
* ^ | HW contexts RSVD |
* | +===> +====================+ <== GuC WOPCM Top
* | ^ | |
* | | | |
* | | | |
* | GuC | |
* | WOPCM | |
* | Size +--------------------+
* WOPCM | | GuC FW RSVD |
* | | +--------------------+
* | | | GuC Stack RSVD |
* | | +------------------- +
* | v | GuC WOPCM RSVD |
* | +===> +====================+ <== GuC WOPCM base
* | | WOPCM RSVD |
* | +------------------- + <== HuC Firmware Top
* v | HuC FW |
* +=========> +====================+ <== WOPCM Base
* ::
*
* +=========> +====================+ <== WOPCM Top
* ^ | HW contexts RSVD |
* | +===> +====================+ <== GuC WOPCM Top
* | ^ | |
* | | | |
* | | | |
* | GuC | |
* | WOPCM | |
* | Size +--------------------+
* WOPCM | | GuC FW RSVD |
* | | +--------------------+
* | | | GuC Stack RSVD |
* | | +------------------- +
* | v | GuC WOPCM RSVD |
* | +===> +====================+ <== GuC WOPCM base
* | | WOPCM RSVD |
* | +------------------- + <== HuC Firmware Top
* v | HuC FW |
* +=========> +====================+ <== WOPCM Base
*
* GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
* The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
......
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