Commit fc3b6177 authored by Jeff Garzik's avatar Jeff Garzik

Merge redhat.com:/spare/repo/netdev-2.6/mips

into redhat.com:/spare/repo/net-drivers-2.6
parents 2d095b6c 8cee2695
......@@ -471,11 +471,32 @@ config SGI_IOC3_ETH
bool "SGI IOC3 Ethernet"
depends on NET_ETHERNET && SGI_IP27
select CRC32
select MII
help
If you have a network (Ethernet) card of this type, say Y and read
the Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto>.
config SGI_IOC3_ETH_HW_RX_CSUM
bool "Receive hardware checksums"
depends on SGI_IOC3_ETH && INET
default y
help
The SGI IOC3 network adapter supports TCP and UDP checksums in
hardware to offload processing of these checksums from the CPU. At
the moment only acceleration of IPv4 is supported. This option
enables offloading for checksums on receive. If unsure, say Y.
config SGI_IOC3_ETH_HW_TX_CSUM
bool "Transmit hardware checksums"
depends on SGI_IOC3_ETH && INET
default y
help
The SGI IOC3 network adapter supports TCP and UDP checksums in
hardware to offload processing of these checksums from the CPU. At
the moment only acceleration of IPv4 is supported. This option
enables offloading for checksums on transmit. If unsure, say Y.
config SGI_O2MACE_ETH
tristate "SGI O2 MACE Fast Ethernet support"
depends on NET_ETHERNET && SGI_IP32=y
......@@ -1777,7 +1798,7 @@ config SGISEEQ
config DECLANCE
tristate "DEC LANCE ethernet controller support"
depends on NET_ETHERNET && DECSTATION
depends on NET_ETHERNET && MACH_DECSTATION
select CRC32
help
This driver is for the series of Ethernet controllers produced by
......
/* $Id$
/*
* bagetlance.c: Ethernet driver for VME Lance cards on Baget/MIPS
* This code stealed and adopted from linux/drivers/net/atarilance.c
* See that for author info
......
......@@ -786,7 +786,7 @@ static int lance_open(struct net_device *dev)
/* Associate IRQ with lance_interrupt */
if (request_irq(dev->irq, &lance_interrupt, 0, "lance", dev)) {
printk("lance: Can't get IRQ %d\n", dev->irq);
printk("%s: Can't get IRQ %d\n", dev->name, dev->irq);
return -EAGAIN;
}
if (lp->dma_irq >= 0) {
......@@ -795,7 +795,8 @@ static int lance_open(struct net_device *dev)
if (request_irq(lp->dma_irq, &lance_dma_merr_int, 0,
"lance error", dev)) {
free_irq(dev->irq, dev);
printk("lance: Can't get DMA IRQ %d\n", lp->dma_irq);
printk("%s: Can't get DMA IRQ %d\n", dev->name,
lp->dma_irq);
return -EAGAIN;
}
......@@ -1025,6 +1026,8 @@ static void lance_set_multicast_retry(unsigned long _opaque)
static int __init dec_lance_init(const int type, const int slot)
{
static unsigned version_printed;
static const char fmt[] = "declance%d";
char name[10];
struct net_device *dev;
struct lance_private *lp;
volatile struct lance_regs *ll;
......@@ -1039,10 +1042,22 @@ static int __init dec_lance_init(const int type, const int slot)
if (dec_lance_debug && version_printed++ == 0)
printk(version);
i = 0;
dev = root_lance_dev;
while (dev) {
i++;
lp = (struct lance_private *)dev->priv;
dev = lp->next;
}
snprintf(name, sizeof(name), fmt, i);
dev = alloc_etherdev(sizeof(struct lance_private));
if (!dev)
return -ENOMEM;
SET_MODULE_OWNER(dev);
if (!dev) {
printk(KERN_ERR "%s: Unable to allocate etherdev, aborting.\n",
name);
ret = -ENOMEM;
goto err_out;
}
/*
* alloc_etherdev ensures the data structures used by the LANCE
......@@ -1160,9 +1175,10 @@ static int __init dec_lance_init(const int type, const int slot)
break;
default:
printk("declance_init called with unknown type\n");
printk(KERN_ERR "%s: declance_init called with unknown type\n",
name);
ret = -ENODEV;
goto err_out;
goto err_out_free_dev;
}
ll = (struct lance_regs *) dev->base_addr;
......@@ -1172,19 +1188,21 @@ static int __init dec_lance_init(const int type, const int slot)
/* First, check for test pattern */
if (esar[0x60] != 0xff && esar[0x64] != 0x00 &&
esar[0x68] != 0x55 && esar[0x6c] != 0xaa) {
printk("Ethernet station address prom not found!\n");
printk(KERN_ERR
"%s: Ethernet station address prom not found!\n",
name);
ret = -ENODEV;
goto err_out;
goto err_out_free_dev;
}
/* Check the prom contents */
for (i = 0; i < 8; i++) {
if (esar[i * 4] != esar[0x3c - i * 4] &&
esar[i * 4] != esar[0x40 + i * 4] &&
esar[0x3c - i * 4] != esar[0x40 + i * 4]) {
printk("Something is wrong with the ethernet "
"station address prom!\n");
printk(KERN_ERR "%s: Something is wrong with the "
"ethernet station address prom!\n", name);
ret = -ENODEV;
goto err_out;
goto err_out_free_dev;
}
}
......@@ -1194,13 +1212,13 @@ static int __init dec_lance_init(const int type, const int slot)
*/
switch (type) {
case ASIC_LANCE:
printk("%s: IOASIC onboard LANCE, addr = ", dev->name);
printk("%s: IOASIC onboard LANCE, addr = ", name);
break;
case PMAD_LANCE:
printk("%s: PMAD-AA, addr = ", dev->name);
printk("%s: PMAD-AA, addr = ", name);
break;
case PMAX_LANCE:
printk("%s: PMAX onboard LANCE, addr = ", dev->name);
printk("%s: PMAX onboard LANCE, addr = ", name);
break;
}
for (i = 0; i < 6; i++) {
......@@ -1236,15 +1254,24 @@ static int __init dec_lance_init(const int type, const int slot)
init_timer(&lp->multicast_timer);
lp->multicast_timer.data = (unsigned long) dev;
lp->multicast_timer.function = &lance_set_multicast_retry;
ret = register_netdev(dev);
if (ret)
goto err_out;
if (ret) {
printk(KERN_ERR
"%s: Unable to register netdev, aborting.\n", name);
goto err_out_free_dev;
}
lp->next = root_lance_dev;
root_lance_dev = dev;
printk("%s: registered as %s.\n", name, dev->name);
return 0;
err_out_free_dev:
kfree(dev);
err_out:
free_netdev(dev);
return ret;
}
......
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......@@ -16,9 +16,6 @@
/* version dependencies have been confined to a separate file */
#define SGI_MFE (MACE_BASE+MACE_ENET)
/* (0xBF280000)*/
/* Tunable parameters */
#define TX_RING_ENTRIES 64 /* 64-512?*/
......@@ -27,10 +24,12 @@
#define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
#define RX_BUFFER_SIZE 1546 /* ethenet packet size */
#define METH_RX_BUFF_SIZE 4096
#define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
#define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
#define RX_BUCKET_SIZE 256
#undef BIT
#define BIT(x) (1 << (x))
/* For more detailed explanations of what each field menas,
see Nick's great comments to #defines below (or docs, if
......@@ -85,7 +84,7 @@ typedef struct tx_packet {
} tx_packet;
typedef union rx_status_vector {
struct {
volatile struct {
u64 pad1:1;/*fill it with ones*/
u64 pad2:15;/*fill with 0*/
u64 ip_chk_sum:16;
......@@ -103,7 +102,7 @@ typedef union rx_status_vector {
u64 rx_code_violation:1;
u64 rx_len:16;
} parsed;
u64 raw;
volatile u64 raw;
} rx_status_vector;
typedef struct rx_packet {
......@@ -113,50 +112,8 @@ typedef struct rx_packet {
char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
} rx_packet;
typedef struct meth_regs {
u64 mac_ctrl; /*0x00,rw,31:0*/
u64 int_flags; /*0x08,rw,30:0*/
u64 dma_ctrl; /*0x10,rw,15:0*/
u64 timer; /*0x18,rw,5:0*/
u64 int_tx; /*0x20,wo,0:0*/
u64 int_rx; /*0x28,wo,9:4*/
struct {
u32 tx_info_pad;
u32 rptr:16,wptr:16;
} tx_info; /*0x30,rw,31:0*/
u64 tx_info_al; /*0x38,rw,31:0*/
struct {
u32 rx_buff_pad1;
u32 rx_buff_pad2:8,
wptr:8,
rptr:8,
depth:8;
} rx_buff; /*0x40,ro,23:0*/
u64 rx_buff_al1; /*0x48,ro,23:0*/
u64 rx_buff_al2; /*0x50,ro,23:0*/
u64 int_update; /*0x58,wo,31:0*/
u32 phy_data_pad;
u32 phy_data; /*0x60,rw,16:0*/
u32 phy_reg_pad;
u32 phy_registers; /*0x68,rw,9:0*/
u64 phy_trans_go; /*0x70,wo,0:0*/
u64 backoff_seed; /*0x78,wo,10:0*/
u64 imq_reserved[4];/*0x80,ro,64:0(x4)*/
/*===================================*/
u64 mac_addr; /*0xA0,rw,47:0, I think it's MAC address, but I'm not sure*/
u64 mcast_addr; /*0xA8,rw,47:0, This seems like secondary MAC address*/
u64 mcast_filter; /*0xB0,rw,63:0*/
u64 tx_ring_base; /*0xB8,rw,31:13*/
/* Following are read-only debugging info register */
u64 tx_pkt1_hdr; /*0xC0,ro,63:0*/
u64 tx_pkt1_ptr[3]; /*0xC8,ro,63:0(x3)*/
u64 tx_pkt2_hdr; /*0xE0,ro,63:0*/
u64 tx_pkt2_ptr[3]; /*0xE8,ro,63:0(x3)*/
/*===================================*/
u32 rx_pad;
u32 rx_fifo;
u64 reserved[31];
}meth_regs;
#define TX_INFO_RPTR 0x00FF0000
#define TX_INFO_WPTR 0x000000FF
/* Bits in METH_MAC */
......@@ -203,9 +160,14 @@ typedef struct meth_regs {
#define METH_DMA_RX_EN BIT(15) /* Enable RX */
#define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
/* RX FIFO MCL Info bits */
#define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf)
#define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf)
#define METH_RX_FIFO_DEPTH(x) ((x)&0x1f)
/* RX status bits */
#define METH_RX_ST_VALID BIT(63)
#define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
#define METH_RX_ST_DRBL_NBL BIT(17)
#define METH_RX_ST_CRC_ERR BIT(18)
......@@ -240,25 +202,34 @@ typedef struct meth_regs {
#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
#define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
#define METH_INT_RX_RPTR_MASK 0x0001F00 /* Bits 8 through 12 alias of RX read-pointer */
/*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
#define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
/* Bits 13 through 15 are always 0. */
#define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
#define METH_INT_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */
#define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */
/* top of the queue */
#define METH_ERRORS ( \
METH_INT_RX_OVERFLOW| \
METH_INT_RX_UNDERFLOW| \
#define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \
METH_INT_MEM_ERROR| \
METH_INT_TX_ABORT)
METH_INT_TX_ABORT| \
METH_INT_RX_OVERFLOW| \
METH_INT_RX_UNDERFLOW)
#define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
/* TX status bits */
#define METH_TX_STATUS_DONE BIT(23) /* Packet was transmitted successfully */
#define METH_TX_ST_DONE BIT(63) /* TX complete */
#define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */
#define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */
#define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */
#define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */
#define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */
#define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */
/* Tx command header bits */
#define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
......@@ -271,3 +242,5 @@ typedef struct meth_regs {
#define PHY_ICS1889 0x0015F41 /* ICS FX */
#define PHY_ICS1890 0x0015F42 /* ICS TX */
#define PHY_DP83840 0x20005C0 /* National TX */
#define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)
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