[SPARC64]: Kill SPARC64_USE_STICK and use real timer drivers.

arch/sparc64/kernel/irq.c

@@ -719,12 +719,8 @@ void handler_irq(int irq, struct pt_regs *regs)
 	 */
 	{
 		unsigned long clr_mask = 1 << irq;
-		unsigned long tick_mask;
+		unsigned long tick_mask = tick_ops->softint_mask;
 
-		if (SPARC64_USE_STICK)
-			tick_mask = (1UL << 16);
-		else
-			tick_mask = (1UL << 0);
 		if ((irq == 14) && (get_softint() & tick_mask)) {
 			irq = 0;
 			clr_mask = tick_mask;

arch/sparc64/mm/ultra.S

@@ -560,8 +560,8 @@ xcall_flush_tlb_kernel_range:
 	/* This runs in a very controlled environment, so we do
 	 * not need to worry about BH races etc.
 	 */
-	.globl		xcall_sync_stick
-xcall_sync_stick:
+	.globl		xcall_sync_tick
+xcall_sync_tick:
 	rdpr		%pstate, %g2
 	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate
 	rdpr		%pil, %g2
@@ -569,7 +569,7 @@ xcall_sync_stick:
 	sethi		%hi(109f), %g7
 	b,pt		%xcc, etrap_irq
 109:	 or		%g7, %lo(109b), %g7
-	call		smp_synchronize_stick_client
+	call		smp_synchronize_tick_client
 	 nop
 	clr		%l6
 	b		rtrap_xcall

include/asm-sparc64/spitfire.h

@@ -45,8 +45,6 @@ enum ultra_tlb_layout {
 
 extern enum ultra_tlb_layout tlb_type;
 
-#define SPARC64_USE_STICK	(tlb_type != spitfire)
-
 #define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)
 
 #define L1DCACHE_SIZE		0x4000

include/asm-sparc64/timer.h

@@ -50,6 +50,17 @@ struct sun5_timer {
  */
 #define SUN5_HZ_TO_LIMIT(__hz)  (1000000/(__hz))
 
+struct sparc64_tick_ops {
+	void (*init_tick)(unsigned long);
+	unsigned long (*get_tick)(void);
+	unsigned long (*get_compare)(void);
+	unsigned long (*add_tick)(unsigned long, unsigned long);
+	unsigned long (*add_compare)(unsigned long);
+	unsigned long softint_mask;
+};
+
+extern struct sparc64_tick_ops *tick_ops;
+
 #ifdef CONFIG_SMP
 extern unsigned long timer_tick_offset;
 extern void timer_tick_interrupt(struct pt_regs *);