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Commit fc5570e0 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'ice-introduce-eth56g-phy-model-for-e825c-products' 

Jacob Keller says:

====================
ice: Introduce ETH56G PHY model for E825C products

E825C products have a different PHY model than E822, E823 and E810 products.
This PHY is ETH56G and its support is necessary to have functional PTP stack
for E825C products.

This series refactors the ice driver to add support for the new PHY model.

Karol introduces the ice_ptp_hw structure. This is used to replace some
hard-coded values relating to the PHY quad and port numbers, as well as to
hold the phy_model type.

Jacob refactors the driver code that converts between the ice_ptp_tmr_cmd
enumeration and hardware register values to better re-use logic and reduce
duplication when introducing another PHY type.

Sergey introduces functions to help enable and disable the Tx timestamp
interrupts. This makes the ice_ptp.c code more generic and encapsulates the
PHY specifics into ice_ptp_hw.c

Karol introduces helper functions to clear the valid bits for Tx and Rx
timestamps. This enables informing hardware to discard stale timestamps
after performing clock operations.

Sergey moves the Clock Generation Unit (CGU) logic out of the E822 specific
area of the ice_ptp_hw.c file as it will be re-used for other device PHY
models.

Jacob introduces a helper function for obtaining the base increment values,
moving this logic out of ice_ptp.c and into the ice_ptp_hw.c file to better
encapsulate hardware differences.

Sergey builds on these refactors to introduce the new ETH56G PHY model used
by the E825C products. This includes introducing the required helpers,
constants, and PHY model checks.

Karol simplifies the CGU logic by using anonymous structures, dropping an
unnecessary ".field" name for accessing the CGU data.

Michal Michalik updates the CGU logic to support the E825C hardware,
ensuring that the clock generation is configured properly.

Grzegorz Nitka adds support to read the NAC topology data from the device.
This is in preparation for supporting devices which combine two NACs
together, connecting all ports to the same clock source. This enables the
driver to determine if its operating on such a device, or if its operating
on the standard 1-NAC configuration.

Grzsecgorz Nitka adjusts the PTP initialization to prepare for the 2x50G
E825C devices, introducing special mapping for the PHY ports to prepare for
support of the 2-NAC devices.

With this, the ice driver is capable of handling PTP for the single-NAC
E825C devices. Complete support for the 2-NAC devices requirs some work on
how the ports connect to the clock owner. During review of this work, it
was pointed out that our existing use of auxiliary bus is disliked, and
Jiri requested that we change it. We are currently working on developing a
replacement solution for the auxiliary bus implementation and have dropped
the relevant changes out of this series. A future series will refactor the
port to clock connection, at which time we will finish the support for
2-NAC E825C devices.
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
====================

Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-0-c082739bb6f6@intel.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 73451e9a 4409ea17
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Showing with 3772 additions and 652 deletions
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View file @ fc5570e0
......@@ -122,6 +122,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define ICE_AQC_CAPS_NVM_MGMT 0x0080
#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
#define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092
#define ICE_AQC_BIT_ROCEV2_LAG 0x01
#define ICE_AQC_BIT_SRIOV_LAG 0x02
......
drivers/net/ethernet/intel/ice/ice_cgu_regs.h
View file @ fc5570e0
......@@ -23,7 +23,18 @@ union nac_cgu_dword9 {
u32 clk_synce0_amp : 2;
u32 one_pps_out_amp : 2;
u32 misc24 : 12;
} field;
};
u32 val;
};
#define NAC_CGU_DWORD16_E825C 0x40
union nac_cgu_dword16_e825c {
struct {
u32 synce_remndr : 6;
u32 synce_phlmt_en : 1;
u32 misc13 : 17;
u32 tspll_ck_refclkfreq : 8;
};
u32 val;
};
......@@ -39,7 +50,7 @@ union nac_cgu_dword19 {
u32 japll_ndivratio : 4;
u32 japll_iref_ndivratio : 3;
u32 misc27 : 1;
} field;
};
u32 val;
};
......@@ -63,7 +74,23 @@ union nac_cgu_dword22 {
u32 fdpllclk_sel_div2 : 1;
u32 time1588clk_sel_div2 : 1;
u32 misc3 : 1;
} field;
};
u32 val;
};
#define NAC_CGU_DWORD23_E825C 0x5C
union nac_cgu_dword23_e825c {
struct {
u32 cgupll_fbdiv_intgr : 10;
u32 ux56pll_fbdiv_intgr : 10;
u32 misc20 : 4;
u32 ts_pll_enable : 1;
u32 time_sync_tspll_align_sel : 1;
u32 ext_synce_sel : 1;
u32 ref1588_ck_div : 4;
u32 time_ref_sel : 1;
};
u32 val;
};
......@@ -77,7 +104,7 @@ union nac_cgu_dword24 {
u32 ext_synce_sel : 1;
u32 ref1588_ck_div : 4;
u32 time_ref_sel : 1;
} field;
};
u32 val;
};
......@@ -92,7 +119,7 @@ union tspll_cntr_bist_settings {
u32 i_plllock_cnt_6_0 : 7;
u32 i_plllock_cnt_10_7 : 4;
u32 reserved200 : 4;
} field;
};
u32 val;
};
......@@ -109,7 +136,45 @@ union tspll_ro_bwm_lf {
u32 afcdone_cri : 1;
u32 feedfwrdgain_cal_cri_7_0 : 8;
u32 m2fbdivmod_cri_7_0 : 8;
} field;
};
u32 val;
};
#define TSPLL_RO_LOCK_E825C 0x3f0
union tspll_ro_lock_e825c {
struct {
u32 bw_freqov_high_cri_7_0 : 8;
u32 bw_freqov_high_cri_9_8 : 2;
u32 reserved455 : 1;
u32 plllock_gain_tran_cri : 1;
u32 plllock_true_lock_cri : 1;
u32 pllunlock_flag_cri : 1;
u32 afcerr_cri : 1;
u32 afcdone_cri : 1;
u32 feedfwrdgain_cal_cri_7_0 : 8;
u32 reserved462 : 8;
};
u32 val;
};
#define TSPLL_BW_TDC_E825C 0x31c
union tspll_bw_tdc_e825c {
struct {
u32 i_tdc_offset_lock_1_0 : 2;
u32 i_bbthresh1_2_0 : 3;
u32 i_bbthresh2_2_0 : 3;
u32 i_tdcsel_1_0 : 2;
u32 i_tdcovccorr_en_h : 1;
u32 i_divretimeren : 1;
u32 i_bw_ampmeas_window : 1;
u32 i_bw_lowerbound_2_0 : 3;
u32 i_bw_upperbound_2_0 : 3;
u32 i_bw_mode_1_0 : 2;
u32 i_ft_mode_sel_2_0 : 3;
u32 i_bwphase_4_0 : 5;
u32 i_plllock_sel_1_0 : 2;
u32 i_afc_divratio : 1;
};
u32 val;
};
......
drivers/net/ethernet/intel/ice/ice_common.c
View file @ fc5570e0
......@@ -239,6 +239,30 @@ bool ice_is_e810t(struct ice_hw *hw)
return false;
}
/**
* ice_is_e822 - Check if a device is E822 family device
* @hw: pointer to the hardware structure
*
* Return: true if the device is E822 based, false if not.
*/
bool ice_is_e822(struct ice_hw *hw)
{
switch (hw->device_id) {
case ICE_DEV_ID_E822C_BACKPLANE:
case ICE_DEV_ID_E822C_QSFP:
case ICE_DEV_ID_E822C_SFP:
case ICE_DEV_ID_E822C_10G_BASE_T:
case ICE_DEV_ID_E822C_SGMII:
case ICE_DEV_ID_E822L_BACKPLANE:
case ICE_DEV_ID_E822L_SFP:
case ICE_DEV_ID_E822L_10G_BASE_T:
case ICE_DEV_ID_E822L_SGMII:
return true;
default:
return false;
}
}
/**
* ice_is_e823
* @hw: pointer to the hardware structure
......@@ -2290,8 +2314,13 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
if (!ice_is_e825c(hw)) {
info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
} else {
info->clk_freq = ICE_TIME_REF_FREQ_156_250;
info->clk_src = ICE_CLK_SRC_TCXO;
}
if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
......@@ -2564,6 +2593,34 @@ ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
dev_p->supported_sensors);
}
/**
* ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
*/
static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw,
struct ice_hw_dev_caps *dev_p,
struct ice_aqc_list_caps_elem *cap)
{
dev_p->nac_topo.mode = le32_to_cpu(cap->number);
dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
dev_info(ice_hw_to_dev(hw),
"PF is configured in %s mode with IP instance ID %d\n",
(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ?
"primary" : "secondary", dev_p->nac_topo.id);
ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n",
!!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M));
ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n",
!!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M));
ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n",
dev_p->nac_topo.id);
}
/**
* ice_parse_dev_caps - Parse device capabilities
* @hw: pointer to the HW struct
......@@ -2615,6 +2672,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
case ICE_AQC_CAPS_SENSOR_READING:
ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]);
break;
case ICE_AQC_CAPS_NAC_TOPOLOGY:
ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]);
break;
default:
/* Don't list common capabilities as unknown */
if (!found)
......@@ -3043,11 +3103,13 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw)
* Note: In the structure of [phy_type_low, phy_type_high], there should
* be one bit set, as this function will convert one PHY type to its
* speed.
* If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
* If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*
* Return:
* * PHY speed for recognized PHY type
* * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
* * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*/
static u16
ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
{
u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
......
drivers/net/ethernet/intel/ice/ice_common.h
View file @ fc5570e0
......@@ -249,6 +249,7 @@ void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
bool ice_is_e810t(struct ice_hw *hw);
bool ice_is_e822(struct ice_hw *hw);
bool ice_is_e823(struct ice_hw *hw);
bool ice_is_e825c(struct ice_hw *hw);
int
......@@ -261,6 +262,7 @@ int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd);
bool ice_is_100m_speed_supported(struct ice_hw *hw);
u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
int
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
struct ice_sq_cd *cd);
......
drivers/net/ethernet/intel/ice/ice_hw_autogen.h
View file @ fc5570e0
......@@ -157,6 +157,8 @@
#define GLGEN_RTRIG_CORER_M BIT(0)
#define GLGEN_RTRIG_GLOBR_M BIT(1)
#define GLGEN_STAT 0x000B612C
#define GLGEN_SWITCH_MODE_CONFIG 0x000B81E0
#define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M BIT(2)
#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
#define PFGEN_CTRL 0x00091000
#define PFGEN_CTRL_PFSWR_M BIT(0)
......@@ -177,6 +179,8 @@
#define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24)
#define GLINT_CTL_ITR_GRAN_25_S 28
#define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28)
#define GLGEN_MAC_LINK_TOPO 0x000B81DC
#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M GENMASK(1, 0)
#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
#define GLINT_DYN_CTL_INTENA_M BIT(0)
#define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
......
drivers/net/ethernet/intel/ice/ice_ptp.c
View file @ fc5570e0
......@@ -7,8 +7,6 @@
#define E810_OUT_PROP_DELAY_NS 1
#define UNKNOWN_INCVAL_E82X 0x100000000ULL
static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
/* name idx func chan */
{ "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
......@@ -813,7 +811,7 @@ static enum ice_tx_tstamp_work ice_ptp_tx_tstamp_owner(struct ice_pf *pf)
}
mutex_unlock(&pf->ptp.ports_owner.lock);
for (i = 0; i < ICE_MAX_QUAD; i++) {
for (i = 0; i < ICE_GET_QUAD_NUM(pf->hw.ptp.num_lports); i++) {
u64 tstamp_ready;
int err;
......@@ -1013,6 +1011,28 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
tx->len = 0;
}
/**
* ice_ptp_init_tx_eth56g - Initialize tracking for Tx timestamps
* @pf: Board private structure
* @tx: the Tx tracking structure to initialize
* @port: the port this structure tracks
*
* Initialize the Tx timestamp tracker for this port. ETH56G PHYs
* have independent memory blocks for all ports.
*
* Return: 0 for success, -ENOMEM when failed to allocate Tx tracker
*/
static int ice_ptp_init_tx_eth56g(struct ice_pf *pf, struct ice_ptp_tx *tx,
u8 port)
{
tx->block = port;
tx->offset = 0;
tx->len = INDEX_PER_PORT_ETH56G;
tx->has_ready_bitmap = 1;
return ice_ptp_alloc_tx_tracker(tx);
}
/**
* ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps
* @pf: Board private structure
......@@ -1027,7 +1047,7 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
static int
ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
{
tx->block = port / ICE_PORTS_PER_QUAD;
tx->block = ICE_GET_QUAD_NUM(port);
tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;
tx->len = INDEX_PER_PORT_E82X;
tx->has_ready_bitmap = 1;
......@@ -1210,12 +1230,7 @@ static u64 ice_base_incval(struct ice_pf *pf)
struct ice_hw *hw = &pf->hw;
u64 incval;
if (ice_is_e810(hw))
incval = ICE_PTP_NOMINAL_INCVAL_E810;
else if (ice_e82x_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
else
incval = UNKNOWN_INCVAL_E82X;
incval = ice_get_base_incval(hw);
dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
incval);
......@@ -1229,8 +1244,8 @@ static u64 ice_base_incval(struct ice_pf *pf)
*/
static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
{
int quad = port->port_num / ICE_PORTS_PER_QUAD;
int offs = port->port_num % ICE_PORTS_PER_QUAD;
int quad = ICE_GET_QUAD_NUM(port->port_num);
struct ice_pf *pf;
struct ice_hw *hw;
u32 val, phy_sts;
......@@ -1348,10 +1363,19 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_stop_phy_timer_eth56g(hw, port, true);
break;
case ICE_PHY_E82X:
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
err = ice_stop_phy_timer_e82x(hw, port, true);
if (err)
err = ice_stop_phy_timer_e82x(hw, port, true);
break;
default:
err = -ENODEV;
}
if (err && err != -EBUSY)
dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
port, err);
......@@ -1385,27 +1409,39 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_start_phy_timer_eth56g(hw, port);
break;
case ICE_PHY_E82X:
/* Start the PHY timer in Vernier mode */
kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
/* temporarily disable Tx timestamps while calibrating PHY offset */
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = true;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
ptp_port->tx_fifo_busy_cnt = 0;
/* temporarily disable Tx timestamps while calibrating
* PHY offset
*/
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = true;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
ptp_port->tx_fifo_busy_cnt = 0;
/* Start the PHY timer in Vernier mode */
err = ice_start_phy_timer_e82x(hw, port);
if (err)
goto out_unlock;
/* Start the PHY timer in Vernier mode */
err = ice_start_phy_timer_e82x(hw, port);
if (err)
break;
/* Enable Tx timestamps right away */
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = false;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
/* Enable Tx timestamps right away */
spin_lock_irqsave(&ptp_port->tx.lock, flags);
ptp_port->tx.calibrating = false;
spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work,
0);
break;
default:
err = -ENODEV;
}
out_unlock:
if (err)
dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
port, err);
......@@ -1429,20 +1465,23 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
if (pf->ptp.state != ICE_PTP_READY)
return;
if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
if (WARN_ON_ONCE(port >= hw->ptp.num_lports))
return;
ptp_port = &pf->ptp.port;
if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
port *= 2;
if (WARN_ON_ONCE(ptp_port->port_num != port))
return;
/* Update cached link status for this port immediately */
ptp_port->link_up = linkup;
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_E810:
/* Do not reconfigure E810 PHY */
return;
case ICE_PHY_ETH56G:
case ICE_PHY_E82X:
ice_ptp_port_phy_restart(ptp_port);
return;
......@@ -1457,42 +1496,62 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
* @ena: bool value to enable or disable interrupt
* @threshold: Minimum number of packets at which intr is triggered
*
* Utility function to enable or disable Tx timestamp interrupt and threshold
* Utility function to configure all the PHY interrupt settings, including
* whether the PHY interrupt is enabled, and what threshold to use. Also
* configures The E82X timestamp owner to react to interrupts from all PHYs.
*
* Return: 0 on success, -EOPNOTSUPP when PHY model incorrect, other error codes
* when failed to configure PHY interrupt for E82X
*/
static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
{
struct device *dev = ice_pf_to_dev(pf);
struct ice_hw *hw = &pf->hw;
int err = 0;
int quad;
u32 val;
ice_ptp_reset_ts_memory(hw);
for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
&val);
if (err)
break;
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G: {
int port;
if (ena) {
val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
threshold);
} else {
val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_phy_cfg_intr_eth56g(hw, port, ena, threshold);
if (err) {
dev_err(dev, "Failed to configure PHY interrupt for port %d, err %d\n",
port, err);
return err;
}
}
err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
val);
if (err)
break;
return 0;
}
case ICE_PHY_E82X: {
int quad;
if (err)
dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
err);
return err;
for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);
quad++) {
int err;
err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);
if (err) {
dev_err(dev, "Failed to configure PHY interrupt for quad %d, err %d\n",
quad, err);
return err;
}
}
return 0;
}
case ICE_PHY_E810:
return 0;
case ICE_PHY_UNSUP:
default:
dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,
hw->ptp.phy_model);
return -EOPNOTSUPP;
}
}
/**
......@@ -1929,11 +1988,14 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
struct ice_hw *hw = &pf->hw;
int err;
/* For Vernier mode, we need to recalibrate after new settime
* Start with disabling timestamp block
/* For Vernier mode on E82X, we need to recalibrate after new settime.
* Start with marking timestamps as invalid.
*/
if (pf->ptp.port.link_up)
ice_ptp_port_phy_stop(&pf->ptp.port);
if (hw->ptp.phy_model == ICE_PHY_E82X) {
err = ice_ptp_clear_phy_offset_ready_e82x(hw);
if (err)
dev_warn(ice_pf_to_dev(pf), "Failed to mark timestamps as invalid before settime\n");
}
if (!ice_ptp_lock(hw)) {
err = -EBUSY;
......@@ -1953,7 +2015,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
ice_ptp_enable_all_clkout(pf);
/* Recalibrate and re-enable timestamp blocks for E822/E823 */
if (hw->phy_model == ICE_PHY_E82X)
if (hw->ptp.phy_model == ICE_PHY_E82X)
ice_ptp_restart_all_phy(pf);
exit:
if (err) {
......@@ -2578,7 +2640,7 @@ static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)
if (!ice_pf_src_tmr_owned(pf))
return;
for (i = 0; i < ICE_MAX_QUAD; i++) {
for (i = 0; i < ICE_GET_QUAD_NUM(hw->ptp.num_lports); i++) {
u64 tstamp_ready;
int err;
......@@ -3010,12 +3072,10 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
/* Release the global hardware lock */
ice_ptp_unlock(hw);
if (!ice_is_e810(hw)) {
/* Enable quad interrupts */
err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
if (err)
goto err_exit;
}
/* Configure PHY interrupt settings */
err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
if (err)
goto err_exit;
/* Ensure we have a clock device */
err = ice_ptp_create_clock(pf);
......@@ -3076,7 +3136,10 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
mutex_init(&ptp_port->ps_lock);
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_ptp_init_tx_eth56g(pf, &ptp_port->tx,
ptp_port->port_num);
case ICE_PHY_E810:
return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
case ICE_PHY_E82X:
......@@ -3171,7 +3234,7 @@ static void ice_ptp_remove_auxbus_device(struct ice_pf *pf)
*/
static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)
{
switch (pf->hw.phy_model) {
switch (pf->hw.ptp.phy_model) {
case ICE_PHY_E82X:
/* E822 based PHY has the clock owner process the interrupt
* for all ports.
......@@ -3207,7 +3270,7 @@ void ice_ptp_init(struct ice_pf *pf)
ptp->state = ICE_PTP_INITIALIZING;
ice_ptp_init_phy_model(hw);
ice_ptp_init_hw(hw);
ice_ptp_init_tx_interrupt_mode(pf);
......@@ -3221,6 +3284,9 @@ void ice_ptp_init(struct ice_pf *pf)
}
ptp->port.port_num = hw->pf_id;
if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
ptp->port.port_num = hw->pf_id * 2;
err = ice_ptp_init_port(pf, &ptp->port);
if (err)
goto err;
......
drivers/net/ethernet/intel/ice/ice_ptp.h
View file @ fc5570e0
......@@ -153,6 +153,7 @@ struct ice_ptp_tx {
#define INDEX_PER_QUAD 64
#define INDEX_PER_PORT_E82X 16
#define INDEX_PER_PORT_E810 64
#define INDEX_PER_PORT_ETH56G 64
/**
* struct ice_ptp_port - data used to initialize an external port for PTP
......
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
View file @ fc5570e0
......@@ -9,6 +9,321 @@
*/
/* Constants defined for the PTP 1588 clock hardware. */
const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
/* ETH56G_PHY_REG_PTP */
{
/* base_addr */
{
0x092000,
0x126000,
0x1BA000,
0x24E000,
0x2E2000,
},
/* step */
0x98,
},
/* ETH56G_PHY_MEM_PTP */
{
/* base_addr */
{
0x093000,
0x127000,
0x1BB000,
0x24F000,
0x2E3000,
},
/* step */
0x200,
},
/* ETH56G_PHY_REG_XPCS */
{
/* base_addr */
{
0x000000,
0x009400,
0x128000,
0x1BC000,
0x250000,
},
/* step */
0x21000,
},
/* ETH56G_PHY_REG_MAC */
{
/* base_addr */
{
0x085000,
0x119000,
0x1AD000,
0x241000,
0x2D5000,
},
/* step */
0x1000,
},
/* ETH56G_PHY_REG_GPCS */
{
/* base_addr */
{
0x084000,
0x118000,
0x1AC000,
0x240000,
0x2D4000,
},
/* step */
0x400,
},
};
const
struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
[ICE_ETH56G_LNK_SPD_1G] = {
.tx_mode = { .def = 6, },
.rx_mode = { .def = 6, },
.blks_per_clk = 1,
.blktime = 0x4000, /* 32 */
.tx_offset = {
.serdes = 0x6666, /* 51.2 */
.no_fec = 0xd066, /* 104.2 */
.sfd = 0x3000, /* 24 */
.onestep = 0x30000 /* 384 */
},
.rx_offset = {
.serdes = 0xffffc59a, /* -29.2 */
.no_fec = 0xffff0a80, /* -122.75 */
.sfd = 0x2c00, /* 22 */
.bs_ds = 0x19a /* 0.8 */
/* Dynamic bitslip 0 equals to 10 */
}
},
[ICE_ETH56G_LNK_SPD_2_5G] = {
.tx_mode = { .def = 6, },
.rx_mode = { .def = 6, },
.blks_per_clk = 1,
.blktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0x28f6, /* 20.48 */
.no_fec = 0x53b8, /* 41.86 */
.sfd = 0x1333, /* 9.6 */
.onestep = 0x13333 /* 153.6 */
},
.rx_offset = {
.serdes = 0xffffe8a4, /* -11.68 */
.no_fec = 0xffff9a76, /* -50.77 */
.sfd = 0xf33, /* 7.6 */
.bs_ds = 0xa4 /* 0.32 */
}
},
[ICE_ETH56G_LNK_SPD_10G] = {
.tx_mode = { .def = 1, },
.rx_mode = { .def = 1, },
.blks_per_clk = 1,
.blktime = 0x666, /* 3.2 */
.tx_offset = {
.serdes = 0x234c, /* 17.6484848 */
.no_fec = 0x8e80, /* 71.25 */
.fc = 0xb4a4, /* 90.32 */
.sfd = 0x4a4, /* 2.32 */
.onestep = 0x4ccd /* 38.4 */
},
.rx_offset = {
.serdes = 0xffffeb27, /* -10.42424 */
.no_fec = 0xffffcccd, /* -25.6 */
.fc = 0xfffe0014, /* -255.96 */
.sfd = 0x4a4, /* 2.32 */
.bs_ds = 0x32 /* 0.0969697 */
}
},
[ICE_ETH56G_LNK_SPD_25G] = {
.tx_mode = {
.def = 1,
.rs = 4
},
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = {
.def = 1,
.rs = 4
},
.rx_mk_dly = {
.def = 1,
.rs = 1
},
.rx_cw_dly = {
.def = 1,
.rs = 1
},
.blks_per_clk = 1,
.blktime = 0x28f, /* 1.28 */
.mktime = 0x147b, /* 10.24, only if RS-FEC enabled */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x3857, /* 28.17 */
.fc = 0x48c3, /* 36.38 */
.rs = 0x8100, /* 64.5 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0x1eb8 /* 15.36 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xffffe71a, /* -12.45 */
.fc = 0xfffe894d, /* -187.35 */
.rs = 0xfffff8cd, /* -3.6 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0x14 /* 0.0387879, RS-FEC 0 */
}
},
[ICE_ETH56G_LNK_SPD_40G] = {
.tx_mode = { .def = 3 },
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = { .def = 4 },
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x333, /* 1.6 */
.mktime = 0xccd, /* 6.4 */
.tx_offset = {
.serdes = 0x234c, /* 17.6484848 */
.no_fec = 0x5a8a, /* 45.27 */
.fc = 0x81b8, /* 64.86 */
.sfd = 0x4a4, /* 2.32 */
.onestep = 0x1333 /* 9.6 */
},
.rx_offset = {
.serdes = 0xffffeb27, /* -10.42424 */
.no_fec = 0xfffff594, /* -5.21 */
.fc = 0xfffe3080, /* -231.75 */
.sfd = 0x4a4, /* 2.32 */
.bs_ds = 0xccd /* 6.4 */
}
},
[ICE_ETH56G_LNK_SPD_50G] = {
.tx_mode = { .def = 5 },
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = { .def = 5 },
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x28f, /* 1.28 */
.mktime = 0xa3d, /* 5.12 */
.tx_offset = {
.serdes = 0x13ba, /* 9.86353 */
.rs = 0x5400, /* 42 */
.sfd = 0xe6, /* 0.45 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7e8, /* -4.04706 */
.rs = 0xfffff994, /* -3.21 */
.sfd = 0xe6 /* 0.45 */
}
},
[ICE_ETH56G_LNK_SPD_50G2] = {
.tx_mode = {
.def = 3,
.rs = 2
},
.tx_mk_dly = 4,
.tx_cw_dly = {
.def = 1,
.onestep = 6
},
.rx_mode = {
.def = 4,
.rs = 1
},
.rx_mk_dly = { .def = 1 },
.rx_cw_dly = { .def = 1 },
.blktime = 0x28f, /* 1.28 */
.mktime = 0xa3d, /* 5.12 */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x3d33, /* 30.6 */
.rs = 0x5057, /* 40.17 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xfffff8cd, /* -3.6 */
.rs = 0xfffff21a, /* -6.95 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0xa3d /* 5.12, RS-FEC 0x633 (3.1) */
}
},
[ICE_ETH56G_LNK_SPD_100G] = {
.tx_mode = {
.def = 3,
.rs = 2
},
.tx_mk_dly = 10,
.tx_cw_dly = {
.def = 3,
.onestep = 6
},
.rx_mode = {
.def = 4,
.rs = 1
},
.rx_mk_dly = { .def = 5 },
.rx_cw_dly = { .def = 5 },
.blks_per_clk = 1,
.blktime = 0x148, /* 0.64 */
.mktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0xe1e, /* 7.0593939 */
.no_fec = 0x67ec, /* 51.96 */
.rs = 0x44fb, /* 34.49 */
.sfd = 0x1dc, /* 0.93 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7a9, /* -4.1697 */
.no_fec = 0xfffff5a9, /* -5.17 */
.rs = 0xfffff6e6, /* -4.55 */
.sfd = 0x1dc, /* 0.93 */
.bs_ds = 0x199a /* 12.8, RS-FEC 0x31b (1.552) */
}
},
[ICE_ETH56G_LNK_SPD_100G2] = {
.tx_mode = { .def = 5 },
.tx_mk_dly = 10,
.tx_cw_dly = {
.def = 3,
.onestep = 6
},
.rx_mode = { .def = 5 },
.rx_mk_dly = { .def = 5 },
.rx_cw_dly = { .def = 5 },
.blks_per_clk = 1,
.blktime = 0x148, /* 0.64 */
.mktime = 0x199a, /* 12.8 */
.tx_offset = {
.serdes = 0x13ba, /* 9.86353 */
.rs = 0x460a, /* 35.02 */
.sfd = 0xe6, /* 0.45 */
.onestep = 0xf5c /* 7.68 */
},
.rx_offset = {
.serdes = 0xfffff7e8, /* -4.04706 */
.rs = 0xfffff548, /* -5.36 */
.sfd = 0xe6, /* 0.45 */
.bs_ds = 0x303 /* 1.506 */
}
}
};
/* struct ice_time_ref_info_e82x
*
* E822 hardware can use different sources as the reference for the PTP
......@@ -155,6 +470,93 @@ const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
},
};
const
struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
{
/* tspll_ck_refclkfreq */
0x19,
/* tspll_ndivratio */
1,
/* tspll_fbdiv_intgr */
320,
/* tspll_fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
{
/* tspll_ck_refclkfreq */
0x29,
/* tspll_ndivratio */
3,
/* tspll_fbdiv_intgr */
195,
/* tspll_fbdiv_frac */
1342177280UL,
/* ref1588_ck_div */
0,
},
/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
{
/* tspll_ck_refclkfreq */
0x3E,
/* tspll_ndivratio */
2,
/* tspll_fbdiv_intgr */
128,
/* tspll_fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
{
/* tspll_ck_refclkfreq */
0x33,
/* tspll_ndivratio */
3,
/* tspll_fbdiv_intgr */
156,
/* tspll_fbdiv_frac */
1073741824UL,
/* ref1588_ck_div */
0,
},
/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
{
/* tspll_ck_refclkfreq */
0x1F,
/* tspll_ndivratio */
5,
/* tspll_fbdiv_intgr */
256,
/* tspll_fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
{
/* tspll_ck_refclkfreq */
0x52,
/* tspll_ndivratio */
3,
/* tspll_fbdiv_intgr */
97,
/* tspll_fbdiv_frac */
2818572288UL,
/* ref1588_ck_div */
0,
},
};
/* struct ice_vernier_info_e82x
*
* E822 hardware calibrates the delay of the timestamp indication from the
......
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View file @ fc5570e0
......@@ -2,6 +2,7 @@
/* Copyright (C) 2021, Intel Corporation. */
#include <linux/delay.h>
#include <linux/iopoll.h>
#include "ice_common.h"
#include "ice_ptp_hw.h"
#include "ice_ptp_consts.h"
......@@ -226,59 +227,2477 @@ static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
}
/**
* ice_read_cgu_reg_e82x - Read a CGU register
* @hw: pointer to the HW struct
* @addr: Register address to read
* @val: storage for register value read
*
* Read the contents of a register of the Clock Generation Unit. Only
* applicable to E822 devices.
*
* Return: 0 on success, other error codes when failed to read from CGU
*/
static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
{
struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_rd,
.dest_dev = cgu,
.msg_addr_low = addr
};
int err;
err = ice_sbq_rw_reg(hw, &cgu_msg);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
addr, err);
return err;
}
*val = cgu_msg.data;
return 0;
}
/**
* ice_write_cgu_reg_e82x - Write a CGU register
* @hw: pointer to the HW struct
* @addr: Register address to write
* @val: value to write into the register
*
* Write the specified value to a register of the Clock Generation Unit. Only
* applicable to E822 devices.
*
* Return: 0 on success, other error codes when failed to write to CGU
*/
static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
{
struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_wr,
.dest_dev = cgu,
.msg_addr_low = addr,
.data = val
};
int err;
err = ice_sbq_rw_reg(hw, &cgu_msg);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
addr, err);
return err;
}
return err;
}
/**
* ice_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
*
* Return: specified TIME_REF clock frequency converted to a string
*/
static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
{
switch (clk_freq) {
case ICE_TIME_REF_FREQ_25_000:
return "25 MHz";
case ICE_TIME_REF_FREQ_122_880:
return "122.88 MHz";
case ICE_TIME_REF_FREQ_125_000:
return "125 MHz";
case ICE_TIME_REF_FREQ_153_600:
return "153.6 MHz";
case ICE_TIME_REF_FREQ_156_250:
return "156.25 MHz";
case ICE_TIME_REF_FREQ_245_760:
return "245.76 MHz";
default:
return "Unknown";
}
}
/**
* ice_clk_src_str - Convert time_ref_src to string
* @clk_src: Clock source
*
* Return: specified clock source converted to its string name
*/
static const char *ice_clk_src_str(enum ice_clk_src clk_src)
{
switch (clk_src) {
case ICE_CLK_SRC_TCXO:
return "TCXO";
case ICE_CLK_SRC_TIME_REF:
return "TIME_REF";
default:
return "Unknown";
}
}
/**
* ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
* @hw: pointer to the HW struct
* @clk_freq: Clock frequency to program
* @clk_src: Clock source to select (TIME_REF, or TCXO)
*
* Configure the Clock Generation Unit with the desired clock frequency and
* time reference, enabling the PLL which drives the PTP hardware clock.
*
* Return:
* * %0 - success
* * %-EINVAL - input parameters are incorrect
* * %-EBUSY - failed to lock TS PLL
* * %other - CGU read/write failure
*/
static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
enum ice_time_ref_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_bwm_lf bwm_lf;
union nac_cgu_dword19 dw19;
union nac_cgu_dword22 dw22;
union nac_cgu_dword24 dw24;
union nac_cgu_dword9 dw9;
int err;
if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
clk_freq);
return -EINVAL;
}
if (clk_src >= NUM_ICE_CLK_SRC) {
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
clk_src);
return -EINVAL;
}
if (clk_src == ICE_CLK_SRC_TCXO &&
clk_freq != ICE_TIME_REF_FREQ_25_000) {
dev_warn(ice_hw_to_dev(hw),
"TCXO only supports 25 MHz frequency\n");
return -EINVAL;
}
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw24.time_ref_sel),
ice_clk_freq_str(dw9.time_ref_freq_sel),
bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
dw24.ts_pll_enable = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
if (err)
return err;
/* Configure the TS PLL feedback divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
if (err)
return err;
dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
dw19.tspll_ndivratio = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
if (err)
return err;
/* Configure the TS PLL post divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
if (err)
return err;
dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
dw22.time1588clk_sel_div2 = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
if (err)
return err;
/* Configure the TS PLL pre divisor and clock source */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
if (err)
return err;
dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
dw24.time_ref_sel = clk_src;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
/* Finally, enable the PLL */
dw24.ts_pll_enable = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
if (!bwm_lf.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
return -EBUSY;
}
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw24.time_ref_sel),
ice_clk_freq_str(dw9.time_ref_freq_sel),
bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
return 0;
}
/**
* ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
* @hw: pointer to the HW struct
* @clk_freq: Clock frequency to program
* @clk_src: Clock source to select (TIME_REF, or TCXO)
*
* Configure the Clock Generation Unit with the desired clock frequency and
* time reference, enabling the PLL which drives the PTP hardware clock.
*
* Return:
* * %0 - success
* * %-EINVAL - input parameters are incorrect
* * %-EBUSY - failed to lock TS PLL
* * %other - CGU read/write failure
*/
static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
enum ice_time_ref_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_lock_e825c ro_lock;
union nac_cgu_dword16_e825c dw16;
union nac_cgu_dword23_e825c dw23;
union nac_cgu_dword19 dw19;
union nac_cgu_dword22 dw22;
union nac_cgu_dword24 dw24;
union nac_cgu_dword9 dw9;
int err;
if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
clk_freq);
return -EINVAL;
}
if (clk_src >= NUM_ICE_CLK_SRC) {
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
clk_src);
return -EINVAL;
}
if (clk_src == ICE_CLK_SRC_TCXO &&
clk_freq != ICE_TIME_REF_FREQ_156_250) {
dev_warn(ice_hw_to_dev(hw),
"TCXO only supports 156.25 MHz frequency\n");
return -EINVAL;
}
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (err)
return err;
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw23.time_ref_sel),
ice_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
dw23.ts_pll_enable = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
dw23.val);
if (err)
return err;
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
/* Enable the correct receiver */
if (clk_src == ICE_CLK_SRC_TCXO) {
dw9.time_ref_en = 0;
dw9.clk_eref0_en = 1;
} else {
dw9.time_ref_en = 1;
dw9.clk_eref0_en = 0;
}
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
if (err)
return err;
/* Choose the referenced frequency */
dw16.tspll_ck_refclkfreq =
e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
if (err)
return err;
/* Configure the TS PLL feedback divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
if (err)
return err;
dw19.tspll_fbdiv_intgr =
e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
dw19.tspll_ndivratio =
e825c_cgu_params[clk_freq].tspll_ndivratio;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
if (err)
return err;
/* Configure the TS PLL post divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
if (err)
return err;
/* These two are constant for E825C */
dw22.time1588clk_div = 5;
dw22.time1588clk_sel_div2 = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
if (err)
return err;
/* Configure the TS PLL pre divisor and clock source */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
if (err)
return err;
dw23.ref1588_ck_div =
e825c_cgu_params[clk_freq].ref1588_ck_div;
dw23.time_ref_sel = clk_src;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
if (err)
return err;
dw24.tspll_fbdiv_frac =
e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
/* Finally, enable the PLL */
dw23.ts_pll_enable = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
if (err)
return err;
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
if (err)
return err;
if (!ro_lock.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
return -EBUSY;
}
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw23.time_ref_sel),
ice_clk_freq_str(dw9.time_ref_freq_sel),
ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
return 0;
}
/**
* ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
* @hw: pointer to the HW struct
*
* Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
* losing TS PLL lock, but always show current state.
*
* Return: 0 on success, other error codes when failed to read/write CGU
*/
static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
{
union tspll_cntr_bist_settings cntr_bist;
int err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
&cntr_bist.val);
if (err)
return err;
/* Disable sticky lock detection so lock err reported is accurate */
cntr_bist.i_plllock_sel_0 = 0;
cntr_bist.i_plllock_sel_1 = 0;
return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
cntr_bist.val);
}
/**
* ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
* @hw: pointer to the HW struct
*
* Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
* losing TS PLL lock, but always show current state.
*
* Return: 0 on success, other error codes when failed to read/write CGU
*/
static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
union tspll_bw_tdc_e825c bw_tdc;
int err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
if (err)
return err;
bw_tdc.i_plllock_sel_1_0 = 0;
return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
}
/**
* ice_init_cgu_e82x - Initialize CGU with settings from firmware
* @hw: pointer to the HW structure
*
* Initialize the Clock Generation Unit of the E822 device.
*
* Return: 0 on success, other error codes when failed to read/write/cfg CGU
*/
static int ice_init_cgu_e82x(struct ice_hw *hw)
{
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
int err;
/* Disable sticky lock detection so lock err reported is accurate */
if (ice_is_e825c(hw))
err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
else
err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
if (err)
return err;
/* Configure the CGU PLL using the parameters from the function
* capabilities.
*/
if (ice_is_e825c(hw))
err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
(enum ice_clk_src)ts_info->clk_src);
else
err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
(enum ice_clk_src)ts_info->clk_src);
return err;
}
/**
* ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
* @hw: pointer to HW struct
* @cmd: Timer command
*
* Return: the source timer command register value for the given PTP timer
* command.
*/
static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
enum ice_ptp_tmr_cmd cmd)
{
u32 cmd_val, tmr_idx;
switch (cmd) {
case ICE_PTP_INIT_TIME:
cmd_val = GLTSYN_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
cmd_val = GLTSYN_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
cmd_val = GLTSYN_CMD_ADJ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
break;
case ICE_PTP_NOP:
case ICE_PTP_READ_TIME:
cmd_val = GLTSYN_CMD_READ_TIME;
break;
default:
dev_warn(ice_hw_to_dev(hw),
"Ignoring unrecognized timer command %u\n", cmd);
cmd_val = 0;
}
tmr_idx = ice_get_ptp_src_clock_index(hw);
return tmr_idx << SEL_CPK_SRC | cmd_val;
}
/**
* ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
* @hw: pointer to HW struct
* @cmd: Timer command
*
* Note that some hardware families use a different command register value for
* the PHY ports, while other hardware families use the same register values
* as the source timer.
*
* Return: the PHY port timer command register value for the given PTP timer
* command.
*/
static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
enum ice_ptp_tmr_cmd cmd)
{
u32 cmd_val, tmr_idx;
/* Certain hardware families share the same register values for the
* port register and source timer register.
*/
switch (hw->ptp.phy_model) {
case ICE_PHY_E810:
return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
default:
break;
}
switch (cmd) {
case ICE_PTP_INIT_TIME:
cmd_val = PHY_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
cmd_val = PHY_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
cmd_val = PHY_CMD_ADJ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
break;
case ICE_PTP_READ_TIME:
cmd_val = PHY_CMD_READ_TIME;
break;
case ICE_PTP_NOP:
cmd_val = 0;
break;
default:
dev_warn(ice_hw_to_dev(hw),
"Ignoring unrecognized timer command %u\n", cmd);
cmd_val = 0;
}
tmr_idx = ice_get_ptp_src_clock_index(hw);
return tmr_idx << SEL_PHY_SRC | cmd_val;
}
/**
* ice_ptp_src_cmd - Prepare source timer for a timer command
* @hw: pointer to HW structure
* @cmd: Timer command
*
* Prepare the source timer for an upcoming timer sync command.
* Prepare the source timer for an upcoming timer sync command.
*/
void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
{
u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
wr32(hw, GLTSYN_CMD, cmd_val);
}
/**
* ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
* @hw: pointer to HW struct
*
* Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
* write immediately. This triggers the hardware to begin executing all of the
* source and PHY timer commands synchronously.
*/
static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
{
struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
ice_flush(hw);
}
/* 56G PHY device functions
*
* The following functions operate on devices with the ETH 56G PHY.
*/
/**
* ice_write_phy_eth56g - Write a PHY port register
* @hw: pointer to the HW struct
* @phy_idx: PHY index
* @addr: PHY register address
* @val: Value to write
*
* Return: 0 on success, other error codes when failed to write to PHY
*/
static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
u32 val)
{
struct ice_sbq_msg_input phy_msg;
int err;
phy_msg.opcode = ice_sbq_msg_wr;
phy_msg.msg_addr_low = lower_16_bits(addr);
phy_msg.msg_addr_high = upper_16_bits(addr);
phy_msg.data = val;
phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
err = ice_sbq_rw_reg(hw, &phy_msg);
if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
return err;
}
/**
* ice_read_phy_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @phy_idx: PHY index
* @addr: PHY register address
* @val: Value to write
*
* Return: 0 on success, other error codes when failed to read from PHY
*/
static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
u32 *val)
{
struct ice_sbq_msg_input phy_msg;
int err;
phy_msg.opcode = ice_sbq_msg_rd;
phy_msg.msg_addr_low = lower_16_bits(addr);
phy_msg.msg_addr_high = upper_16_bits(addr);
phy_msg.data = 0;
phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
err = ice_sbq_rw_reg(hw, &phy_msg);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
err);
return err;
}
*val = phy_msg.data;
return 0;
}
/**
* ice_phy_res_address_eth56g - Calculate a PHY port register address
* @port: Port number to be written
* @res_type: resource type (register/memory)
* @offset: Offset from PHY port register base
* @addr: The result address
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
*/
static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type,
u32 offset, u32 *addr)
{
u8 lane = port % ICE_PORTS_PER_QUAD;
u8 phy = ICE_GET_QUAD_NUM(port);
if (res_type >= NUM_ETH56G_PHY_RES)
return -EINVAL;
*addr = eth56g_phy_res[res_type].base[phy] +
lane * eth56g_phy_res[res_type].step + offset;
return 0;
}
/**
* ice_write_port_eth56g - Write a PHY port register
* @hw: pointer to the HW struct
* @offset: PHY register offset
* @port: Port number
* @val: Value to write
* @res_type: resource type (register/memory)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 val, enum eth56g_res_type res_type)
{
u8 phy_port = port % hw->ptp.ports_per_phy;
u8 phy_idx = port / hw->ptp.ports_per_phy;
u32 addr;
int err;
if (port >= hw->ptp.num_lports)
return -EINVAL;
err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
if (err)
return err;
return ice_write_phy_eth56g(hw, phy_idx, addr, val);
}
/**
* ice_read_port_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @offset: PHY register offset
* @port: Port number
* @val: Value to write
* @res_type: resource type (register/memory)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 *val, enum eth56g_res_type res_type)
{
u8 phy_port = port % hw->ptp.ports_per_phy;
u8 phy_idx = port / hw->ptp.ports_per_phy;
u32 addr;
int err;
if (port >= hw->ptp.num_lports)
return -EINVAL;
err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
if (err)
return err;
return ice_read_phy_eth56g(hw, phy_idx, addr, val);
}
/**
* ice_write_ptp_reg_eth56g - Write a PHY port register
* @hw: pointer to the HW struct
* @port: Port number to be written
* @offset: Offset from PHY port register base
* @val: Value to write
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 val)
{
return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
}
/**
* ice_write_mac_reg_eth56g - Write a MAC PHY port register
* parameter
* @hw: pointer to the HW struct
* @port: Port number to be written
* @offset: Offset from PHY port register base
* @val: Value to write
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 val)
{
return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
}
/**
* ice_write_xpcs_reg_eth56g - Write a PHY port register
* @hw: pointer to the HW struct
* @port: Port number to be written
* @offset: Offset from PHY port register base
* @val: Value to write
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
u32 val)
{
return ice_write_port_eth56g(hw, port, offset, val,
ETH56G_PHY_REG_XPCS);
}
/**
* ice_read_ptp_reg_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @port: Port number to be read
* @offset: Offset from PHY port register base
* @val: Pointer to the value to read (out param)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 *val)
{
return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
}
/**
* ice_read_mac_reg_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @port: Port number to be read
* @offset: Offset from PHY port register base
* @val: Pointer to the value to read (out param)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 *val)
{
return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
}
/**
* ice_read_gpcs_reg_eth56g - Read a PHY port register
* @hw: pointer to the HW struct
* @port: Port number to be read
* @offset: Offset from PHY port register base
* @val: Pointer to the value to read (out param)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 *val)
{
return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS);
}
/**
* ice_read_port_mem_eth56g - Read a PHY port memory location
* @hw: pointer to the HW struct
* @port: Port number to be read
* @offset: Offset from PHY port register base
* @val: Pointer to the value to read (out param)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to read from PHY
*/
static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 *val)
{
return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
}
/**
* ice_write_port_mem_eth56g - Write a PHY port memory location
* @hw: pointer to the HW struct
* @port: Port number to be read
* @offset: Offset from PHY port register base
* @val: Pointer to the value to read (out param)
*
* Return:
* * %0 - success
* * %EINVAL - invalid port number or resource type
* * %other - failed to write to PHY
*/
static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
u32 val)
{
return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
}
/**
* ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
* @low_addr: the low address to check
* @high_addr: on return, contains the high address of the 64bit register
*
* Write the appropriate high register offset to use.
*
* Return: true if the provided low address is one of the known 64bit PHY values
* represented as two 32bit registers, false otherwise.
*/
static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
{
switch (low_addr) {
case PHY_REG_TX_TIMER_INC_PRE_L:
*high_addr = PHY_REG_TX_TIMER_INC_PRE_U;
return true;
case PHY_REG_RX_TIMER_INC_PRE_L:
*high_addr = PHY_REG_RX_TIMER_INC_PRE_U;
return true;
case PHY_REG_TX_CAPTURE_L:
*high_addr = PHY_REG_TX_CAPTURE_U;
return true;
case PHY_REG_RX_CAPTURE_L:
*high_addr = PHY_REG_RX_CAPTURE_U;
return true;
case PHY_REG_TOTAL_TX_OFFSET_L:
*high_addr = PHY_REG_TOTAL_TX_OFFSET_U;
return true;
case PHY_REG_TOTAL_RX_OFFSET_L:
*high_addr = PHY_REG_TOTAL_RX_OFFSET_U;
return true;
case PHY_REG_TX_MEMORY_STATUS_L:
*high_addr = PHY_REG_TX_MEMORY_STATUS_U;
return true;
default:
return false;
}
}
/**
* ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
* @low_addr: the low address to check
* @high_addr: on return, contains the high address of the 40bit value
*
* Write the appropriate high register offset to use.
*
* Return: true if the provided low address is one of the known 40bit PHY
* values split into two registers with the lower 8 bits in the low register and
* the upper 32 bits in the high register, false otherwise.
*/
static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
{
switch (low_addr) {
case PHY_REG_TIMETUS_L:
*high_addr = PHY_REG_TIMETUS_U;
return true;
case PHY_PCS_REF_TUS_L:
*high_addr = PHY_PCS_REF_TUS_U;
return true;
case PHY_PCS_REF_INC_L:
*high_addr = PHY_PCS_REF_INC_U;
return true;
default:
return false;
}
}
/**
* ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
* @hw: pointer to the HW struct
* @port: PHY port to read from
* @low_addr: offset of the lower register to read from
* @val: on return, the contents of the 64bit value from the PHY registers
* @res_type: resource type
*
* Check if the caller has specified a known 40 bit register offset and read
* the two registers associated with a 40bit value and return it in the val
* pointer.
*
* Return:
* * %0 - success
* * %EINVAL - not a 64 bit register
* * %other - failed to read from PHY
*/
static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
u64 *val, enum eth56g_res_type res_type)
{
u16 high_addr;
u32 lo, hi;
int err;
if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
return -EINVAL;
err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
low_addr, err);
return err;
}
err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
high_addr, err);
return err;
}
*val = ((u64)hi << 32) | lo;
return 0;
}
/**
* ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
* @hw: pointer to the HW struct
* @port: PHY port to read from
* @low_addr: offset of the lower register to read from
* @val: on return, the contents of the 64bit value from the PHY registers
*
* Check if the caller has specified a known 40 bit register offset and read
* the two registers associated with a 40bit value and return it in the val
* pointer.
*
* Return:
* * %0 - success
* * %EINVAL - not a 64 bit register
* * %other - failed to read from PHY
*/
static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
u64 *val)
{
return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val,
ETH56G_PHY_REG_PTP);
}
/**
* ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
* @hw: pointer to the HW struct
* @port: port to write to
* @low_addr: offset of the low register
* @val: 40b value to write
* @res_type: resource type
*
* Check if the caller has specified a known 40 bit register offset and write
* provided 40b value to the two associated registers by splitting it up into
* two chunks, the lower 8 bits and the upper 32 bits.
*
* Return:
* * %0 - success
* * %EINVAL - not a 40 bit register
* * %other - failed to write to PHY
*/
static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val,
enum eth56g_res_type res_type)
{
u16 high_addr;
u32 lo, hi;
int err;
if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr))
return -EINVAL;
lo = FIELD_GET(P_REG_40B_LOW_M, val);
hi = (u32)(val >> P_REG_40B_HIGH_S);
err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
low_addr, err);
return err;
}
err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
high_addr, err);
return err;
}
return 0;
}
/**
* ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
* @hw: pointer to the HW struct
* @port: port to write to
* @low_addr: offset of the low register
* @val: 40b value to write
*
* Check if the caller has specified a known 40 bit register offset and write
* provided 40b value to the two associated registers by splitting it up into
* two chunks, the lower 8 bits and the upper 32 bits.
*
* Return:
* * %0 - success
* * %EINVAL - not a 40 bit register
* * %other - failed to write to PHY
*/
static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val)
{
return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val,
ETH56G_PHY_REG_PTP);
}
/**
* ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
* @hw: pointer to the HW struct
* @port: PHY port to read from
* @low_addr: offset of the lower register to read from
* @val: the contents of the 64bit value to write to PHY
* @res_type: resource type
*
* Check if the caller has specified a known 64 bit register offset and write
* the 64bit value to the two associated 32bit PHY registers.
*
* Return:
* * %0 - success
* * %EINVAL - not a 64 bit register
* * %other - failed to write to PHY
*/
static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val,
enum eth56g_res_type res_type)
{
u16 high_addr;
u32 lo, hi;
int err;
if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
return -EINVAL;
lo = lower_32_bits(val);
hi = upper_32_bits(val);
err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
low_addr, err);
return err;
}
err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
high_addr, err);
return err;
}
return 0;
}
/**
* ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
* @hw: pointer to the HW struct
* @port: PHY port to read from
* @low_addr: offset of the lower register to read from
* @val: the contents of the 64bit value to write to PHY
*
* Check if the caller has specified a known 64 bit register offset and write
* the 64bit value to the two associated 32bit PHY registers.
*
* Return:
* * %0 - success
* * %EINVAL - not a 64 bit register
* * %other - failed to write to PHY
*/
static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val)
{
return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val,
ETH56G_PHY_REG_PTP);
}
/**
* ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
* @hw: pointer to the HW struct
* @port: the port to read from
* @idx: the timestamp index to read
* @tstamp: on return, the 40bit timestamp value
*
* Read a 40bit timestamp value out of the two associated entries in the
* port memory block of the internal PHYs of the 56G devices.
*
* Return:
* * %0 - success
* * %other - failed to read from PHY
*/
static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
u64 *tstamp)
{
u16 lo_addr, hi_addr;
u32 lo, hi;
int err;
lo_addr = (u16)PHY_TSTAMP_L(idx);
hi_addr = (u16)PHY_TSTAMP_U(idx);
err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
err);
return err;
}
err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
err);
return err;
}
/* For 56G based internal PHYs, the timestamp is reported with the
* lower 8 bits in the low register, and the upper 32 bits in the high
* register.
*/
*tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
return 0;
}
/**
* ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
* @hw: pointer to the HW struct
* @port: the quad to read from
* @idx: the timestamp index to reset
*
* Read and then forcibly clear the timestamp index to ensure the valid bit is
* cleared and the timestamp status bit is reset in the PHY port memory of
* internal PHYs of the 56G devices.
*
* To directly clear the contents of the timestamp block entirely, discarding
* all timestamp data at once, software should instead use
* ice_ptp_reset_ts_memory_quad_eth56g().
*
* This function should only be called on an idx whose bit is set according to
* ice_get_phy_tx_tstamp_ready().
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
{
u64 unused_tstamp;
u16 lo_addr;
int err;
/* Read the timestamp register to ensure the timestamp status bit is
* cleared.
*/
err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
port, idx, err);
}
lo_addr = (u16)PHY_TSTAMP_L(idx);
err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
port, idx, err);
return err;
}
return 0;
}
/**
* ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
* @hw: pointer to the HW struct
*/
static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
{
unsigned int port;
for (port = 0; port < hw->ptp.num_lports; port++) {
ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
0);
ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
0);
}
}
/**
* ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
* @hw: pointer to the HW struct
* @port: port number
* @time: time to initialize the PHY port clocks to
*
* Write a new initial time value into registers of a specific PHY port.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port,
u64 time)
{
int err;
/* Tx case */
err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
time);
if (err)
return err;
/* Rx case */
return ice_write_64b_ptp_reg_eth56g(hw, port,
PHY_REG_RX_TIMER_INC_PRE_L, time);
}
/**
* ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
* @hw: pointer to the HW struct
* @time: Time to initialize the PHY port clocks to
*
* Program the PHY port registers with a new initial time value. The port
* clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
* command. The time value is the upper 32 bits of the PHY timer, usually in
* units of nominal nanoseconds.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
{
u64 phy_time;
u8 port;
/* The time represents the upper 32 bits of the PHY timer, so we need
* to shift to account for this when programming.
*/
phy_time = (u64)time << 32;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
port, err);
return err;
}
}
return 0;
}
/**
* ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
* @hw: pointer to HW struct
* @port: Port number to be programmed
* @time: time in cycles to adjust the port clocks
*
* Program the port for an atomic adjustment by writing the Tx and Rx timer
* registers. The atomic adjustment won't be completed until the driver issues
* an ICE_PTP_ADJ_TIME command.
*
* Note that time is not in units of nanoseconds. It is in clock time
* including the lower sub-nanosecond portion of the port timer.
*
* Negative adjustments are supported using 2s complement arithmetic.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time)
{
u32 l_time, u_time;
int err;
l_time = lower_32_bits(time);
u_time = upper_32_bits(time);
/* Tx case */
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
l_time);
if (err)
goto exit_err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
u_time);
if (err)
goto exit_err;
/* Rx case */
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
l_time);
if (err)
goto exit_err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
u_time);
if (err)
goto exit_err;
return 0;
exit_err:
ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
port, err);
return err;
}
/**
* ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
* @hw: pointer to HW struct
* @adj: adjustment in nanoseconds
*
* Prepare the PHY ports for an atomic time adjustment by programming the PHY
* Tx and Rx port registers. The actual adjustment is completed by issuing an
* ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj)
{
s64 cycles;
u8 port;
/* The port clock supports adjustment of the sub-nanosecond portion of
* the clock (lowest 32 bits). We shift the provided adjustment in
* nanoseconds by 32 to calculate the appropriate adjustment to program
* into the PHY ports.
*/
cycles = (s64)adj << 32;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles);
if (err)
return err;
}
return 0;
}
/**
* ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
* @hw: pointer to HW struct
* @incval: new increment value to prepare
*
* Prepare each of the PHY ports for a new increment value by programming the
* port's TIMETUS registers. The new increment value will be updated after
* issuing an ICE_PTP_INIT_INCVAL command.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
{
u8 port;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
incval);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
port, err);
return err;
}
}
return 0;
}
/**
* ice_ptp_read_port_capture_eth56g - Read a port's local time capture
* @hw: pointer to HW struct
* @port: Port number to read
* @tx_ts: on return, the Tx port time capture
* @rx_ts: on return, the Rx port time capture
*
* Read the port's Tx and Rx local time capture values.
*
* Return:
* * %0 - success
* * %other - failed to read from PHY
*/
static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
u64 *tx_ts, u64 *rx_ts)
{
int err;
/* Tx case */
err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
tx_ts);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
err);
return err;
}
ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
/* Rx case */
err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
rx_ts);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
err);
return err;
}
ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
return 0;
}
/**
* ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
* @hw: pointer to HW struct
* @port: Port to which cmd has to be sent
* @cmd: Command to be sent to the port
*
* Prepare the requested port for an upcoming timer sync command.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd)
{
u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
int err;
/* Tx case */
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
err);
return err;
}
/* Rx case */
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
err);
return err;
}
return 0;
}
/**
* ice_phy_get_speed_eth56g - Get link speed based on PHY link type
* @li: pointer to link information struct
*
* Return: simplified ETH56G PHY speed
*/
static enum ice_eth56g_link_spd
ice_phy_get_speed_eth56g(struct ice_link_status *li)
{
u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low,
li->phy_type_high);
switch (speed) {
case ICE_AQ_LINK_SPEED_1000MB:
return ICE_ETH56G_LNK_SPD_1G;
case ICE_AQ_LINK_SPEED_2500MB:
return ICE_ETH56G_LNK_SPD_2_5G;
case ICE_AQ_LINK_SPEED_10GB:
return ICE_ETH56G_LNK_SPD_10G;
case ICE_AQ_LINK_SPEED_25GB:
return ICE_ETH56G_LNK_SPD_25G;
case ICE_AQ_LINK_SPEED_40GB:
return ICE_ETH56G_LNK_SPD_40G;
case ICE_AQ_LINK_SPEED_50GB:
switch (li->phy_type_low) {
case ICE_PHY_TYPE_LOW_50GBASE_SR:
case ICE_PHY_TYPE_LOW_50GBASE_FR:
case ICE_PHY_TYPE_LOW_50GBASE_LR:
case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
case ICE_PHY_TYPE_LOW_50G_AUI1:
return ICE_ETH56G_LNK_SPD_50G;
default:
return ICE_ETH56G_LNK_SPD_50G2;
}
case ICE_AQ_LINK_SPEED_100GB:
if (li->phy_type_high ||
li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2)
return ICE_ETH56G_LNK_SPD_100G2;
else
return ICE_ETH56G_LNK_SPD_100G;
default:
return ICE_ETH56G_LNK_SPD_1G;
}
}
/**
* ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
* @hw: pointer to the HW struct
* @port: port to configure
*
* Configure the number of TUs for the PAR and PCS clocks used as part of the
* timestamp calibration process.
*
* Return:
* * %0 - success
* * %other - PHY read/write failed
*/
static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
{
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u32 val;
int err;
err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH,
ICE_ETH56G_NOMINAL_THRESH4);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
err);
return err;
}
switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
case ICE_ETH56G_LNK_SPD_1G:
case ICE_ETH56G_LNK_SPD_2_5G:
err = ice_read_ptp_reg_eth56g(hw, port_blk,
PHY_GPCS_CONFIG_REG0, &val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
err);
return err;
}
val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M;
val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
ICE_ETH56G_NOMINAL_TX_THRESH);
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_GPCS_CONFIG_REG0, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
err);
return err;
}
break;
default:
break;
}
err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L,
ICE_ETH56G_NOMINAL_PCS_REF_TUS);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
err);
return err;
}
err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L,
ICE_ETH56G_NOMINAL_PCS_REF_INC);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
err);
return err;
}
return 0;
}
/**
* ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
* @hw: Pointer to the HW struct
* @port: Port to configure
*
* Return:
* * %0 - success
* * %other - PHY read/write failed
*/
int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
{
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1);
bool enable, sfd_ena;
u32 val, peer_delay;
int err;
enable = hw->ptp.phy.eth56g.onestep_ena;
peer_delay = hw->ptp.phy.eth56g.peer_delay;
sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
/* PHY_PTP_1STEP_CONFIG */
err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val);
if (err)
return err;
if (enable)
val |= blk_port;
else
val &= ~blk_port;
val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val);
if (err)
return err;
/* PHY_PTP_1STEP_PEER_DELAY */
val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
if (peer_delay)
val |= PHY_PTP_1STEP_PD_ADD_PD_M;
val |= PHY_PTP_1STEP_PD_DLY_V_M;
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
if (err)
return err;
val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
err = ice_write_ptp_reg_eth56g(hw, port_blk,
PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
if (err)
return err;
/* PHY_MAC_XIF_MODE */
err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val);
if (err)
return err;
val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M |
PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M);
switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
case ICE_ETH56G_LNK_SPD_1G:
case ICE_ETH56G_LNK_SPD_2_5G:
val |= PHY_MAC_XIF_GMII_TS_SEL_M;
break;
default:
break;
}
val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) |
FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val);
}
/**
* mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
* @a: multiplier value
* @b: multiplicand value
*
* Return: result of multiplication
*/
static u32 mul_u32_u32_fx_q9(u32 a, u32 b)
{
return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
}
/**
* add_u32_u32_fx - Add two u32 fixed point values and discard overflow
* @a: first value
* @b: second value
*
* Return: result of addition
*/
static u32 add_u32_u32_fx(u32 a, u32 b)
{
return lower_32_bits(((u64)a + b));
}
/**
* ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
* @hw: pointer to the HW struct
* @port: port to configure
* @bs: bitslip multiplier
* @fc: FC-FEC enabled
* @rs: RS-FEC enabled
* @spd: link speed
*
* Return: calculated bitslip value
*/
static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
bool fc, bool rs,
enum ice_eth56g_link_spd spd)
{
u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1);
u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
u32 bitslip;
int err;
if (!bs || rs)
return 0;
if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G)
err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
&bitslip);
else
err = ice_read_ptp_reg_eth56g(hw, port_blk,
PHY_REG_SD_BIT_SLIP(port_offset),
&bitslip);
if (err)
return 0;
if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) {
/* Bitslip register value of 0 corresponds to 10 so substitute
* it for calculations
*/
bitslip = 10;
} else if (spd == ICE_ETH56G_LNK_SPD_10G ||
spd == ICE_ETH56G_LNK_SPD_25G) {
if (fc)
bitslip = bitslip * 2 + 32;
else
bitslip = (u32)((s32)bitslip * -1 + 20);
}
bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W;
return mul_u32_u32_fx_q9(bitslip, bs);
}
/**
* ice_ptp_calc_deskew_eth56g - Calculate deskew value
* @hw: pointer to the HW struct
* @port: port to configure
* @ds: deskew multiplier
* @rs: RS-FEC enabled
* @spd: link speed
*
* Return: calculated deskew value
*/
static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
bool rs, enum ice_eth56g_link_spd spd)
{
u32 deskew_i, deskew_f;
int err;
if (!ds)
return 0;
read_poll_timeout(ice_read_ptp_reg_eth56g, err,
FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500,
50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0,
&deskew_i);
if (err)
return err;
deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i);
deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i);
if (rs && spd == ICE_ETH56G_LNK_SPD_50G2)
ds = 0x633; /* 3.1 */
else if (rs && spd == ICE_ETH56G_LNK_SPD_100G)
ds = 0x31b; /* 1.552 */
deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i);
/* Shift 3 fractional bits to the end of the integer part */
deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
}
/**
* ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
* @hw: pointer to the HW struct
* @port: port to configure
* @spd: link speed
* @cfg: structure to store output values
* @fc: FC-FEC enabled
* @rs: RS-FEC enabled
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
enum ice_eth56g_link_spd spd,
const struct ice_eth56g_mac_reg_cfg *cfg,
bool fc, bool rs)
{
u32 rx_offset, tx_offset, bs_ds;
bool onestep, sfd;
onestep = hw->ptp.phy.eth56g.onestep_ena;
sfd = hw->ptp.phy.eth56g.sfd_ena;
bs_ds = cfg->rx_offset.bs_ds;
if (fc)
rx_offset = cfg->rx_offset.fc;
else if (rs)
rx_offset = cfg->rx_offset.rs;
else
rx_offset = cfg->rx_offset.no_fec;
rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes);
if (sfd)
rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd);
if (spd < ICE_ETH56G_LNK_SPD_40G)
bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs,
spd);
else
bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd);
rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
if (fc)
tx_offset = cfg->tx_offset.fc;
else if (rs)
tx_offset = cfg->tx_offset.rs;
else
tx_offset = cfg->tx_offset.no_fec;
tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd +
cfg->tx_offset.onestep * onestep;
ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset);
return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset);
}
/**
* ice_phy_cfg_mac_eth56g - Configure MAC for PTP
* @hw: Pointer to the HW struct
* @port: Port to configure
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)
{
const struct ice_eth56g_mac_reg_cfg *cfg;
enum ice_eth56g_link_spd spd;
struct ice_link_status *li;
bool fc = false;
bool rs = false;
bool onestep;
u32 val;
int err;
onestep = hw->ptp.phy.eth56g.onestep_ena;
li = &hw->port_info->phy.link_info;
spd = ice_phy_get_speed_eth56g(li);
if (!!(li->an_info & ICE_AQ_FEC_EN)) {
if (spd == ICE_ETH56G_LNK_SPD_10G) {
fc = true;
} else {
fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN);
rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN);
}
}
cfg = &eth56g_mac_cfg[spd];
err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0);
if (err)
return err;
err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0);
if (err)
return err;
val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M,
cfg->tx_mode.def + rs * cfg->tx_mode.rs) |
FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) |
FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M,
cfg->tx_cw_dly.def +
onestep * cfg->tx_cw_dly.onestep) |
FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M,
cfg->rx_mode.def + rs * cfg->rx_mode.rs) |
FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M,
cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) |
FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M,
cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) |
FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk);
err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val);
if (err)
return err;
err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME,
cfg->blktime);
if (err)
return err;
err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs);
if (err)
return err;
if (spd == ICE_ETH56G_LNK_SPD_25G && !rs)
val = 0;
else
val = cfg->mktime;
return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val);
}
/**
* ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
* @hw: pointer to the HW struct
* @port: the timestamp port
* @ena: enable or disable interrupt
* @threshold: interrupt threshold
*
* Configure TX timestamp interrupt for the specified port
*
* Return:
* * %0 - success
* * %other - PHY read/write failed
*/
int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
{
int err;
u32 val;
err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
if (err)
return err;
if (ena) {
val |= PHY_TS_INT_CONFIG_ENA_M;
val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
} else {
val &= ~PHY_TS_INT_CONFIG_ENA_M;
}
return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
}
/**
* ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
* @hw: pointer to the HW struct
* @port: the PHY port to read
* @phy_time: on return, the 64bit PHY timer value
* @phc_time: on return, the lower 64bits of PHC time
*
* Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
* and PHC timer values.
*
* Return:
* * %0 - success
* * %other - PHY read/write failed
*/
static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port,
u64 *phy_time, u64 *phc_time)
{
u64 tx_time, rx_time;
u32 zo, lo;
u8 tmr_idx;
int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
/* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
if (err)
return err;
/* Issue the sync to start the ICE_PTP_READ_TIME capture */
ice_ptp_exec_tmr_cmd(hw);
/* Read the captured PHC time from the shadow time registers */
zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
*phc_time = (u64)lo << 32 | zo;
/* Read the captured PHY time from the PHY shadow registers */
err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
if (err)
return err;
/* If the PHY Tx and Rx timers don't match, log a warning message.
* Note that this should not happen in normal circumstances since the
* driver always programs them together.
*/
if (tx_time != rx_time)
dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
port, tx_time, rx_time);
*phy_time = tx_time;
return 0;
}
/**
* ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
* @hw: pointer to the HW struct
* @port: the PHY port to synchronize
*
* Perform an adjustment to ensure that the PHY and PHC timers are in sync.
* This is done by issuing a ICE_PTP_READ_TIME command which triggers a
* simultaneous read of the PHY timer and PHC timer. Then we use the
* difference to calculate an appropriate 2s complement addition to add
* to the PHY timer in order to ensure it reads the same value as the
* primary PHC timer.
*
* Return:
* * %0 - success
* * %-EBUSY- failed to acquire PTP semaphore
* * %other - PHY read/write failed
*/
void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
{
u64 phc_time, phy_time, difference;
int err;
if (!ice_ptp_lock(hw)) {
ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
return -EBUSY;
}
err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
if (err)
goto err_unlock;
/* Calculate the amount required to add to the port time in order for
* it to match the PHC time.
*
* Note that the port adjustment is done using 2s complement
* arithmetic. This is convenient since it means that we can simply
* calculate the difference between the PHC time and the port time,
* and it will be interpreted correctly.
*/
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
difference = phc_time - phy_time;
err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference);
if (err)
goto err_unlock;
err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
if (err)
goto err_unlock;
/* Issue the sync to activate the time adjustment */
ice_ptp_exec_tmr_cmd(hw);
/* Re-capture the timer values to flush the command registers and
* verify that the time was properly adjusted.
*/
err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
if (err)
goto err_unlock;
dev_info(ice_hw_to_dev(hw),
"Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
port, phy_time, phc_time);
err_unlock:
ice_ptp_unlock(hw);
return err;
}
/**
* ice_stop_phy_timer_eth56g - Stop the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to stop
* @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
*
* Stop the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
* initialized or when link speed changes.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
{
int err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
if (err)
return err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
if (err)
return err;
ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
return 0;
}
/**
* ice_start_phy_timer_eth56g - Start the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to start
*
* Start the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
* initialized or when link speed changes.
*
* Return:
* * %0 - success
* * %other - PHY read/write failed
*/
int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
{
u32 cmd_val;
u32 lo, hi;
u64 incval;
u8 tmr_idx;
int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
cmd_val = tmr_idx << SEL_CPK_SRC;
switch (cmd) {
case ICE_PTP_INIT_TIME:
cmd_val |= GLTSYN_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
cmd_val |= GLTSYN_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
cmd_val |= GLTSYN_CMD_ADJ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
break;
case ICE_PTP_READ_TIME:
cmd_val |= GLTSYN_CMD_READ_TIME;
break;
case ICE_PTP_NOP:
break;
}
err = ice_stop_phy_timer_eth56g(hw, port, false);
if (err)
return err;
wr32(hw, GLTSYN_CMD, cmd_val);
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
err = ice_phy_cfg_parpcs_eth56g(hw, port);
if (err)
return err;
err = ice_phy_cfg_ptp_1step_eth56g(hw, port);
if (err)
return err;
err = ice_phy_cfg_mac_eth56g(hw, port);
if (err)
return err;
lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
incval = (u64)hi << 32 | lo;
err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval);
if (err)
return err;
err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
if (err)
return err;
ice_ptp_exec_tmr_cmd(hw);
err = ice_sync_phy_timer_eth56g(hw, port);
if (err)
return err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
if (err)
return err;
err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
if (err)
return err;
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
return 0;
}
/**
* ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
* ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
* @hw: pointer to HW struct
* @enable: Enable or disable access
*
* Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
* write immediately. This triggers the hardware to begin executing all of the
* source and PHY timer commands synchronously.
* Enable sideband devices (PHY and others) access.
*/
static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
{
u32 val = rd32(hw, PF_SB_REM_DEV_CTL);
if (enable)
val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);
else
val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));
wr32(hw, PF_SB_REM_DEV_CTL, val);
}
/**
* ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
* @hw: pointer to HW struct
*
* Perform PHC initialization steps specific to E82X devices.
*
* Return:
* * %0 - success
* * %other - failed to initialize CGU
*/
static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
{
ice_sb_access_ena_eth56g(hw, true);
/* Initialize the Clock Generation Unit */
return ice_init_cgu_e82x(hw);
}
/**
* ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
* @hw: pointer to the HW struct
* @ts_status: the timestamp mask pointer
*
* Read the PHY Tx timestamp status mask indicating which ports have Tx
* timestamps available.
*
* Return:
* * %0 - success
* * %other - failed to read from PHY
*/
int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
{
const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g;
u8 phy, mask;
u32 status;
mask = (1 << hw->ptp.ports_per_phy) - 1;
*ts_status = 0;
for (phy = 0; phy < params->num_phys; phy++) {
int err;
err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status);
if (err)
return err;
*ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy);
}
ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
return 0;
}
/**
* ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
* @hw: pointer to the HW struct
* @port: the PHY port to read from
* @tstamp_ready: contents of the Tx memory status register
*
* Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
* the PHY are ready. A set bit means the corresponding timestamp is valid and
* ready to be captured from the PHY timestamp block.
*
* Return:
* * %0 - success
* * %other - failed to read from PHY
*/
static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
u64 *tstamp_ready)
{
int err;
err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
tstamp_ready);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
port, err);
return err;
}
return 0;
}
/**
* ice_is_muxed_topo - detect breakout 2x50G topology for E825C
* @hw: pointer to the HW struct
*
* Return: true if it's 2x50 breakout topology, false otherwise
*/
static bool ice_is_muxed_topo(struct ice_hw *hw)
{
u8 link_topo;
bool mux;
u32 val;
val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val);
val = rd32(hw, GLGEN_MAC_LINK_TOPO);
link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
}
/**
* ice_ptp_init_phy_e825c - initialize PHY parameters
* @hw: pointer to the HW struct
*/
static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
{
struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
struct ice_ptp_hw *ptp = &hw->ptp;
struct ice_eth56g_params *params;
u8 phy;
ptp->phy_model = ICE_PHY_ETH56G;
params = &ptp->phy.eth56g;
params->onestep_ena = false;
params->peer_delay = 0;
params->sfd_ena = false;
params->phy_addr[0] = eth56g_phy_0;
params->phy_addr[1] = eth56g_phy_1;
params->num_phys = 2;
ptp->ports_per_phy = 4;
ptp->num_lports = params->num_phys * ptp->ports_per_phy;
ice_sb_access_ena_eth56g(hw, true);
for (phy = 0; phy < params->num_phys; phy++) {
u32 phy_rev;
int err;
guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
ice_flush(hw);
err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev);
if (err || phy_rev != PHY_REVISION_ETH56G) {
ptp->phy_model = ICE_PHY_UNSUP;
return;
}
}
ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
}
/* E822 family functions
......@@ -288,18 +2707,21 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
/**
* ice_fill_phy_msg_e82x - Fill message data for a PHY register access
* @hw: pointer to the HW struct
* @msg: the PHY message buffer to fill in
* @port: the port to access
* @offset: the register offset
*/
static void
ice_fill_phy_msg_e82x(struct ice_sbq_msg_input *msg, u8 port, u16 offset)
static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
struct ice_sbq_msg_input *msg, u8 port,
u16 offset)
{
int phy_port, phy, quadtype;
phy_port = port % ICE_PORTS_PER_PHY_E82X;
phy = port / ICE_PORTS_PER_PHY_E82X;
quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E82X;
phy_port = port % hw->ptp.ports_per_phy;
phy = port / hw->ptp.ports_per_phy;
quadtype = ICE_GET_QUAD_NUM(port) %
ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
if (quadtype == 0) {
msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
......@@ -430,7 +2852,7 @@ ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
struct ice_sbq_msg_input msg = {0};
int err;
ice_fill_phy_msg_e82x(&msg, port, offset);
ice_fill_phy_msg_e82x(hw, &msg, port, offset);
msg.opcode = ice_sbq_msg_rd;
err = ice_sbq_rw_reg(hw, &msg);
......@@ -507,7 +2929,7 @@ ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
struct ice_sbq_msg_input msg = {0};
int err;
ice_fill_phy_msg_e82x(&msg, port, offset);
ice_fill_phy_msg_e82x(hw, &msg, port, offset);
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
......@@ -546,8 +2968,7 @@ ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
low_addr);
return -EINVAL;
}
low = (u32)(val & P_REG_40B_LOW_M);
low = FIELD_GET(P_REG_40B_LOW_M, val);
high = (u32)(val >> P_REG_40B_HIGH_S);
err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
......@@ -617,24 +3038,30 @@ ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
/**
* ice_fill_quad_msg_e82x - Fill message data for quad register access
* @hw: pointer to the HW struct
* @msg: the PHY message buffer to fill in
* @quad: the quad to access
* @offset: the register offset
*
* Fill a message buffer for accessing a register in a quad shared between
* multiple PHYs.
*
* Return:
* * %0 - OK
* * %-EINVAL - invalid quad number
*/
static int
ice_fill_quad_msg_e82x(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
static int ice_fill_quad_msg_e82x(struct ice_hw *hw,
struct ice_sbq_msg_input *msg, u8 quad,
u16 offset)
{
u32 addr;
if (quad >= ICE_MAX_QUAD)
if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports))
return -EINVAL;
msg->dest_dev = rmn_0;
if ((quad % ICE_QUADS_PER_PHY_E82X) == 0)
if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy)))
addr = Q_0_BASE + offset;
else
addr = Q_1_BASE + offset;
......@@ -661,7 +3088,7 @@ ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
struct ice_sbq_msg_input msg = {0};
int err;
err = ice_fill_quad_msg_e82x(&msg, quad, offset);
err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
if (err)
return err;
......@@ -695,7 +3122,7 @@ ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
struct ice_sbq_msg_input msg = {0};
int err;
err = ice_fill_quad_msg_e82x(&msg, quad, offset);
err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
if (err)
return err;
......@@ -751,7 +3178,7 @@ ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
* lower 8 bits in the low register, and the upper 32 bits in the high
* register.
*/
*tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
*tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo);
return 0;
}
......@@ -805,302 +3232,19 @@ ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)
void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
{
ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
}
/**
* ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
* @hw: pointer to the HW struct
*/
static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
{
unsigned int quad;
for (quad = 0; quad < ICE_MAX_QUAD; quad++)
ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
}
/**
* ice_read_cgu_reg_e82x - Read a CGU register
* @hw: pointer to the HW struct
* @addr: Register address to read
* @val: storage for register value read
*
* Read the contents of a register of the Clock Generation Unit. Only
* applicable to E822 devices.
*/
static int
ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
{
struct ice_sbq_msg_input cgu_msg;
int err;
cgu_msg.opcode = ice_sbq_msg_rd;
cgu_msg.dest_dev = cgu;
cgu_msg.msg_addr_low = addr;
cgu_msg.msg_addr_high = 0x0;
err = ice_sbq_rw_reg(hw, &cgu_msg);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
addr, err);
return err;
}
*val = cgu_msg.data;
return err;
}
/**
* ice_write_cgu_reg_e82x - Write a CGU register
* @hw: pointer to the HW struct
* @addr: Register address to write
* @val: value to write into the register
*
* Write the specified value to a register of the Clock Generation Unit. Only
* applicable to E822 devices.
*/
static int
ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
{
struct ice_sbq_msg_input cgu_msg;
int err;
cgu_msg.opcode = ice_sbq_msg_wr;
cgu_msg.dest_dev = cgu;
cgu_msg.msg_addr_low = addr;
cgu_msg.msg_addr_high = 0x0;
cgu_msg.data = val;
err = ice_sbq_rw_reg(hw, &cgu_msg);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
addr, err);
return err;
}
return err;
}
/**
* ice_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
*
* Convert the specified TIME_REF clock frequency to a string.
*/
static const char *ice_clk_freq_str(u8 clk_freq)
{
switch ((enum ice_time_ref_freq)clk_freq) {
case ICE_TIME_REF_FREQ_25_000:
return "25 MHz";
case ICE_TIME_REF_FREQ_122_880:
return "122.88 MHz";
case ICE_TIME_REF_FREQ_125_000:
return "125 MHz";
case ICE_TIME_REF_FREQ_153_600:
return "153.6 MHz";
case ICE_TIME_REF_FREQ_156_250:
return "156.25 MHz";
case ICE_TIME_REF_FREQ_245_760:
return "245.76 MHz";
default:
return "Unknown";
}
}
/**
* ice_clk_src_str - Convert time_ref_src to string
* @clk_src: Clock source
*
* Convert the specified clock source to its string name.
*/
static const char *ice_clk_src_str(u8 clk_src)
{
switch ((enum ice_clk_src)clk_src) {
case ICE_CLK_SRC_TCX0:
return "TCX0";
case ICE_CLK_SRC_TIME_REF:
return "TIME_REF";
default:
return "Unknown";
}
}
/**
* ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
* @hw: pointer to the HW struct
* @clk_freq: Clock frequency to program
* @clk_src: Clock source to select (TIME_REF, or TCX0)
*
* Configure the Clock Generation Unit with the desired clock frequency and
* time reference, enabling the PLL which drives the PTP hardware clock.
*/
static int
ice_cfg_cgu_pll_e82x(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
enum ice_clk_src clk_src)
{
union tspll_ro_bwm_lf bwm_lf;
union nac_cgu_dword19 dw19;
union nac_cgu_dword22 dw22;
union nac_cgu_dword24 dw24;
union nac_cgu_dword9 dw9;
int err;
if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
clk_freq);
return -EINVAL;
}
if (clk_src >= NUM_ICE_CLK_SRC) {
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
clk_src);
return -EINVAL;
}
if (clk_src == ICE_CLK_SRC_TCX0 &&
clk_freq != ICE_TIME_REF_FREQ_25_000) {
dev_warn(ice_hw_to_dev(hw),
"TCX0 only supports 25 MHz frequency\n");
return -EINVAL;
}
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
if (err)
return err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.field.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw24.field.time_ref_sel),
ice_clk_freq_str(dw9.field.time_ref_freq_sel),
bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
if (dw24.field.ts_pll_enable) {
dw24.field.ts_pll_enable = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
}
/* Set the frequency */
dw9.field.time_ref_freq_sel = clk_freq;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
if (err)
return err;
/* Configure the TS PLL feedback divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
if (err)
return err;
dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
dw19.field.tspll_ndivratio = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
if (err)
return err;
/* Configure the TS PLL post divisor */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
if (err)
return err;
dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
dw22.field.time1588clk_sel_div2 = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
if (err)
return err;
/* Configure the TS PLL pre divisor and clock source */
err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
if (err)
return err;
dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
dw24.field.time_ref_sel = clk_src;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
/* Finally, enable the PLL */
dw24.field.ts_pll_enable = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
return err;
/* Wait to verify if the PLL locks */
usleep_range(1000, 5000);
err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
if (err)
return err;
if (!bwm_lf.field.plllock_true_lock_cri) {
dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
return -EBUSY;
}
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
dw24.field.ts_pll_enable ? "enabled" : "disabled",
ice_clk_src_str(dw24.field.time_ref_sel),
ice_clk_freq_str(dw9.field.time_ref_freq_sel),
bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
return 0;
}
/**
* ice_init_cgu_e82x - Initialize CGU with settings from firmware
* @hw: pointer to the HW structure
*
* Initialize the Clock Generation Unit of the E822 device.
*/
static int ice_init_cgu_e82x(struct ice_hw *hw)
{
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
union tspll_cntr_bist_settings cntr_bist;
int err;
err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
&cntr_bist.val);
if (err)
return err;
/* Disable sticky lock detection so lock err reported is accurate */
cntr_bist.field.i_plllock_sel_0 = 0;
cntr_bist.field.i_plllock_sel_1 = 0;
err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
cntr_bist.val);
if (err)
return err;
ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
}
/* Configure the CGU PLL using the parameters from the function
* capabilities.
*/
err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
(enum ice_clk_src)ts_info->clk_src);
if (err)
return err;
/**
* ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
* @hw: pointer to the HW struct
*/
static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
{
unsigned int quad;
return 0;
for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++)
ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
}
/**
......@@ -1113,7 +3257,7 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
{
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
......@@ -1137,15 +3281,14 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
{
int err;
u32 regval;
u32 val;
/* Enable reading switch and PHY registers over the sideband queue */
#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
regval = rd32(hw, PF_SB_REM_DEV_CTL);
regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
PF_SB_REM_DEV_CTL_PHY0);
wr32(hw, PF_SB_REM_DEV_CTL, regval);
val = rd32(hw, PF_SB_REM_DEV_CTL);
val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
wr32(hw, PF_SB_REM_DEV_CTL, val);
/* Initialize the Clock Generation Unit */
err = ice_init_cgu_e82x(hw);
......@@ -1178,7 +3321,7 @@ ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)
*/
phy_time = (u64)time << 32;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
for (port = 0; port < hw->ptp.num_lports; port++) {
/* Tx case */
err = ice_write_64b_phy_reg_e82x(hw, port,
P_REG_TX_TIMER_INC_PRE_L,
......@@ -1281,7 +3424,7 @@ ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)
else
cycles = -(((s64)-adj) << 32);
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
......@@ -1307,7 +3450,7 @@ ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)
int err;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
for (port = 0; port < hw->ptp.num_lports; port++) {
err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
incval);
if (err)
......@@ -1372,51 +3515,20 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
*
* Prepare the requested port for an upcoming timer sync command.
*
* Do not use this function directly. If you want to configure exactly one
* port, use ice_ptp_one_port_cmd() instead.
* Note there is no equivalent of this operation on E810, as that device
* always handles all external PHYs internally.
*
* Return:
* * %0 - success
* * %other - failed to write to PHY
*/
static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd)
{
u32 cmd_val, val;
u8 tmr_idx;
u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
cmd_val = tmr_idx << SEL_PHY_SRC;
switch (cmd) {
case ICE_PTP_INIT_TIME:
cmd_val |= PHY_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
cmd_val |= PHY_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
cmd_val |= PHY_CMD_ADJ_TIME;
break;
case ICE_PTP_READ_TIME:
cmd_val |= PHY_CMD_READ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
break;
case ICE_PTP_NOP:
break;
}
/* Tx case */
/* Read, modify, write */
err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, &val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n",
err);
return err;
}
/* Modify necessary bits only and perform write */
val &= ~TS_CMD_MASK;
val |= cmd_val;
err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
......@@ -1425,19 +3537,8 @@ static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
}
/* Rx case */
/* Read, modify, write */
err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, &val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n",
err);
return err;
}
/* Modify necessary bits only and perform write */
val &= ~TS_CMD_MASK;
val |= cmd_val;
err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, val);
err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD,
val | TS_CMD_RX_TYPE);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
err);
......@@ -1447,63 +3548,6 @@ static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
return 0;
}
/**
* ice_ptp_one_port_cmd - Prepare one port for a timer command
* @hw: pointer to the HW struct
* @configured_port: the port to configure with configured_cmd
* @configured_cmd: timer command to prepare on the configured_port
*
* Prepare the configured_port for the configured_cmd, and prepare all other
* ports for ICE_PTP_NOP. This causes the configured_port to execute the
* desired command while all other ports perform no operation.
*/
static int
ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
enum ice_ptp_tmr_cmd configured_cmd)
{
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
enum ice_ptp_tmr_cmd cmd;
int err;
if (port == configured_port)
cmd = configured_cmd;
else
cmd = ICE_PTP_NOP;
err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);
if (err)
return err;
}
return 0;
}
/**
* ice_ptp_port_cmd_e82x - Prepare all ports for a timer command
* @hw: pointer to the HW struct
* @cmd: timer command to prepare
*
* Prepare all ports connected to this device for an upcoming timer sync
* command.
*/
static int
ice_ptp_port_cmd_e82x(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
{
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
int err;
err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);
if (err)
return err;
}
return 0;
}
/* E822 Vernier calibration functions
*
* The following functions are used as part of the vernier calibration of
......@@ -1606,7 +3650,7 @@ static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)
return;
}
quad = port / ICE_PORTS_PER_QUAD;
quad = ICE_GET_QUAD_NUM(port);
err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
if (err) {
......@@ -2326,6 +4370,40 @@ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
return 0;
}
/**
* ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
* @hw: pointer to the HW struct
*
* Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
* and received timestamps as invalid.
*
* Return: 0 on success, other error codes when failed to write to PHY
*/
int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
{
u8 port;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
if (err) {
dev_warn(ice_hw_to_dev(hw),
"Failed to clear PHY TX_OFFSET_READY register\n");
return err;
}
err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
if (err) {
dev_warn(ice_hw_to_dev(hw),
"Failed to clear PHY RX_OFFSET_READY register\n");
return err;
}
}
return 0;
}
/**
* ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
* @hw: pointer to the HW struct
......@@ -2636,6 +4714,48 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
return 0;
}
/**
* ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
* @hw: pointer to the HW struct
* @quad: the timestamp quad
* @ena: enable or disable interrupt
* @threshold: interrupt threshold
*
* Configure TX timestamp interrupt for the specified quad
*
* Return: 0 on success, other error codes when failed to read/write quad
*/
int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
{
int err;
u32 val;
err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
if (err)
return err;
val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
if (ena) {
val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
}
return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
}
/**
* ice_ptp_init_phy_e82x - initialize PHY parameters
* @ptp: pointer to the PTP HW struct
*/
static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)
{
ptp->phy_model = ICE_PHY_E82X;
ptp->num_lports = 8;
ptp->ports_per_phy = 8;
}
/* E810 functions
*
* The following functions operate on the E810 series devices which use
......@@ -2863,17 +4983,21 @@ static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
}
/**
* ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
* ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
* @hw: pointer to HW struct
*
* Enable the timesync PTP functionality for the external PHY connected to
* this function.
* Perform E810-specific PTP hardware clock initialization steps.
*
* Return: 0 on success, other error codes when failed to initialize TimeSync
*/
int ice_ptp_init_phy_e810(struct ice_hw *hw)
static int ice_ptp_init_phc_e810(struct ice_hw *hw)
{
u8 tmr_idx;
int err;
/* Ensure synchronization delay is zero */
wr32(hw, GLTSYN_SYNC_DLAY, 0);
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
GLTSYN_ENA_TSYN_ENA_M);
......@@ -2884,21 +5008,6 @@ int ice_ptp_init_phy_e810(struct ice_hw *hw)
return err;
}
/**
* ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
* @hw: pointer to HW struct
*
* Perform E810-specific PTP hardware clock initialization steps.
*/
static int ice_ptp_init_phc_e810(struct ice_hw *hw)
{
/* Ensure synchronization delay is zero */
wr32(hw, GLTSYN_SYNC_DLAY, 0);
/* Initialize the PHY */
return ice_ptp_init_phy_e810(hw);
}
/**
* ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
* @hw: Board private structure
......@@ -3020,47 +5129,9 @@ static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
*/
static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
{
u32 cmd_val, val;
int err;
switch (cmd) {
case ICE_PTP_INIT_TIME:
cmd_val = GLTSYN_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
cmd_val = GLTSYN_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
cmd_val = GLTSYN_CMD_ADJ_TIME;
break;
case ICE_PTP_READ_TIME:
cmd_val = GLTSYN_CMD_READ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
break;
case ICE_PTP_NOP:
return 0;
}
/* Read, modify, write */
err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err);
return err;
}
u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
/* Modify necessary bits only and perform write */
val &= ~TS_CMD_MASK_E810;
val |= cmd_val;
err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err);
return err;
}
return 0;
return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val);
}
/**
......@@ -3242,6 +5313,17 @@ int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
}
/**
* ice_ptp_init_phy_e810 - initialize PHY parameters
* @ptp: pointer to the PTP HW struct
*/
static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp)
{
ptp->phy_model = ICE_PHY_E810;
ptp->num_lports = 8;
ptp->ports_per_phy = 4;
}
/* Device agnostic functions
*
* The following functions implement shared behavior common to both E822 and
......@@ -3299,18 +5381,126 @@ void ice_ptp_unlock(struct ice_hw *hw)
}
/**
* ice_ptp_init_phy_model - Initialize hw->phy_model based on device type
* ice_ptp_init_hw - Initialize hw based on device type
* @hw: pointer to the HW structure
*
* Determine the PHY model for the device, and initialize hw->phy_model
* Determine the PHY model for the device, and initialize hw
* for use by other functions.
*/
void ice_ptp_init_phy_model(struct ice_hw *hw)
void ice_ptp_init_hw(struct ice_hw *hw)
{
if (ice_is_e810(hw))
hw->phy_model = ICE_PHY_E810;
struct ice_ptp_hw *ptp = &hw->ptp;
if (ice_is_e822(hw) || ice_is_e823(hw))
ice_ptp_init_phy_e82x(ptp);
else if (ice_is_e810(hw))
ice_ptp_init_phy_e810(ptp);
else if (ice_is_e825c(hw))
ice_ptp_init_phy_e825c(hw);
else
hw->phy_model = ICE_PHY_E82X;
ptp->phy_model = ICE_PHY_UNSUP;
}
/**
* ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
* @hw: pointer to HW struct
* @port: Port to which cmd has to be sent
* @cmd: Command to be sent to the port
*
* Prepare one port for the upcoming timer sync command. Do not use this for
* programming only a single port, instead use ice_ptp_one_port_cmd() to
* ensure non-modified ports get properly initialized to ICE_PTP_NOP.
*
* Return:
* * %0 - success
* %-EBUSY - PHY type not supported
* * %other - failed to write port command
*/
static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd)
{
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_ptp_write_port_cmd_eth56g(hw, port, cmd);
case ICE_PHY_E82X:
return ice_ptp_write_port_cmd_e82x(hw, port, cmd);
default:
return -EOPNOTSUPP;
}
}
/**
* ice_ptp_one_port_cmd - Program one PHY port for a timer command
* @hw: pointer to HW struct
* @configured_port: the port that should execute the command
* @configured_cmd: the command to be executed on the configured port
*
* Prepare one port for executing a timer command, while preparing all other
* ports to ICE_PTP_NOP. This allows executing a command on a single port
* while ensuring all other ports do not execute stale commands.
*
* Return:
* * %0 - success
* * %other - failed to write port command
*/
int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
enum ice_ptp_tmr_cmd configured_cmd)
{
u32 port;
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
/* Program the configured port with the configured command,
* program all other ports with ICE_PTP_NOP.
*/
if (port == configured_port)
err = ice_ptp_write_port_cmd(hw, port, configured_cmd);
else
err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP);
if (err)
return err;
}
return 0;
}
/**
* ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
* @hw: pointer to HW struct
* @cmd: the timer command to setup
*
* Prepare all PHY ports on this device for the requested timer command. For
* some families this can be done in one shot, but for other families each
* port must be configured individually.
*
* Return:
* * %0 - success
* * %other - failed to write port command
*/
static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
{
u32 port;
/* PHY models which can program all ports simultaneously */
switch (hw->ptp.phy_model) {
case ICE_PHY_E810:
return ice_ptp_port_cmd_e810(hw, cmd);
default:
break;
}
/* PHY models which require programming each port separately */
for (port = 0; port < hw->ptp.num_lports; port++) {
int err;
err = ice_ptp_write_port_cmd(hw, port, cmd);
if (err)
return err;
}
return 0;
}
/**
......@@ -3331,17 +5521,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
ice_ptp_src_cmd(hw, cmd);
/* Next, prepare the ports */
switch (hw->phy_model) {
case ICE_PHY_E810:
err = ice_ptp_port_cmd_e810(hw, cmd);
break;
case ICE_PHY_E82X:
err = ice_ptp_port_cmd_e82x(hw, cmd);
break;
default:
err = -EOPNOTSUPP;
}
err = ice_ptp_port_cmd(hw, cmd);
if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
cmd, err);
......@@ -3383,7 +5563,11 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time)
/* PHY timers */
/* Fill Rx and Tx ports and send msg to PHY */
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_ptp_prep_phy_time_eth56g(hw,
(u32)(time & 0xFFFFFFFF));
break;
case ICE_PHY_E810:
err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
break;
......@@ -3425,7 +5609,10 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
break;
case ICE_PHY_E810:
err = ice_ptp_prep_phy_incval_e810(hw, incval);
break;
......@@ -3491,7 +5678,10 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
err = ice_ptp_prep_phy_adj_eth56g(hw, adj);
break;
case ICE_PHY_E810:
err = ice_ptp_prep_phy_adj_e810(hw, adj);
break;
......@@ -3521,7 +5711,9 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
*/
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
{
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp);
case ICE_PHY_E810:
return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
case ICE_PHY_E82X:
......@@ -3549,7 +5741,9 @@ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
*/
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
{
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_clear_ptp_tstamp_eth56g(hw, block, idx);
case ICE_PHY_E810:
return ice_clear_phy_tstamp_e810(hw, block, idx);
case ICE_PHY_E82X:
......@@ -3610,7 +5804,10 @@ static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
*/
void ice_ptp_reset_ts_memory(struct ice_hw *hw)
{
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
ice_ptp_reset_ts_memory_eth56g(hw);
break;
case ICE_PHY_E82X:
ice_ptp_reset_ts_memory_e82x(hw);
break;
......@@ -3636,7 +5833,9 @@ int ice_ptp_init_phc(struct ice_hw *hw)
/* Clear event err indications for auxiliary pins */
(void)rd32(hw, GLTSYN_STAT(src_idx));
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_ptp_init_phc_eth56g(hw);
case ICE_PHY_E810:
return ice_ptp_init_phc_e810(hw);
case ICE_PHY_E82X:
......@@ -3659,7 +5858,10 @@ int ice_ptp_init_phc(struct ice_hw *hw)
*/
int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
{
switch (hw->phy_model) {
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
tstamp_ready);
case ICE_PHY_E810:
return ice_get_phy_tx_tstamp_ready_e810(hw, block,
tstamp_ready);
......
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View file @ fc5570e0
......@@ -41,6 +41,41 @@ enum ice_ptp_fec_mode {
ICE_PTP_FEC_MODE_RS_FEC
};
enum eth56g_res_type {
ETH56G_PHY_REG_PTP,
ETH56G_PHY_MEM_PTP,
ETH56G_PHY_REG_XPCS,
ETH56G_PHY_REG_MAC,
ETH56G_PHY_REG_GPCS,
NUM_ETH56G_PHY_RES
};
enum ice_eth56g_link_spd {
ICE_ETH56G_LNK_SPD_1G,
ICE_ETH56G_LNK_SPD_2_5G,
ICE_ETH56G_LNK_SPD_10G,
ICE_ETH56G_LNK_SPD_25G,
ICE_ETH56G_LNK_SPD_40G,
ICE_ETH56G_LNK_SPD_50G,
ICE_ETH56G_LNK_SPD_50G2,
ICE_ETH56G_LNK_SPD_100G,
ICE_ETH56G_LNK_SPD_100G2,
NUM_ICE_ETH56G_LNK_SPD /* Must be last */
};
/**
* struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
* @base: base address for each PHY block
* @step: step between PHY lanes
*
* Characteristic information for the various PHY register parameters in the
* ETH56G devices
*/
struct ice_phy_reg_info_eth56g {
u32 base[NUM_ETH56G_PHY_RES];
u32 step;
};
/**
* struct ice_time_ref_info_e82x
* @pll_freq: Frequency of PLL that drives timer ticks in Hz
......@@ -94,8 +129,75 @@ struct ice_vernier_info_e82x {
u32 rx_fixed_delay;
};
#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)
#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
#define ICE_ETH56G_MAC_CFG_FRAC_W 9
/**
* struct ice_cgu_pll_params_e82x
* struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
* @tx_mode: Tx timestamp compensation mode
* @tx_mk_dly: Tx timestamp marker start strobe delay
* @tx_cw_dly: Tx timestamp codeword start strobe delay
* @rx_mode: Rx timestamp compensation mode
* @rx_mk_dly: Rx timestamp marker start strobe delay
* @rx_cw_dly: Rx timestamp codeword start strobe delay
* @blks_per_clk: number of blocks transferred per clock cycle
* @blktime: block time, fixed point
* @mktime: marker time, fixed point
* @tx_offset: total Tx offset, fixed point
* @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
*
* All fixed point registers except Rx offset are 23 bit unsigned ints with
* a 9 bit fractional.
* Rx offset is 11 bit unsigned int with a 9 bit fractional.
*/
struct ice_eth56g_mac_reg_cfg {
struct {
u8 def;
u8 rs;
} tx_mode;
u8 tx_mk_dly;
struct {
u8 def;
u8 onestep;
} tx_cw_dly;
struct {
u8 def;
u8 rs;
} rx_mode;
struct {
u8 def;
u8 rs;
} rx_mk_dly;
struct {
u8 def;
u8 rs;
} rx_cw_dly;
u8 blks_per_clk;
u16 blktime;
u16 mktime;
struct {
u32 serdes;
u32 no_fec;
u32 fc;
u32 rs;
u32 sfd;
u32 onestep;
} tx_offset;
struct {
u32 serdes;
u32 no_fec;
u32 fc;
u32 rs;
u32 sfd;
u32 bs_ds;
} rx_offset;
};
extern
const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
/**
* struct ice_cgu_pll_params_e82x - E82X CGU parameters
* @refclk_pre_div: Reference clock pre-divisor
* @feedback_div: Feedback divisor
* @frac_n_div: Fractional divisor
......@@ -185,9 +287,34 @@ struct ice_cgu_pin_desc {
extern const struct
ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
/**
* struct ice_cgu_pll_params_e825c - E825C CGU parameters
* @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
* @tspll_ndivratio: ndiv ratio that goes directly to the pll
* @tspll_fbdiv_intgr: TS PLL integer feedback divide
* @tspll_fbdiv_frac: TS PLL fractional feedback divide
* @ref1588_ck_div: clock divider for tspll ref
*
* Clock Generation Unit parameters used to program the PLL based on the
* selected TIME_REF/TCXO frequency.
*/
struct ice_cgu_pll_params_e825c {
u32 tspll_ck_refclkfreq;
u32 tspll_ndivratio;
u32 tspll_fbdiv_intgr;
u32 tspll_fbdiv_frac;
u32 ref1588_ck_div;
};
extern const struct
ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];
#define E810C_QSFP_C827_0_HANDLE 2
#define E810C_QSFP_C827_1_HANDLE 3
/* Table of constants related to possible ETH56G PHY resources */
extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
/* Table of constants related to possible TIME_REF sources */
extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];
......@@ -197,7 +324,9 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
*/
#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
#define ICE_E810_PLL_FREQ 812500000
#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
#define E810_OUT_PROP_DELAY_NS 1
/* Device agnostic functions */
u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
......@@ -208,11 +337,15 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time);
int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
void ice_ptp_reset_ts_memory(struct ice_hw *hw);
int ice_ptp_init_phc(struct ice_hw *hw);
void ice_ptp_init_hw(struct ice_hw *hw);
int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
enum ice_ptp_tmr_cmd configured_cmd);
/* E822 family functions */
int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
......@@ -264,9 +397,9 @@ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
/* E810 family functions */
int ice_ptp_init_phy_e810(struct ice_hw *hw);
int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
......@@ -280,11 +413,44 @@ int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
enum dpll_lock_status *dpll_state);
int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
void ice_ptp_init_phy_model(struct ice_hw *hw);
int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
unsigned long *caps);
/* ETH56G family functions */
int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
#define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
#define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
#define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
#define ICE_ETH56G_NOMINAL_THRESH4 0x7777
#define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
/**
* ice_get_base_incval - Get base clock increment value
* @hw: pointer to the HW struct
*
* Return: base clock increment value for supported PHYs, 0 otherwise
*/
static inline u64 ice_get_base_incval(struct ice_hw *hw)
{
switch (hw->ptp.phy_model) {
case ICE_PHY_ETH56G:
return ICE_ETH56G_NOMINAL_INCVAL;
case ICE_PHY_E810:
return ICE_PTP_NOMINAL_INCVAL_E810;
case ICE_PHY_E82X:
return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
default:
return 0;
}
}
#define PFTSYN_SEM_BYTES 4
#define ICE_PTP_CLOCK_INDEX_0 0x00
......@@ -312,6 +478,7 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
#define TS_CMD_MASK_E810 0xFF
#define TS_CMD_MASK 0xF
#define SYNC_EXEC_CMD 0x3
#define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
/* Macros to derive port low and high addresses on both quads */
#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
......@@ -344,11 +511,8 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
#define Q_REG_TX_MEM_GBL_CFG 0xC08
#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
/* Tx Timestamp data registers */
......@@ -380,7 +544,7 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
#define P_REG_TIMETUS_L 0x410
#define P_REG_TIMETUS_U 0x414
#define P_REG_40B_LOW_M 0xFF
#define P_REG_40B_LOW_M GENMASK(7, 0)
#define P_REG_40B_HIGH_S 8
/* PHY window length registers */
......@@ -487,7 +651,7 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
/* E810 timer command register */
#define ETH_GLTSYN_CMD 0x03000344
#define E810_ETH_GLTSYN_CMD 0x03000344
/* Source timer incval macros */
#define INCVAL_HIGH_M 0xFF
......@@ -549,4 +713,115 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
/* E810T PCA9575 IO controller pin control */
#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
/* ETH56G PHY register addresses */
/* Timestamp PHY incval registers */
#define PHY_REG_TIMETUS_L 0x8
#define PHY_REG_TIMETUS_U 0xC
/* Timestamp PCS registers */
#define PHY_PCS_REF_TUS_L 0x18
#define PHY_PCS_REF_TUS_U 0x1C
/* Timestamp PCS ref incval registers */
#define PHY_PCS_REF_INC_L 0x20
#define PHY_PCS_REF_INC_U 0x24
/* Timestamp init registers */
#define PHY_REG_RX_TIMER_INC_PRE_L 0x64
#define PHY_REG_RX_TIMER_INC_PRE_U 0x68
#define PHY_REG_TX_TIMER_INC_PRE_L 0x44
#define PHY_REG_TX_TIMER_INC_PRE_U 0x48
/* Timestamp match and adjust target registers */
#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
/* Timestamp command registers */
#define PHY_REG_TX_TMR_CMD 0x40
#define PHY_REG_RX_TMR_CMD 0x60
/* Phy offset ready registers */
#define PHY_REG_TX_OFFSET_READY 0x54
#define PHY_REG_RX_OFFSET_READY 0x74
/* Phy total offset registers */
#define PHY_REG_TOTAL_TX_OFFSET_L 0x38
#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
#define PHY_REG_TOTAL_RX_OFFSET_L 0x58
#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
/* Timestamp capture registers */
#define PHY_REG_TX_CAPTURE_L 0x78
#define PHY_REG_TX_CAPTURE_U 0x7C
#define PHY_REG_RX_CAPTURE_L 0x8C
#define PHY_REG_RX_CAPTURE_U 0x90
/* Memory status registers */
#define PHY_REG_TX_MEMORY_STATUS_L 0x80
#define PHY_REG_TX_MEMORY_STATUS_U 0x84
/* Interrupt config register */
#define PHY_REG_TS_INT_CONFIG 0x88
/* XIF mode config register */
#define PHY_MAC_XIF_MODE 0x24
#define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
#define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
#define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
#define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
/* GPCS config register */
#define PHY_GPCS_CONFIG_REG0 0x268
#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
#define PHY_GPCS_BITSLIP 0x5C
#define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
#define PHY_TS_INT_CONFIG_ENA_M BIT(6)
/* 1-step PTP config */
#define PHY_PTP_1STEP_CONFIG 0x270
#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
/* Macros to derive offsets for TimeStampLow and TimeStampHigh */
#define PHY_TSTAMP_L(x) (((x) * 8) + 0)
#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
#define PHY_REG_REVISION 0x85000
#define PHY_REG_DESKEW_0 0x94
#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
#define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)
#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
#define PHY_REG_GPCS_BITSLIP 0x5C
#define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
#define PHY_REVISION_ETH56G 0x10200
#define PHY_VENDOR_TXLANE_THRESH 0x2000C
#define PHY_MAC_TSU_CONFIG 0x40
#define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
#define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
#define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
#define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
#define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
#define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
#define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
#define PHY_MAC_RX_MODULO 0x44
#define PHY_MAC_RX_OFFSET 0x48
#define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
#define PHY_MAC_TX_MODULO 0x4C
#define PHY_MAC_BLOCKTIME 0x50
#define PHY_MAC_MARKERTIME 0x54
#define PHY_MAC_TX_OFFSET 0x58
#define PHY_PTP_INT_STATUS 0x7FD140
#endif /* _ICE_PTP_HW_H_ */
drivers/net/ethernet/intel/ice/ice_sbq_cmd.h
View file @ fc5570e0
......@@ -47,10 +47,12 @@ struct ice_sbq_evt_desc {
};
enum ice_sbq_msg_dev {
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
cgu = 0x06
eth56g_phy_0 = 0x02,
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
cgu = 0x06,
eth56g_phy_1 = 0x0D,
};
enum ice_sbq_msg_opcode {
......
drivers/net/ethernet/intel/ice/ice_type.h
View file @ fc5570e0
......@@ -322,12 +322,14 @@ enum ice_time_ref_freq {
ICE_TIME_REF_FREQ_156_250 = 4,
ICE_TIME_REF_FREQ_245_760 = 5,
NUM_ICE_TIME_REF_FREQ
NUM_ICE_TIME_REF_FREQ,
ICE_TIME_REF_FREQ_INVALID = -1,
};
/* Clock source specification */
enum ice_clk_src {
ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
ICE_CLK_SRC_TCXO = 0, /* Temperature compensated oscillator */
ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
NUM_ICE_CLK_SRC
......@@ -372,6 +374,15 @@ struct ice_ts_dev_info {
u8 ts_ll_int_read;
};
#define ICE_NAC_TOPO_PRIMARY_M BIT(0)
#define ICE_NAC_TOPO_DUAL_M BIT(1)
#define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)
struct ice_nac_topology {
u32 mode;
u8 id;
};
/* Function specific capabilities */
struct ice_hw_func_caps {
struct ice_hw_common_caps common_cap;
......@@ -393,6 +404,7 @@ struct ice_hw_dev_caps {
u32 num_flow_director_fltr; /* Number of FD filters available */
struct ice_ts_dev_info ts_dev_info;
u32 num_funcs;
struct ice_nac_topology nac_topo;
/* bitmap of supported sensors
* bit 0 - internal temperature sensor
* bit 31:1 - Reserved
......@@ -818,11 +830,43 @@ struct ice_mbx_data {
u16 async_watermark_val;
};
#define ICE_PORTS_PER_QUAD 4
#define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
struct ice_eth56g_params {
u8 num_phys;
u8 phy_addr[2];
bool onestep_ena;
bool sfd_ena;
u32 peer_delay;
};
union ice_phy_params {
struct ice_eth56g_params eth56g;
};
/* PHY model */
enum ice_phy_model {
ICE_PHY_UNSUP = -1,
ICE_PHY_E810 = 1,
ICE_PHY_E810 = 1,
ICE_PHY_E82X,
ICE_PHY_ETH56G,
};
/* Global Link Topology */
enum ice_global_link_topo {
ICE_LINK_TOPO_UP_TO_2_LINKS,
ICE_LINK_TOPO_UP_TO_4_LINKS,
ICE_LINK_TOPO_UP_TO_8_LINKS,
ICE_LINK_TOPO_RESERVED,
};
struct ice_ptp_hw {
enum ice_phy_model phy_model;
union ice_phy_params phy;
u8 num_lports;
u8 ports_per_phy;
bool is_2x50g_muxed_topo;
};
/* Port hardware description */
......@@ -846,7 +890,6 @@ struct ice_hw {
u8 revision_id;
u8 pf_id; /* device profile info */
enum ice_phy_model phy_model;
u16 max_burst_size; /* driver sets this value */
......@@ -909,12 +952,7 @@ struct ice_hw {
/* INTRL granularity in 1 us */
u8 intrl_gran;
#define ICE_MAX_QUAD 2
#define ICE_QUADS_PER_PHY_E82X 2
#define ICE_PORTS_PER_PHY_E82X 8
#define ICE_PORTS_PER_QUAD 4
#define ICE_PORTS_PER_PHY_E810 4
#define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
struct ice_ptp_hw ptp;
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
......
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