Commit fd360e20 authored by Jon Hunter's avatar Jon Hunter Committed by Thierry Reding

clk: tegra: Fix sparse warnings for functions not declared as static

Sparse reports the following warnings for functions in clk-tegra210.c
that should be declared as static:

drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol
 'tegra210_pllcx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol
 '_pllc_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol
 '_pllc2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol
 '_pllc3_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol
 '_plla1_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol
 'tegra210_plla_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol
 'tegra210_plld_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol
 'tegra210_plld2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol
 'tegra210_plldp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol
 'tegra210_pllc4_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol
 'tegra210_pllre_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol
 'tegra210_pllx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol
 'tegra210_pllmb_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol
 'tegra210_pllp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol
 'tegra210_pllu_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol
 'tegra210_clk_adjust_vco_min' was not declared. Should it be static?

Fix this by declaring the above as static.
Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d9e65791
...@@ -458,7 +458,8 @@ static void pllcx_check_defaults(struct tegra_clk_pll_params *params) ...@@ -458,7 +458,8 @@ static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
PLLCX_MISC3_WRITE_MASK); PLLCX_MISC3_WRITE_MASK);
} }
void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx) static void tegra210_pllcx_set_defaults(const char *name,
struct tegra_clk_pll *pllcx)
{ {
pllcx->params->defaults_set = true; pllcx->params->defaults_set = true;
...@@ -483,22 +484,22 @@ void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx) ...@@ -483,22 +484,22 @@ void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
udelay(1); udelay(1);
} }
void _pllc_set_defaults(struct tegra_clk_pll *pllcx) static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
{ {
tegra210_pllcx_set_defaults("PLL_C", pllcx); tegra210_pllcx_set_defaults("PLL_C", pllcx);
} }
void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
{ {
tegra210_pllcx_set_defaults("PLL_C2", pllcx); tegra210_pllcx_set_defaults("PLL_C2", pllcx);
} }
void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
{ {
tegra210_pllcx_set_defaults("PLL_C3", pllcx); tegra210_pllcx_set_defaults("PLL_C3", pllcx);
} }
void _plla1_set_defaults(struct tegra_clk_pll *pllcx) static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
{ {
tegra210_pllcx_set_defaults("PLL_A1", pllcx); tegra210_pllcx_set_defaults("PLL_A1", pllcx);
} }
...@@ -508,7 +509,7 @@ void _plla1_set_defaults(struct tegra_clk_pll *pllcx) ...@@ -508,7 +509,7 @@ void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
* PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
* Fractional SDM is allowed to provide exact audio rates. * Fractional SDM is allowed to provide exact audio rates.
*/ */
void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
{ {
u32 mask; u32 mask;
u32 val = readl_relaxed(clk_base + plla->params->base_reg); u32 val = readl_relaxed(clk_base + plla->params->base_reg);
...@@ -560,7 +561,7 @@ void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) ...@@ -560,7 +561,7 @@ void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
* PLLD * PLLD
* PLL with fractional SDM. * PLL with fractional SDM.
*/ */
void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
{ {
u32 val; u32 val;
u32 mask = 0xffff; u32 mask = 0xffff;
...@@ -699,7 +700,7 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, ...@@ -699,7 +700,7 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
udelay(1); udelay(1);
} }
void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
{ {
plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
PLLD2_MISC1_CFG_DEFAULT_VALUE, PLLD2_MISC1_CFG_DEFAULT_VALUE,
...@@ -707,7 +708,7 @@ void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) ...@@ -707,7 +708,7 @@ void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
PLLD2_MISC3_CTRL2_DEFAULT_VALUE); PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
} }
void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
{ {
plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
PLLDP_MISC1_CFG_DEFAULT_VALUE, PLLDP_MISC1_CFG_DEFAULT_VALUE,
...@@ -720,7 +721,7 @@ void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) ...@@ -720,7 +721,7 @@ void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
* Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
* VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
*/ */
void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
{ {
plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
} }
...@@ -729,7 +730,7 @@ void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) ...@@ -729,7 +730,7 @@ void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
* PLLRE * PLLRE
* VCO is exposed to the clock tree directly along with post-divider output * VCO is exposed to the clock tree directly along with post-divider output
*/ */
void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
{ {
u32 mask; u32 mask;
u32 val = readl_relaxed(clk_base + pllre->params->base_reg); u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
...@@ -842,7 +843,7 @@ static void pllx_check_defaults(struct tegra_clk_pll *pll) ...@@ -842,7 +843,7 @@ static void pllx_check_defaults(struct tegra_clk_pll *pll)
PLLX_MISC5_WRITE_MASK); PLLX_MISC5_WRITE_MASK);
} }
void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
{ {
u32 val; u32 val;
u32 step_a, step_b; u32 step_a, step_b;
...@@ -902,7 +903,7 @@ void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) ...@@ -902,7 +903,7 @@ void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
} }
/* PLLMB */ /* PLLMB */
void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
{ {
u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
...@@ -961,7 +962,7 @@ static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) ...@@ -961,7 +962,7 @@ static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
~mask & PLLP_MISC1_WRITE_MASK); ~mask & PLLP_MISC1_WRITE_MASK);
} }
void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
{ {
u32 mask; u32 mask;
u32 val = readl_relaxed(clk_base + pllp->params->base_reg); u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
...@@ -1023,7 +1024,7 @@ static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control) ...@@ -1023,7 +1024,7 @@ static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control)
~mask & PLLU_MISC1_WRITE_MASK); ~mask & PLLU_MISC1_WRITE_MASK);
} }
void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
{ {
u32 val = readl_relaxed(clk_base + pllu->params->base_reg); u32 val = readl_relaxed(clk_base + pllu->params->base_reg);
...@@ -1213,7 +1214,8 @@ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) ...@@ -1213,7 +1214,8 @@ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
cfg->m *= PLL_SDM_COEFF; cfg->m *= PLL_SDM_COEFF;
} }
unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, static unsigned long
tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
unsigned long parent_rate) unsigned long parent_rate)
{ {
unsigned long vco_min = params->vco_min; unsigned long vco_min = params->vco_min;
......
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