Commit fd6b8f43 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Make IS_IVYBRIDGE only take dev_priv

Saves 848 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)
v3: Rebase.
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 50a0bc90
...@@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv) ...@@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv)
fmt, ##__VA_ARGS__) fmt, ##__VA_ARGS__)
static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
{ {
enum intel_pch ret = PCH_NOP; enum intel_pch ret = PCH_NOP;
...@@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) ...@@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
* make an educated guess as to which PCH is really there. * make an educated guess as to which PCH is really there.
*/ */
if (IS_GEN5(dev)) { if (IS_GEN5(dev_priv)) {
ret = PCH_IBX; ret = PCH_IBX;
DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
ret = PCH_CPT; ret = PCH_CPT;
DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ret = PCH_LPT; ret = PCH_LPT;
DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
ret = PCH_SPT; ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
} }
...@@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev) ...@@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT; dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n"); DRM_DEBUG_KMS("Found CougarPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); WARN_ON(!(IS_GEN6(dev_priv) ||
IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */ /* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT; dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n"); DRM_DEBUG_KMS("Found PantherPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); WARN_ON(!(IS_GEN6(dev_priv) ||
IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT; dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n"); DRM_DEBUG_KMS("Found LynxPoint PCH\n");
...@@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev) ...@@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET && PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device == pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) { PCI_SUBDEVICE_ID_QEMU)) {
dev_priv->pch_type = intel_virt_detect_pch(dev); dev_priv->pch_type =
intel_virt_detect_pch(dev_priv);
} else } else
continue; continue;
......
...@@ -2651,7 +2651,7 @@ struct drm_i915_cmd_table { ...@@ -2651,7 +2651,7 @@ struct drm_i915_cmd_table {
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
INTEL_DEVID(dev_priv) == 0x0152 || \ INTEL_DEVID(dev_priv) == 0x0152 || \
INTEL_DEVID(dev_priv) == 0x015a) INTEL_DEVID(dev_priv) == 0x015a)
......
...@@ -4432,7 +4432,7 @@ i915_gem_init_hw(struct drm_device *dev) ...@@ -4432,7 +4432,7 @@ i915_gem_init_hw(struct drm_device *dev)
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
if (HAS_PCH_NOP(dev_priv)) { if (HAS_PCH_NOP(dev_priv)) {
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(dev_priv)) {
u32 temp = I915_READ(GEN7_MSG_CTL); u32 temp = I915_READ(GEN7_MSG_CTL);
temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
I915_WRITE(GEN7_MSG_CTL, temp); I915_WRITE(GEN7_MSG_CTL, temp);
......
...@@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) ...@@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
* This is only applicable for Ivy Bridge devices since * This is only applicable for Ivy Bridge devices since
* later platforms don't have L3 control bits in the PTE. * later platforms don't have L3 control bits in the PTE.
*/ */
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(to_i915(dev))) {
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
/* Failure shouldn't ever happen this early */ /* Failure shouldn't ever happen this early */
if (WARN_ON(ret)) { if (WARN_ON(ret)) {
......
...@@ -3727,7 +3727,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) ...@@ -3727,7 +3727,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */ /* enable normal train */
reg = FDI_TX_CTL(pipe); reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg); temp = I915_READ(reg);
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp &= ~FDI_LINK_TRAIN_NONE_IVB;
temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
} else { } else {
...@@ -3752,7 +3752,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) ...@@ -3752,7 +3752,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
udelay(1000); udelay(1000);
/* IVB wants error correction enabled */ /* IVB wants error correction enabled */
if (IS_IVYBRIDGE(dev)) if (IS_IVYBRIDGE(dev_priv))
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
FDI_FE_ERRC_ENABLE); FDI_FE_ERRC_ENABLE);
} }
...@@ -4538,7 +4538,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) ...@@ -4538,7 +4538,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
assert_pch_transcoder_disabled(dev_priv, pipe); assert_pch_transcoder_disabled(dev_priv, pipe);
if (IS_IVYBRIDGE(dev)) if (IS_IVYBRIDGE(dev_priv))
ivybridge_update_fdi_bc_bifurcation(intel_crtc); ivybridge_update_fdi_bc_bifurcation(intel_crtc);
/* Write the TU size bits before fdi link training, so that error /* Write the TU size bits before fdi link training, so that error
...@@ -4852,7 +4852,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) ...@@ -4852,7 +4852,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
* as some pre-programmed values are broken, * as some pre-programmed values are broken,
* e.g. x201. * e.g. x201.
*/ */
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
PF_PIPE_SEL_IVB(pipe)); PF_PIPE_SEL_IVB(pipe));
else else
...@@ -12249,7 +12249,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, ...@@ -12249,7 +12249,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (fb->modifier[0] != old_fb->modifier[0]) if (fb->modifier[0] != old_fb->modifier[0])
/* vlv: DISPLAY_FLIP fails to change tiling */ /* vlv: DISPLAY_FLIP fails to change tiling */
engine = NULL; engine = NULL;
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
engine = dev_priv->engine[BCS]; engine = dev_priv->engine[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) { } else if (INTEL_INFO(dev)->gen >= 7) {
engine = i915_gem_active_get_engine(&obj->last_write, engine = i915_gem_active_get_engine(&obj->last_write,
...@@ -12525,7 +12525,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, ...@@ -12525,7 +12525,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
* cstate->update_wm was already set above, so this flag will * cstate->update_wm was already set above, so this flag will
* take effect when we commit and program watermarks. * take effect when we commit and program watermarks.
*/ */
if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
needs_scaling(to_intel_plane_state(plane_state)) && needs_scaling(to_intel_plane_state(plane_state)) &&
!needs_scaling(old_plane_state)) !needs_scaling(old_plane_state))
pipe_config->disable_lp_wm = true; pipe_config->disable_lp_wm = true;
......
...@@ -2191,14 +2191,15 @@ static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) ...@@ -2191,14 +2191,15 @@ static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
wm[0] = 13; wm[0] = 13;
} }
static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
uint16_t wm[5])
{ {
/* ILK cursor LP0 latency is 1300 ns */ /* ILK cursor LP0 latency is 1300 ns */
if (IS_GEN5(dev)) if (IS_GEN5(dev_priv))
wm[0] = 13; wm[0] = 13;
/* WaDoubleCursorLP3Latency:ivb */ /* WaDoubleCursorLP3Latency:ivb */
if (IS_IVYBRIDGE(dev)) if (IS_IVYBRIDGE(dev_priv))
wm[3] *= 2; wm[3] *= 2;
} }
...@@ -2294,7 +2295,7 @@ static void ilk_setup_wm_latency(struct drm_device *dev) ...@@ -2294,7 +2295,7 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
sizeof(dev_priv->wm.pri_latency)); sizeof(dev_priv->wm.pri_latency));
intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
...@@ -2522,7 +2523,7 @@ static void ilk_wm_merge(struct drm_device *dev, ...@@ -2522,7 +2523,7 @@ static void ilk_wm_merge(struct drm_device *dev,
int last_enabled_level = max_level; int last_enabled_level = max_level;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
config->num_pipes_active > 1) config->num_pipes_active > 1)
last_enabled_level = 0; last_enabled_level = 0;
...@@ -4625,7 +4626,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) ...@@ -4625,7 +4626,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) if (IS_HASWELL(dev) || IS_BROADWELL(dev))
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
else if (IS_IVYBRIDGE(dev)) else if (IS_IVYBRIDGE(dev_priv))
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
......
...@@ -1084,7 +1084,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) ...@@ -1084,7 +1084,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
case 7: case 7:
case 8: case 8:
if (IS_IVYBRIDGE(dev)) { if (IS_IVYBRIDGE(to_i915(dev))) {
intel_plane->can_scale = true; intel_plane->can_scale = true;
intel_plane->max_downscale = 2; intel_plane->max_downscale = 2;
} else { } else {
......
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