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Commit fd9470ce authored by Russell King's avatar Russell King Committed by Russell King
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Merge branch 'omap2-clock' of... 

Merge branch 'omap2-clock' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git

Merge branch 'omap2-clock' into omap-all
parents b8e6c91c e89087c9
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Showing with 3578 additions and 147 deletions
arch/arm/mach-omap2/Makefile
View file @ fd9470ce
...@@ -4,7 +4,8 @@ ...@@ -4,7 +4,8 @@
# Common support # Common support
obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
clockdomain.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......
arch/arm/mach-omap2/clock.c
View file @ fd9470ce
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/clockdomain.h>
#include <mach/sram.h> #include <mach/sram.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <asm/div64.h> #include <asm/div64.h>
...@@ -62,9 +63,35 @@ ...@@ -62,9 +63,35 @@
u8 cpu_mask; u8 cpu_mask;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
* Omap2 specific clock functions * OMAP2/3 specific clock functions
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/**
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
* @clk: OMAP clock struct ptr to use
*
* Convert a clockdomain name stored in a struct clk 'clk' into a
* clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). No return value.
*/
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
if (!clk->clkdm_name)
return;
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
clk->name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
pr_debug("clock: could not associate clk %s to "
"clkdm %s\n", clk->name, clk->clkdm_name);
}
}
/** /**
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
* @clk: OMAP clock struct ptr to use * @clk: OMAP clock struct ptr to use
...@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk) ...@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk); _omap2_clk_disable(clk);
if (likely((u32)clk->parent)) if (likely((u32)clk->parent))
omap2_clk_disable(clk->parent); omap2_clk_disable(clk->parent);
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
} }
} }
...@@ -324,11 +354,19 @@ int omap2_clk_enable(struct clk *clk) ...@@ -324,11 +354,19 @@ int omap2_clk_enable(struct clk *clk)
return ret; return ret;
} }
if (clk->clkdm)
omap2_clkdm_clk_enable(clk->clkdm, clk);
ret = _omap2_clk_enable(clk); ret = _omap2_clk_enable(clk);
if (unlikely(ret != 0) && clk->parent) { if (unlikely(ret != 0)) {
omap2_clk_disable(clk->parent); if (clk->clkdm)
clk->usecount--; omap2_clkdm_clk_disable(clk->clkdm, clk);
if (clk->parent) {
omap2_clk_disable(clk->parent);
clk->usecount--;
}
} }
} }
......
arch/arm/mach-omap2/clock.h
View file @ fd9470ce
...@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk); ...@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk);
#endif #endif
void omap2_clksel_recalc(struct clk *clk); void omap2_clksel_recalc(struct clk *clk);
void omap2_init_clk_clkdm(struct clk *clk);
void omap2_init_clksel_parent(struct clk *clk); void omap2_init_clksel_parent(struct clk *clk);
u32 omap2_clksel_get_divisor(struct clk *clk); u32 omap2_clksel_get_divisor(struct clk *clk);
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
......
arch/arm/mach-omap2/clock24xx.h
View file @ fd9470ce
...@@ -626,6 +626,7 @@ static struct clk func_32k_ck = { ...@@ -626,6 +626,7 @@ static struct clk func_32k_ck = {
.rate = 32000, .rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate, .recalc = &propagate_rate,
}; };
...@@ -634,17 +635,19 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ ...@@ -634,17 +635,19 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck", .name = "osc_ck",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES, RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.enable = &omap2_enable_osc_ck, .enable = &omap2_enable_osc_ck,
.disable = &omap2_disable_osc_ck, .disable = &omap2_disable_osc_ck,
.recalc = &omap2_osc_clk_recalc, .recalc = &omap2_osc_clk_recalc,
}; };
/* With out modem likely 12MHz, with modem likely 13MHz */ /* Without modem likely 12MHz, with modem likely 13MHz */
static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.name = "sys_ck", /* ~ ref_clk also */ .name = "sys_ck", /* ~ ref_clk also */
.parent = &osc_ck, .parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES, ALWAYS_ENABLED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_sys_clk_recalc, .recalc = &omap2_sys_clk_recalc,
}; };
...@@ -653,6 +656,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ ...@@ -653,6 +656,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.rate = 54000000, .rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate, .recalc = &propagate_rate,
}; };
...@@ -684,6 +688,7 @@ static struct clk dpll_ck = { ...@@ -684,6 +688,7 @@ static struct clk dpll_ck = {
.dpll_data = &dpll_dd, .dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED, RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_dpllcore_recalc, .recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore, .set_rate = &omap2_reprogram_dpllcore,
}; };
...@@ -694,6 +699,7 @@ static struct clk apll96_ck = { ...@@ -694,6 +699,7 @@ static struct clk apll96_ck = {
.rate = 96000000, .rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable, .enable = &omap2_clk_fixed_enable,
...@@ -707,6 +713,7 @@ static struct clk apll54_ck = { ...@@ -707,6 +713,7 @@ static struct clk apll54_ck = {
.rate = 54000000, .rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable, .enable = &omap2_clk_fixed_enable,
...@@ -741,6 +748,7 @@ static struct clk func_54m_ck = { ...@@ -741,6 +748,7 @@ static struct clk func_54m_ck = {
.parent = &apll54_ck, /* can also be alt_clk */ .parent = &apll54_ck, /* can also be alt_clk */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_54M_SOURCE, .clksel_mask = OMAP24XX_54M_SOURCE,
...@@ -753,6 +761,7 @@ static struct clk core_ck = { ...@@ -753,6 +761,7 @@ static struct clk core_ck = {
.parent = &dpll_ck, /* can also be 32k */ .parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES, ALWAYS_ENABLED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -779,6 +788,7 @@ static struct clk func_96m_ck = { ...@@ -779,6 +788,7 @@ static struct clk func_96m_ck = {
.parent = &apll96_ck, .parent = &apll96_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP2430_96M_SOURCE, .clksel_mask = OMAP2430_96M_SOURCE,
...@@ -811,6 +821,7 @@ static struct clk func_48m_ck = { ...@@ -811,6 +821,7 @@ static struct clk func_48m_ck = {
.parent = &apll96_ck, /* 96M or Alt */ .parent = &apll96_ck, /* 96M or Alt */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_48M_SOURCE, .clksel_mask = OMAP24XX_48M_SOURCE,
...@@ -826,6 +837,7 @@ static struct clk func_12m_ck = { ...@@ -826,6 +837,7 @@ static struct clk func_12m_ck = {
.fixed_div = 4, .fixed_div = 4,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_fixed_divisor_recalc, .recalc = &omap2_fixed_divisor_recalc,
}; };
...@@ -878,6 +890,7 @@ static struct clk sys_clkout_src = { ...@@ -878,6 +890,7 @@ static struct clk sys_clkout_src = {
.parent = &func_54m_ck, .parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES, RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -908,6 +921,7 @@ static struct clk sys_clkout = { ...@@ -908,6 +921,7 @@ static struct clk sys_clkout = {
.parent = &sys_clkout_src, .parent = &sys_clkout_src,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel, .clksel = sys_clkout_clksel,
...@@ -921,6 +935,7 @@ static struct clk sys_clkout2_src = { ...@@ -921,6 +935,7 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src", .name = "sys_clkout2_src",
.parent = &func_54m_ck, .parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -942,6 +957,7 @@ static struct clk sys_clkout2 = { ...@@ -942,6 +957,7 @@ static struct clk sys_clkout2 = {
.name = "sys_clkout2", .name = "sys_clkout2",
.parent = &sys_clkout2_src, .parent = &sys_clkout2_src,
.flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
.clkdm_name = "wkup_clkdm",
.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel, .clksel = sys_clkout2_clksel,
...@@ -954,6 +970,7 @@ static struct clk emul_ck = { ...@@ -954,6 +970,7 @@ static struct clk emul_ck = {
.name = "emul_ck", .name = "emul_ck",
.parent = &func_54m_ck, .parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT, .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -990,12 +1007,13 @@ static struct clk mpu_ck = { /* Control cpu */ ...@@ -990,12 +1007,13 @@ static struct clk mpu_ck = { /* Control cpu */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES, CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "mpu_clkdm",
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
.clksel = mpu_clksel, .clksel = mpu_clksel,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate, .round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate .set_rate = &omap2_clksel_set_rate
}; };
...@@ -1031,6 +1049,7 @@ static struct clk dsp_fck = { ...@@ -1031,6 +1049,7 @@ static struct clk dsp_fck = {
.parent = &core_ck, .parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES, CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "dsp_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
...@@ -1054,10 +1073,7 @@ static const struct clksel dsp_irate_ick_clksel[] = { ...@@ -1054,10 +1073,7 @@ static const struct clksel dsp_irate_ick_clksel[] = {
{ .parent = NULL } { .parent = NULL }
}; };
/* /* This clock does not exist as such in the TRM. */
* This clock does not exist as such in the TRM, but is added to
* separate source selection from XXX
*/
static struct clk dsp_irate_ick = { static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick", .name = "dsp_irate_ick",
.parent = &dsp_fck, .parent = &dsp_fck,
...@@ -1089,11 +1105,17 @@ static struct clk iva2_1_ick = { ...@@ -1089,11 +1105,17 @@ static struct clk iva2_1_ick = {
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
}; };
/*
* The IVA1 is an ARM7 core on the 2420 that has nothing to do with
* the C54x, but which is contained in the DSP powerdomain. Does not
* exist on later OMAPs.
*/
static struct clk iva1_ifck = { static struct clk iva1_ifck = {
.name = "iva1_ifck", .name = "iva1_ifck",
.parent = &core_ck, .parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
RATE_PROPAGATES | DELAYED_APP, RATE_PROPAGATES | DELAYED_APP,
.clkdm_name = "iva1_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_COP_SHIFT, .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
...@@ -1109,6 +1131,7 @@ static struct clk iva1_mpu_int_ifck = { ...@@ -1109,6 +1131,7 @@ static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck", .name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck, .parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "iva1_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
.fixed_div = 2, .fixed_div = 2,
...@@ -1156,6 +1179,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ ...@@ -1156,6 +1179,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES, CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "core_l3_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
.clksel = core_l3_clksel, .clksel = core_l3_clksel,
...@@ -1177,11 +1201,13 @@ static const struct clksel usb_l4_ick_clksel[] = { ...@@ -1177,11 +1201,13 @@ static const struct clksel usb_l4_ick_clksel[] = {
{ .parent = NULL }, { .parent = NULL },
}; };
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick", .name = "usb_l4_ick",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP | CONFIG_PARTICIPANT, DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_USB_SHIFT, .enable_bit = OMAP24XX_EN_USB_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
...@@ -1192,11 +1218,43 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ ...@@ -1192,11 +1218,43 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.set_rate = &omap2_clksel_set_rate .set_rate = &omap2_clksel_set_rate
}; };
/*
* L4 clock management domain
*
* This domain contains lots of interface clocks from the L4 interface, some
* functional clocks. Fixed APLL functional source clocks are managed in
* this domain.
*/
static const struct clksel_rate l4_core_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 }
};
static const struct clksel l4_clksel[] = {
{ .parent = &core_l3_ck, .rates = l4_core_l3_rates },
{ .parent = NULL }
};
static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
.clksel = l4_clksel,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate
};
/* /*
* SSI is in L3 management domain, its direct parent is core not l3, * SSI is in L3 management domain, its direct parent is core not l3,
* many core power domain entities are grouped into the L3 clock * many core power domain entities are grouped into the L3 clock
* domain. * domain.
* SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
* *
* ssr = core/1/2/3/4/5, sst = 1/2 ssr. * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
*/ */
...@@ -1221,6 +1279,7 @@ static struct clk ssi_ssr_sst_fck = { ...@@ -1221,6 +1279,7 @@ static struct clk ssi_ssr_sst_fck = {
.parent = &core_ck, .parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP, DELAYED_APP,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_SSI_SHIFT, .enable_bit = OMAP24XX_EN_SSI_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
...@@ -1231,6 +1290,7 @@ static struct clk ssi_ssr_sst_fck = { ...@@ -1231,6 +1290,7 @@ static struct clk ssi_ssr_sst_fck = {
.set_rate = &omap2_clksel_set_rate .set_rate = &omap2_clksel_set_rate
}; };
/* /*
* GFX clock domain * GFX clock domain
* Clocks: * Clocks:
...@@ -1254,6 +1314,7 @@ static struct clk gfx_3d_fck = { ...@@ -1254,6 +1314,7 @@ static struct clk gfx_3d_fck = {
.name = "gfx_3d_fck", .name = "gfx_3d_fck",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_3D_SHIFT, .enable_bit = OMAP24XX_EN_3D_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
...@@ -1268,6 +1329,7 @@ static struct clk gfx_2d_fck = { ...@@ -1268,6 +1329,7 @@ static struct clk gfx_2d_fck = {
.name = "gfx_2d_fck", .name = "gfx_2d_fck",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_2D_SHIFT, .enable_bit = OMAP24XX_EN_2D_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
...@@ -1282,6 +1344,7 @@ static struct clk gfx_ick = { ...@@ -1282,6 +1344,7 @@ static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */ .name = "gfx_ick", /* From l3 */
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "gfx_clkdm",
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT, .enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1311,6 +1374,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ ...@@ -1311,6 +1374,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick", .name = "mdm_ick",
.parent = &core_ck, .parent = &core_ck,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
...@@ -1325,51 +1389,12 @@ static struct clk mdm_osc_ck = { ...@@ -1325,51 +1389,12 @@ static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck", .name = "mdm_osc_ck",
.parent = &osc_ck, .parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
.enable_bit = OMAP2430_EN_OSC_SHIFT, .enable_bit = OMAP2430_EN_OSC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
/*
* L4 clock management domain
*
* This domain contains lots of interface clocks from the L4 interface, some
* functional clocks. Fixed APLL functional source clocks are managed in
* this domain.
*/
static const struct clksel_rate l4_core_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 }
};
static const struct clksel l4_clksel[] = {
{ .parent = &core_l3_ck, .rates = l4_core_l3_rates },
{ .parent = NULL }
};
static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
.clksel = l4_clksel,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate
};
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
.recalc = &followparent_recalc,
};
/* /*
* DSS clock domain * DSS clock domain
* CLOCKs: * CLOCKs:
...@@ -1409,6 +1434,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ ...@@ -1409,6 +1434,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick", .name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */ .parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_DSS1_SHIFT, .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1419,6 +1445,7 @@ static struct clk dss1_fck = { ...@@ -1419,6 +1445,7 @@ static struct clk dss1_fck = {
.parent = &core_ck, /* Core or sys */ .parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP, DELAYED_APP,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS1_SHIFT, .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1451,6 +1478,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ ...@@ -1451,6 +1478,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */ .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP, DELAYED_APP,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS2_SHIFT, .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1464,6 +1492,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ ...@@ -1464,6 +1492,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
.name = "dss_54m_fck", /* 54m tv clk */ .name = "dss_54m_fck", /* 54m tv clk */
.parent = &func_54m_ck, .parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_TV_SHIFT, .enable_bit = OMAP24XX_EN_TV_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1491,6 +1520,7 @@ static struct clk gpt1_ick = { ...@@ -1491,6 +1520,7 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick", .name = "gpt1_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT, .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1500,6 +1530,7 @@ static struct clk gpt1_fck = { ...@@ -1500,6 +1530,7 @@ static struct clk gpt1_fck = {
.name = "gpt1_fck", .name = "gpt1_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT, .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1515,6 +1546,7 @@ static struct clk gpt2_ick = { ...@@ -1515,6 +1546,7 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick", .name = "gpt2_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT2_SHIFT, .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1524,6 +1556,7 @@ static struct clk gpt2_fck = { ...@@ -1524,6 +1556,7 @@ static struct clk gpt2_fck = {
.name = "gpt2_fck", .name = "gpt2_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT2_SHIFT, .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1537,6 +1570,7 @@ static struct clk gpt3_ick = { ...@@ -1537,6 +1570,7 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick", .name = "gpt3_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT3_SHIFT, .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1546,6 +1580,7 @@ static struct clk gpt3_fck = { ...@@ -1546,6 +1580,7 @@ static struct clk gpt3_fck = {
.name = "gpt3_fck", .name = "gpt3_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT3_SHIFT, .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1559,6 +1594,7 @@ static struct clk gpt4_ick = { ...@@ -1559,6 +1594,7 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick", .name = "gpt4_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT4_SHIFT, .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1568,6 +1604,7 @@ static struct clk gpt4_fck = { ...@@ -1568,6 +1604,7 @@ static struct clk gpt4_fck = {
.name = "gpt4_fck", .name = "gpt4_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT4_SHIFT, .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1581,6 +1618,7 @@ static struct clk gpt5_ick = { ...@@ -1581,6 +1618,7 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick", .name = "gpt5_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT5_SHIFT, .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1590,6 +1628,7 @@ static struct clk gpt5_fck = { ...@@ -1590,6 +1628,7 @@ static struct clk gpt5_fck = {
.name = "gpt5_fck", .name = "gpt5_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT5_SHIFT, .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1603,6 +1642,7 @@ static struct clk gpt6_ick = { ...@@ -1603,6 +1642,7 @@ static struct clk gpt6_ick = {
.name = "gpt6_ick", .name = "gpt6_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT6_SHIFT, .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1612,6 +1652,7 @@ static struct clk gpt6_fck = { ...@@ -1612,6 +1652,7 @@ static struct clk gpt6_fck = {
.name = "gpt6_fck", .name = "gpt6_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT6_SHIFT, .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1634,6 +1675,7 @@ static struct clk gpt7_fck = { ...@@ -1634,6 +1675,7 @@ static struct clk gpt7_fck = {
.name = "gpt7_fck", .name = "gpt7_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT, .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1647,6 +1689,7 @@ static struct clk gpt8_ick = { ...@@ -1647,6 +1689,7 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick", .name = "gpt8_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT8_SHIFT, .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1656,6 +1699,7 @@ static struct clk gpt8_fck = { ...@@ -1656,6 +1699,7 @@ static struct clk gpt8_fck = {
.name = "gpt8_fck", .name = "gpt8_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT8_SHIFT, .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1669,6 +1713,7 @@ static struct clk gpt9_ick = { ...@@ -1669,6 +1713,7 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick", .name = "gpt9_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT9_SHIFT, .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1678,6 +1723,7 @@ static struct clk gpt9_fck = { ...@@ -1678,6 +1723,7 @@ static struct clk gpt9_fck = {
.name = "gpt9_fck", .name = "gpt9_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT9_SHIFT, .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1691,6 +1737,7 @@ static struct clk gpt10_ick = { ...@@ -1691,6 +1737,7 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick", .name = "gpt10_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT10_SHIFT, .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1700,6 +1747,7 @@ static struct clk gpt10_fck = { ...@@ -1700,6 +1747,7 @@ static struct clk gpt10_fck = {
.name = "gpt10_fck", .name = "gpt10_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT10_SHIFT, .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1713,6 +1761,7 @@ static struct clk gpt11_ick = { ...@@ -1713,6 +1761,7 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick", .name = "gpt11_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT11_SHIFT, .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1722,6 +1771,7 @@ static struct clk gpt11_fck = { ...@@ -1722,6 +1771,7 @@ static struct clk gpt11_fck = {
.name = "gpt11_fck", .name = "gpt11_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT11_SHIFT, .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1735,6 +1785,7 @@ static struct clk gpt12_ick = { ...@@ -1735,6 +1785,7 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick", .name = "gpt12_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT12_SHIFT, .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1744,6 +1795,7 @@ static struct clk gpt12_fck = { ...@@ -1744,6 +1795,7 @@ static struct clk gpt12_fck = {
.name = "gpt12_fck", .name = "gpt12_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT12_SHIFT, .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1758,6 +1810,7 @@ static struct clk mcbsp1_ick = { ...@@ -1758,6 +1810,7 @@ static struct clk mcbsp1_ick = {
.id = 1, .id = 1,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1768,6 +1821,7 @@ static struct clk mcbsp1_fck = { ...@@ -1768,6 +1821,7 @@ static struct clk mcbsp1_fck = {
.id = 1, .id = 1,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1778,6 +1832,7 @@ static struct clk mcbsp2_ick = { ...@@ -1778,6 +1832,7 @@ static struct clk mcbsp2_ick = {
.id = 2, .id = 2,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1788,6 +1843,7 @@ static struct clk mcbsp2_fck = { ...@@ -1788,6 +1843,7 @@ static struct clk mcbsp2_fck = {
.id = 2, .id = 2,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1798,6 +1854,7 @@ static struct clk mcbsp3_ick = { ...@@ -1798,6 +1854,7 @@ static struct clk mcbsp3_ick = {
.id = 3, .id = 3,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1808,6 +1865,7 @@ static struct clk mcbsp3_fck = { ...@@ -1808,6 +1865,7 @@ static struct clk mcbsp3_fck = {
.id = 3, .id = 3,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1818,6 +1876,7 @@ static struct clk mcbsp4_ick = { ...@@ -1818,6 +1876,7 @@ static struct clk mcbsp4_ick = {
.id = 4, .id = 4,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1828,6 +1887,7 @@ static struct clk mcbsp4_fck = { ...@@ -1828,6 +1887,7 @@ static struct clk mcbsp4_fck = {
.id = 4, .id = 4,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1838,6 +1898,7 @@ static struct clk mcbsp5_ick = { ...@@ -1838,6 +1898,7 @@ static struct clk mcbsp5_ick = {
.id = 5, .id = 5,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1848,6 +1909,7 @@ static struct clk mcbsp5_fck = { ...@@ -1848,6 +1909,7 @@ static struct clk mcbsp5_fck = {
.id = 5, .id = 5,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1857,6 +1919,7 @@ static struct clk mcspi1_ick = { ...@@ -1857,6 +1919,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi_ick", .name = "mcspi_ick",
.id = 1, .id = 1,
.parent = &l4_ck, .parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
...@@ -1868,6 +1931,7 @@ static struct clk mcspi1_fck = { ...@@ -1868,6 +1931,7 @@ static struct clk mcspi1_fck = {
.id = 1, .id = 1,
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1878,6 +1942,7 @@ static struct clk mcspi2_ick = { ...@@ -1878,6 +1942,7 @@ static struct clk mcspi2_ick = {
.id = 2, .id = 2,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1888,6 +1953,7 @@ static struct clk mcspi2_fck = { ...@@ -1888,6 +1953,7 @@ static struct clk mcspi2_fck = {
.id = 2, .id = 2,
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1898,6 +1964,7 @@ static struct clk mcspi3_ick = { ...@@ -1898,6 +1964,7 @@ static struct clk mcspi3_ick = {
.id = 3, .id = 3,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1908,6 +1975,7 @@ static struct clk mcspi3_fck = { ...@@ -1908,6 +1975,7 @@ static struct clk mcspi3_fck = {
.id = 3, .id = 3,
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1917,6 +1985,7 @@ static struct clk uart1_ick = { ...@@ -1917,6 +1985,7 @@ static struct clk uart1_ick = {
.name = "uart1_ick", .name = "uart1_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_UART1_SHIFT, .enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1926,6 +1995,7 @@ static struct clk uart1_fck = { ...@@ -1926,6 +1995,7 @@ static struct clk uart1_fck = {
.name = "uart1_fck", .name = "uart1_fck",
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_UART1_SHIFT, .enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1935,6 +2005,7 @@ static struct clk uart2_ick = { ...@@ -1935,6 +2005,7 @@ static struct clk uart2_ick = {
.name = "uart2_ick", .name = "uart2_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_UART2_SHIFT, .enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1944,6 +2015,7 @@ static struct clk uart2_fck = { ...@@ -1944,6 +2015,7 @@ static struct clk uart2_fck = {
.name = "uart2_fck", .name = "uart2_fck",
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_UART2_SHIFT, .enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1953,6 +2025,7 @@ static struct clk uart3_ick = { ...@@ -1953,6 +2025,7 @@ static struct clk uart3_ick = {
.name = "uart3_ick", .name = "uart3_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_UART3_SHIFT, .enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1962,6 +2035,7 @@ static struct clk uart3_fck = { ...@@ -1962,6 +2035,7 @@ static struct clk uart3_fck = {
.name = "uart3_fck", .name = "uart3_fck",
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_UART3_SHIFT, .enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1971,6 +2045,7 @@ static struct clk gpios_ick = { ...@@ -1971,6 +2045,7 @@ static struct clk gpios_ick = {
.name = "gpios_ick", .name = "gpios_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1980,6 +2055,7 @@ static struct clk gpios_fck = { ...@@ -1980,6 +2055,7 @@ static struct clk gpios_fck = {
.name = "gpios_fck", .name = "gpios_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1989,6 +2065,7 @@ static struct clk mpu_wdt_ick = { ...@@ -1989,6 +2065,7 @@ static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick", .name = "mpu_wdt_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -1998,6 +2075,7 @@ static struct clk mpu_wdt_fck = { ...@@ -1998,6 +2075,7 @@ static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck", .name = "mpu_wdt_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2006,31 +2084,40 @@ static struct clk mpu_wdt_fck = { ...@@ -2006,31 +2084,40 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = { static struct clk sync_32k_ick = {
.name = "sync_32k_ick", .name = "sync_32k_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk wdt1_ick = { static struct clk wdt1_ick = {
.name = "wdt1_ick", .name = "wdt1_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT, .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk omapctrl_ick = { static struct clk omapctrl_ick = {
.name = "omapctrl_ick", .name = "omapctrl_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk icr_ick = { static struct clk icr_ick = {
.name = "icr_ick", .name = "icr_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_EN_ICR_SHIFT, .enable_bit = OMAP2430_EN_ICR_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2040,15 +2127,22 @@ static struct clk cam_ick = { ...@@ -2040,15 +2127,22 @@ static struct clk cam_ick = {
.name = "cam_ick", .name = "cam_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_CAM_SHIFT, .enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
/*
* cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
* split into two separate clocks, since the parent clocks are different
* and the clockdomains are also different.
*/
static struct clk cam_fck = { static struct clk cam_fck = {
.name = "cam_fck", .name = "cam_fck",
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_CAM_SHIFT, .enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2058,6 +2152,7 @@ static struct clk mailboxes_ick = { ...@@ -2058,6 +2152,7 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick", .name = "mailboxes_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2067,6 +2162,7 @@ static struct clk wdt4_ick = { ...@@ -2067,6 +2162,7 @@ static struct clk wdt4_ick = {
.name = "wdt4_ick", .name = "wdt4_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_WDT4_SHIFT, .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2076,6 +2172,7 @@ static struct clk wdt4_fck = { ...@@ -2076,6 +2172,7 @@ static struct clk wdt4_fck = {
.name = "wdt4_fck", .name = "wdt4_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_WDT4_SHIFT, .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2085,6 +2182,7 @@ static struct clk wdt3_ick = { ...@@ -2085,6 +2182,7 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick", .name = "wdt3_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_WDT3_SHIFT, .enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2094,6 +2192,7 @@ static struct clk wdt3_fck = { ...@@ -2094,6 +2192,7 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck", .name = "wdt3_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_WDT3_SHIFT, .enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2103,6 +2202,7 @@ static struct clk mspro_ick = { ...@@ -2103,6 +2202,7 @@ static struct clk mspro_ick = {
.name = "mspro_ick", .name = "mspro_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2112,6 +2212,7 @@ static struct clk mspro_fck = { ...@@ -2112,6 +2212,7 @@ static struct clk mspro_fck = {
.name = "mspro_fck", .name = "mspro_fck",
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2121,6 +2222,7 @@ static struct clk mmc_ick = { ...@@ -2121,6 +2222,7 @@ static struct clk mmc_ick = {
.name = "mmc_ick", .name = "mmc_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_MMC_SHIFT, .enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2130,6 +2232,7 @@ static struct clk mmc_fck = { ...@@ -2130,6 +2232,7 @@ static struct clk mmc_fck = {
.name = "mmc_fck", .name = "mmc_fck",
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_MMC_SHIFT, .enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2139,6 +2242,7 @@ static struct clk fac_ick = { ...@@ -2139,6 +2242,7 @@ static struct clk fac_ick = {
.name = "fac_ick", .name = "fac_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_FAC_SHIFT, .enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2148,6 +2252,7 @@ static struct clk fac_fck = { ...@@ -2148,6 +2252,7 @@ static struct clk fac_fck = {
.name = "fac_fck", .name = "fac_fck",
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_FAC_SHIFT, .enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2157,6 +2262,7 @@ static struct clk eac_ick = { ...@@ -2157,6 +2262,7 @@ static struct clk eac_ick = {
.name = "eac_ick", .name = "eac_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_EAC_SHIFT, .enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2166,6 +2272,7 @@ static struct clk eac_fck = { ...@@ -2166,6 +2272,7 @@ static struct clk eac_fck = {
.name = "eac_fck", .name = "eac_fck",
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_EAC_SHIFT, .enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2175,6 +2282,7 @@ static struct clk hdq_ick = { ...@@ -2175,6 +2282,7 @@ static struct clk hdq_ick = {
.name = "hdq_ick", .name = "hdq_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_HDQ_SHIFT, .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2184,6 +2292,7 @@ static struct clk hdq_fck = { ...@@ -2184,6 +2292,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck", .name = "hdq_fck",
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_HDQ_SHIFT, .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2194,6 +2303,7 @@ static struct clk i2c2_ick = { ...@@ -2194,6 +2303,7 @@ static struct clk i2c2_ick = {
.id = 2, .id = 2,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_I2C2_SHIFT, .enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2204,6 +2314,7 @@ static struct clk i2c2_fck = { ...@@ -2204,6 +2314,7 @@ static struct clk i2c2_fck = {
.id = 2, .id = 2,
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_I2C2_SHIFT, .enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2214,6 +2325,7 @@ static struct clk i2chs2_fck = { ...@@ -2214,6 +2325,7 @@ static struct clk i2chs2_fck = {
.id = 2, .id = 2,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_I2CHS2_SHIFT, .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2224,6 +2336,7 @@ static struct clk i2c1_ick = { ...@@ -2224,6 +2336,7 @@ static struct clk i2c1_ick = {
.id = 1, .id = 1,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_I2C1_SHIFT, .enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2234,6 +2347,7 @@ static struct clk i2c1_fck = { ...@@ -2234,6 +2347,7 @@ static struct clk i2c1_fck = {
.id = 1, .id = 1,
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_I2C1_SHIFT, .enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2244,6 +2358,7 @@ static struct clk i2chs1_fck = { ...@@ -2244,6 +2358,7 @@ static struct clk i2chs1_fck = {
.id = 1, .id = 1,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_I2CHS1_SHIFT, .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2252,7 +2367,9 @@ static struct clk i2chs1_fck = { ...@@ -2252,7 +2367,9 @@ static struct clk i2chs1_fck = {
static struct clk gpmc_fck = { static struct clk gpmc_fck = {
.name = "gpmc_fck", .name = "gpmc_fck",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2260,6 +2377,7 @@ static struct clk sdma_fck = { ...@@ -2260,6 +2377,7 @@ static struct clk sdma_fck = {
.name = "sdma_fck", .name = "sdma_fck",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2267,6 +2385,7 @@ static struct clk sdma_ick = { ...@@ -2267,6 +2385,7 @@ static struct clk sdma_ick = {
.name = "sdma_ick", .name = "sdma_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2274,6 +2393,7 @@ static struct clk vlynq_ick = { ...@@ -2274,6 +2393,7 @@ static struct clk vlynq_ick = {
.name = "vlynq_ick", .name = "vlynq_ick",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP242X,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2308,6 +2428,7 @@ static struct clk vlynq_fck = { ...@@ -2308,6 +2428,7 @@ static struct clk vlynq_fck = {
.name = "vlynq_fck", .name = "vlynq_fck",
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP, .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -2323,6 +2444,7 @@ static struct clk sdrc_ick = { ...@@ -2323,6 +2444,7 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick", .name = "sdrc_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP2430_EN_SDRC_SHIFT, .enable_bit = OMAP2430_EN_SDRC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2332,6 +2454,7 @@ static struct clk des_ick = { ...@@ -2332,6 +2454,7 @@ static struct clk des_ick = {
.name = "des_ick", .name = "des_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_DES_SHIFT, .enable_bit = OMAP24XX_EN_DES_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2341,6 +2464,7 @@ static struct clk sha_ick = { ...@@ -2341,6 +2464,7 @@ static struct clk sha_ick = {
.name = "sha_ick", .name = "sha_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_SHA_SHIFT, .enable_bit = OMAP24XX_EN_SHA_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2350,6 +2474,7 @@ static struct clk rng_ick = { ...@@ -2350,6 +2474,7 @@ static struct clk rng_ick = {
.name = "rng_ick", .name = "rng_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_RNG_SHIFT, .enable_bit = OMAP24XX_EN_RNG_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2359,6 +2484,7 @@ static struct clk aes_ick = { ...@@ -2359,6 +2484,7 @@ static struct clk aes_ick = {
.name = "aes_ick", .name = "aes_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_AES_SHIFT, .enable_bit = OMAP24XX_EN_AES_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2368,6 +2494,7 @@ static struct clk pka_ick = { ...@@ -2368,6 +2494,7 @@ static struct clk pka_ick = {
.name = "pka_ick", .name = "pka_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_PKA_SHIFT, .enable_bit = OMAP24XX_EN_PKA_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2377,6 +2504,7 @@ static struct clk usb_fck = { ...@@ -2377,6 +2504,7 @@ static struct clk usb_fck = {
.name = "usb_fck", .name = "usb_fck",
.parent = &func_48m_ck, .parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_USB_SHIFT, .enable_bit = OMAP24XX_EN_USB_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2386,6 +2514,7 @@ static struct clk usbhs_ick = { ...@@ -2386,6 +2514,7 @@ static struct clk usbhs_ick = {
.name = "usbhs_ick", .name = "usbhs_ick",
.parent = &core_l3_ck, .parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_USBHS_SHIFT, .enable_bit = OMAP2430_EN_USBHS_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2396,6 +2525,7 @@ static struct clk mmchs1_ick = { ...@@ -2396,6 +2525,7 @@ static struct clk mmchs1_ick = {
.id = 1, .id = 1,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2406,6 +2536,7 @@ static struct clk mmchs1_fck = { ...@@ -2406,6 +2536,7 @@ static struct clk mmchs1_fck = {
.id = 1, .id = 1,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2416,6 +2547,7 @@ static struct clk mmchs2_ick = { ...@@ -2416,6 +2547,7 @@ static struct clk mmchs2_ick = {
.id = 2, .id = 2,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2435,6 +2567,7 @@ static struct clk gpio5_ick = { ...@@ -2435,6 +2567,7 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick", .name = "gpio5_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_GPIO5_SHIFT, .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2444,6 +2577,7 @@ static struct clk gpio5_fck = { ...@@ -2444,6 +2577,7 @@ static struct clk gpio5_fck = {
.name = "gpio5_fck", .name = "gpio5_fck",
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_GPIO5_SHIFT, .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2453,6 +2587,7 @@ static struct clk mdm_intc_ick = { ...@@ -2453,6 +2587,7 @@ static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick", .name = "mdm_intc_ick",
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2463,6 +2598,7 @@ static struct clk mmchsdb1_fck = { ...@@ -2463,6 +2598,7 @@ static struct clk mmchsdb1_fck = {
.id = 1, .id = 1,
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2473,6 +2609,7 @@ static struct clk mmchsdb2_fck = { ...@@ -2473,6 +2609,7 @@ static struct clk mmchsdb2_fck = {
.id = 2, .id = 2,
.parent = &func_32k_ck, .parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP243X,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -2551,7 +2688,6 @@ static struct clk *onchip_24xx_clks[] __initdata = { ...@@ -2551,7 +2688,6 @@ static struct clk *onchip_24xx_clks[] __initdata = {
&usb_l4_ick, &usb_l4_ick,
/* L4 domain clocks */ /* L4 domain clocks */
&l4_ck, /* used as both core_l4 and wu_l4 */ &l4_ck, /* used as both core_l4 and wu_l4 */
&ssi_l4_ick,
/* virtual meta-group clock */ /* virtual meta-group clock */
&virt_prcm_set, &virt_prcm_set,
/* general l4 interface ck, multi-parent functional clk */ /* general l4 interface ck, multi-parent functional clk */
......
arch/arm/mach-omap2/clock34xx.c
View file @ fd9470ce
...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk) ...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask), v = __raw_readl(dd->control_reg);
dd->control_reg); v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
__raw_writel(v, dd->control_reg);
} }
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) ...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
state <<= dd->idlest_bit; state <<= dd->idlest_bit;
idlest_mask = 1 << dd->idlest_bit; idlest_mask = 1 << dd->idlest_bit;
while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) { i < MAX_DPLL_WAIT_TRIES) {
i++; i++;
udelay(1); udelay(1);
...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
v = cm_read_reg(dd->autoidle_reg); v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask; v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask); v >>= __ffs(dd->autoidle_mask);
...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
static void omap3_dpll_allow_idle(struct clk *clk) static void omap3_dpll_allow_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
* by writing 0x5 instead of 0x1. Add some mechanism to * by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode. * optionally enter this mode.
*/ */
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/** /**
...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
static void omap3_dpll_deny_idle(struct clk *clk) static void omap3_dpll_deny_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/* Clock control for DPLL outputs */ /* Clock control for DPLL outputs */
...@@ -482,8 +489,10 @@ int __init omap2_clk_init(void) ...@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
for (clkp = onchip_34xx_clks; for (clkp = onchip_34xx_clks;
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
clkp++) { clkp++) {
if ((*clkp)->flags & cpu_clkflg) if ((*clkp)->flags & cpu_clkflg) {
clk_register(*clkp); clk_register(*clkp);
omap2_init_clk_clkdm(*clkp);
}
} }
/* REVISIT: Not yet ready for OMAP3 */ /* REVISIT: Not yet ready for OMAP3 */
......
arch/arm/mach-omap2/clock34xx.h
View file @ fd9470ce
...@@ -478,7 +478,7 @@ static struct clk dpll3_m2_ck = { ...@@ -478,7 +478,7 @@ static struct clk dpll3_m2_ck = {
}; };
static const struct clksel core_ck_clksel[] = { static const struct clksel core_ck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -495,7 +495,7 @@ static struct clk core_ck = { ...@@ -495,7 +495,7 @@ static struct clk core_ck = {
}; };
static const struct clksel dpll3_m2x2_ck_clksel[] = { static const struct clksel dpll3_m2x2_ck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -541,7 +541,7 @@ static struct clk dpll3_m3x2_ck = { ...@@ -541,7 +541,7 @@ static struct clk dpll3_m3x2_ck = {
}; };
static const struct clksel emu_core_alwon_ck_clksel[] = { static const struct clksel emu_core_alwon_ck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -633,7 +633,7 @@ static struct clk dpll4_m2x2_ck = { ...@@ -633,7 +633,7 @@ static struct clk dpll4_m2x2_ck = {
}; };
static const struct clksel omap_96m_alwon_fck_clksel[] = { static const struct clksel omap_96m_alwon_fck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -659,7 +659,7 @@ static struct clk omap_96m_fck = { ...@@ -659,7 +659,7 @@ static struct clk omap_96m_fck = {
}; };
static const struct clksel cm_96m_fck_clksel[] = { static const struct clksel cm_96m_fck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -701,7 +701,7 @@ static struct clk dpll4_m3x2_ck = { ...@@ -701,7 +701,7 @@ static struct clk dpll4_m3x2_ck = {
}; };
static const struct clksel virt_omap_54m_fck_clksel[] = { static const struct clksel virt_omap_54m_fck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -911,7 +911,7 @@ static struct clk dpll5_m2_ck = { ...@@ -911,7 +911,7 @@ static struct clk dpll5_m2_ck = {
}; };
static const struct clksel omap_120m_fck_clksel[] = { static const struct clksel omap_120m_fck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -919,13 +919,13 @@ static const struct clksel omap_120m_fck_clksel[] = { ...@@ -919,13 +919,13 @@ static const struct clksel omap_120m_fck_clksel[] = {
static struct clk omap_120m_fck = { static struct clk omap_120m_fck = {
.name = "omap_120m_fck", .name = "omap_120m_fck",
.parent = &dpll5_m2_ck, .parent = &dpll5_m2_ck,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
.clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
.clksel = omap_120m_fck_clksel, .clksel = omap_120m_fck_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
/* CM EXTERNAL CLOCK OUTPUTS */ /* CM EXTERNAL CLOCK OUTPUTS */
...@@ -1034,7 +1034,7 @@ static struct clk dpll1_fck = { ...@@ -1034,7 +1034,7 @@ static struct clk dpll1_fck = {
* called 'dpll1_fck' * called 'dpll1_fck'
*/ */
static const struct clksel mpu_clksel[] = { static const struct clksel mpu_clksel[] = {
{ .parent = &dpll1_fck, .rates = dpll_bypass_rates }, { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
{ .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -1048,6 +1048,7 @@ static struct clk mpu_ck = { ...@@ -1048,6 +1048,7 @@ static struct clk mpu_ck = {
.clksel = mpu_clksel, .clksel = mpu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "mpu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1075,6 +1076,8 @@ static struct clk arm_fck = { ...@@ -1075,6 +1076,8 @@ static struct clk arm_fck = {
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
/* XXX What about neon_clkdm ? */
/* /*
* REVISIT: This clock is never specifically defined in the 3430 TRM, * REVISIT: This clock is never specifically defined in the 3430 TRM,
* although it is referenced - so this is a guess * although it is referenced - so this is a guess
...@@ -1107,7 +1110,7 @@ static struct clk dpll2_fck = { ...@@ -1107,7 +1110,7 @@ static struct clk dpll2_fck = {
*/ */
static const struct clksel iva2_clksel[] = { static const struct clksel iva2_clksel[] = {
{ .parent = &dpll2_fck, .rates = dpll_bypass_rates }, { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
{ .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -1123,6 +1126,7 @@ static struct clk iva2_ck = { ...@@ -1123,6 +1126,7 @@ static struct clk iva2_ck = {
.clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
.clksel = iva2_clksel, .clksel = iva2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.clkdm_name = "iva2_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1137,6 +1141,7 @@ static struct clk l3_ick = { ...@@ -1137,6 +1141,7 @@ static struct clk l3_ick = {
.clksel = div2_core_clksel, .clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l3_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1154,6 +1159,7 @@ static struct clk l4_ick = { ...@@ -1154,6 +1159,7 @@ static struct clk l4_ick = {
.clksel = div2_l3_clksel, .clksel = div2_l3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1183,43 +1189,57 @@ static const struct clksel gfx_l3_clksel[] = { ...@@ -1183,43 +1189,57 @@ static const struct clksel gfx_l3_clksel[] = {
{ .parent = NULL } { .parent = NULL }
}; };
static struct clk gfx_l3_fck = { /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
.name = "gfx_l3_fck", static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.parent = &l3_ick, .parent = &l3_ick,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT, .enable_bit = OMAP_EN_GFX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
static struct clk gfx_l3_fck = {
.name = "gfx_l3_fck",
.parent = &gfx_l3_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel, .clksel = gfx_l3_clksel,
.flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk gfx_l3_ick = { static struct clk gfx_l3_ick = {
.name = "gfx_l3_ick", .name = "gfx_l3_ick",
.parent = &l3_ick, .parent = &gfx_l3_ck,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
.enable_bit = OMAP_EN_GFX_SHIFT, .clkdm_name = "gfx_3430es1_clkdm",
.flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk gfx_cg1_ck = { static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck", .name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */ .parent = &gfx_l3_fck, /* REVISIT: correct? */
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT, .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1, .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk gfx_cg2_ck = { static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck", .name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */ .parent = &gfx_l3_fck, /* REVISIT: correct? */
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT, .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1, .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1252,15 +1272,18 @@ static struct clk sgx_fck = { ...@@ -1252,15 +1272,18 @@ static struct clk sgx_fck = {
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel, .clksel = sgx_clksel,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "sgx_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk sgx_ick = { static struct clk sgx_ick = {
.name = "sgx_ick", .name = "sgx_ick",
.parent = &l3_ick, .parent = &l3_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_SGX_SHIFT, .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "sgx_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1269,9 +1292,11 @@ static struct clk sgx_ick = { ...@@ -1269,9 +1292,11 @@ static struct clk sgx_ick = {
static struct clk d2d_26m_fck = { static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck", .name = "d2d_26m_fck",
.parent = &sys_ck, .parent = &sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT, .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1, .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "d2d_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1291,6 +1316,7 @@ static struct clk gpt10_fck = { ...@@ -1291,6 +1316,7 @@ static struct clk gpt10_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1304,6 +1330,7 @@ static struct clk gpt11_fck = { ...@@ -1304,6 +1330,7 @@ static struct clk gpt11_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1341,6 +1368,7 @@ static struct clk core_96m_fck = { ...@@ -1341,6 +1368,7 @@ static struct clk core_96m_fck = {
.parent = &omap_96m_fck, .parent = &omap_96m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1351,6 +1379,7 @@ static struct clk mmchs3_fck = { ...@@ -1351,6 +1379,7 @@ static struct clk mmchs3_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1361,6 +1390,7 @@ static struct clk mmchs2_fck = { ...@@ -1361,6 +1390,7 @@ static struct clk mmchs2_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT, .enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1370,6 +1400,7 @@ static struct clk mspro_fck = { ...@@ -1370,6 +1400,7 @@ static struct clk mspro_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT, .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1380,6 +1411,7 @@ static struct clk mmchs1_fck = { ...@@ -1380,6 +1411,7 @@ static struct clk mmchs1_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT, .enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1390,16 +1422,18 @@ static struct clk i2c3_fck = { ...@@ -1390,16 +1422,18 @@ static struct clk i2c3_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT, .enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk i2c2_fck = { static struct clk i2c2_fck = {
.name = "i2c_fck", .name = "i2c_fck",
.id = 2, .id = 2,
.parent = &core_96m_fck, .parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT, .enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1410,6 +1444,7 @@ static struct clk i2c1_fck = { ...@@ -1410,6 +1444,7 @@ static struct clk i2c1_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT, .enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1443,6 +1478,7 @@ static struct clk mcbsp5_fck = { ...@@ -1443,6 +1478,7 @@ static struct clk mcbsp5_fck = {
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK, .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel, .clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1456,6 +1492,7 @@ static struct clk mcbsp1_fck = { ...@@ -1456,6 +1492,7 @@ static struct clk mcbsp1_fck = {
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK, .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel, .clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1466,6 +1503,7 @@ static struct clk core_48m_fck = { ...@@ -1466,6 +1503,7 @@ static struct clk core_48m_fck = {
.parent = &omap_48m_fck, .parent = &omap_48m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1543,6 +1581,7 @@ static struct clk core_12m_fck = { ...@@ -1543,6 +1581,7 @@ static struct clk core_12m_fck = {
.parent = &omap_12m_fck, .parent = &omap_12m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1581,6 +1620,7 @@ static struct clk ssi_ssr_fck = { ...@@ -1581,6 +1620,7 @@ static struct clk ssi_ssr_fck = {
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel, .clksel = ssi_ssr_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -1596,11 +1636,17 @@ static struct clk ssi_sst_fck = { ...@@ -1596,11 +1636,17 @@ static struct clk ssi_sst_fck = {
/* CORE_L3_ICK based clocks */ /* CORE_L3_ICK based clocks */
/*
* XXX must add clk_enable/clk_disable for these if standard code won't
* handle it
*/
static struct clk core_l3_ick = { static struct clk core_l3_ick = {
.name = "core_l3_ick", .name = "core_l3_ick",
.parent = &l3_ick, .parent = &l3_ick,
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1610,6 +1656,7 @@ static struct clk hsotgusb_ick = { ...@@ -1610,6 +1656,7 @@ static struct clk hsotgusb_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1619,6 +1666,7 @@ static struct clk sdrc_ick = { ...@@ -1619,6 +1666,7 @@ static struct clk sdrc_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT, .enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1627,6 +1675,7 @@ static struct clk gpmc_fck = { ...@@ -1627,6 +1675,7 @@ static struct clk gpmc_fck = {
.parent = &core_l3_ick, .parent = &core_l3_ick,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
ENABLE_ON_INIT, ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1654,8 +1703,10 @@ static struct clk pka_ick = { ...@@ -1654,8 +1703,10 @@ static struct clk pka_ick = {
static struct clk core_l4_ick = { static struct clk core_l4_ick = {
.name = "core_l4_ick", .name = "core_l4_ick",
.parent = &l4_ick, .parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1665,6 +1716,7 @@ static struct clk usbtll_ick = { ...@@ -1665,6 +1716,7 @@ static struct clk usbtll_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1675,6 +1727,7 @@ static struct clk mmchs3_ick = { ...@@ -1675,6 +1727,7 @@ static struct clk mmchs3_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1685,6 +1738,7 @@ static struct clk icr_ick = { ...@@ -1685,6 +1738,7 @@ static struct clk icr_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT, .enable_bit = OMAP3430_EN_ICR_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1694,6 +1748,7 @@ static struct clk aes2_ick = { ...@@ -1694,6 +1748,7 @@ static struct clk aes2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT, .enable_bit = OMAP3430_EN_AES2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1703,6 +1758,7 @@ static struct clk sha12_ick = { ...@@ -1703,6 +1758,7 @@ static struct clk sha12_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT, .enable_bit = OMAP3430_EN_SHA12_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1712,6 +1768,7 @@ static struct clk des2_ick = { ...@@ -1712,6 +1768,7 @@ static struct clk des2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT, .enable_bit = OMAP3430_EN_DES2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1722,6 +1779,7 @@ static struct clk mmchs2_ick = { ...@@ -1722,6 +1779,7 @@ static struct clk mmchs2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT, .enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1732,6 +1790,7 @@ static struct clk mmchs1_ick = { ...@@ -1732,6 +1790,7 @@ static struct clk mmchs1_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT, .enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1741,6 +1800,7 @@ static struct clk mspro_ick = { ...@@ -1741,6 +1800,7 @@ static struct clk mspro_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT, .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1750,6 +1810,7 @@ static struct clk hdq_ick = { ...@@ -1750,6 +1810,7 @@ static struct clk hdq_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT, .enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1760,6 +1821,7 @@ static struct clk mcspi4_ick = { ...@@ -1760,6 +1821,7 @@ static struct clk mcspi4_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1770,6 +1832,7 @@ static struct clk mcspi3_ick = { ...@@ -1770,6 +1832,7 @@ static struct clk mcspi3_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1780,6 +1843,7 @@ static struct clk mcspi2_ick = { ...@@ -1780,6 +1843,7 @@ static struct clk mcspi2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1790,6 +1854,7 @@ static struct clk mcspi1_ick = { ...@@ -1790,6 +1854,7 @@ static struct clk mcspi1_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1800,6 +1865,7 @@ static struct clk i2c3_ick = { ...@@ -1800,6 +1865,7 @@ static struct clk i2c3_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT, .enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1810,6 +1876,7 @@ static struct clk i2c2_ick = { ...@@ -1810,6 +1876,7 @@ static struct clk i2c2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT, .enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1820,6 +1887,7 @@ static struct clk i2c1_ick = { ...@@ -1820,6 +1887,7 @@ static struct clk i2c1_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT, .enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1829,6 +1897,7 @@ static struct clk uart2_ick = { ...@@ -1829,6 +1897,7 @@ static struct clk uart2_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT, .enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1838,6 +1907,7 @@ static struct clk uart1_ick = { ...@@ -1838,6 +1907,7 @@ static struct clk uart1_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT, .enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1847,6 +1917,7 @@ static struct clk gpt11_ick = { ...@@ -1847,6 +1917,7 @@ static struct clk gpt11_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT, .enable_bit = OMAP3430_EN_GPT11_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1856,6 +1927,7 @@ static struct clk gpt10_ick = { ...@@ -1856,6 +1927,7 @@ static struct clk gpt10_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT, .enable_bit = OMAP3430_EN_GPT10_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1866,6 +1938,7 @@ static struct clk mcbsp5_ick = { ...@@ -1866,6 +1938,7 @@ static struct clk mcbsp5_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1876,6 +1949,7 @@ static struct clk mcbsp1_ick = { ...@@ -1876,6 +1949,7 @@ static struct clk mcbsp1_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1885,6 +1959,7 @@ static struct clk fac_ick = { ...@@ -1885,6 +1959,7 @@ static struct clk fac_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT, .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1, .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1894,6 +1969,7 @@ static struct clk mailboxes_ick = { ...@@ -1894,6 +1969,7 @@ static struct clk mailboxes_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1913,6 +1989,7 @@ static struct clk ssi_l4_ick = { ...@@ -1913,6 +1989,7 @@ static struct clk ssi_l4_ick = {
.parent = &l4_ick, .parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1922,6 +1999,7 @@ static struct clk ssi_ick = { ...@@ -1922,6 +1999,7 @@ static struct clk ssi_ick = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT, .enable_bit = OMAP3430_EN_SSI_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -1996,7 +2074,7 @@ static struct clk des1_ick = { ...@@ -1996,7 +2074,7 @@ static struct clk des1_ick = {
/* DSS */ /* DSS */
static const struct clksel dss1_alwon_fck_clksel[] = { static const struct clksel dss1_alwon_fck_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -2011,33 +2089,40 @@ static struct clk dss1_alwon_fck = { ...@@ -2011,33 +2089,40 @@ static struct clk dss1_alwon_fck = {
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = dss1_alwon_fck_clksel, .clksel = dss1_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "dss_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk dss_tv_fck = { static struct clk dss_tv_fck = {
.name = "dss_tv_fck", .name = "dss_tv_fck",
.parent = &omap_54m_fck, .parent = &omap_54m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT, .enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dss_96m_fck = { static struct clk dss_96m_fck = {
.name = "dss_96m_fck", .name = "dss_96m_fck",
.parent = &omap_96m_fck, .parent = &omap_96m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT, .enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dss2_alwon_fck = { static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck", .name = "dss2_alwon_fck",
.parent = &sys_ck, .parent = &sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT, .enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2045,16 +2130,18 @@ static struct clk dss_ick = { ...@@ -2045,16 +2130,18 @@ static struct clk dss_ick = {
/* Handles both L3 and L4 clocks */ /* Handles both L3 and L4 clocks */
.name = "dss_ick", .name = "dss_ick",
.parent = &l4_ick, .parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
/* CAM */ /* CAM */
static const struct clksel cam_mclk_clksel[] = { static const struct clksel cam_mclk_clksel[] = {
{ .parent = &sys_ck, .rates = dpll_bypass_rates }, { .parent = &sys_ck, .rates = dpll_bypass_rates },
{ .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -2069,24 +2156,19 @@ static struct clk cam_mclk = { ...@@ -2069,24 +2156,19 @@ static struct clk cam_mclk = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT, .enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "cam_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk cam_l3_ick = { static struct clk cam_ick = {
.name = "cam_l3_ick", /* Handles both L3 and L4 clocks */
.parent = &l3_ick, .name = "cam_ick",
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
static struct clk cam_l4_ick = {
.name = "cam_l4_ick",
.parent = &l4_ick, .parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT, .enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "cam_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2095,45 +2177,45 @@ static struct clk cam_l4_ick = { ...@@ -2095,45 +2177,45 @@ static struct clk cam_l4_ick = {
static struct clk usbhost_120m_fck = { static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck", .name = "usbhost_120m_fck",
.parent = &omap_120m_fck, .parent = &omap_120m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk usbhost_48m_fck = { static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck", .name = "usbhost_48m_fck",
.parent = &omap_48m_fck, .parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk usbhost_l3_ick = { static struct clk usbhost_ick = {
.name = "usbhost_l3_ick", /* Handles both L3 and L4 clocks */
.parent = &l3_ick, .name = "usbhost_ick",
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
.recalc = &followparent_recalc,
};
static struct clk usbhost_l4_ick = {
.name = "usbhost_l4_ick",
.parent = &l4_ick, .parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk usbhost_sar_fck = { static struct clk usbhost_sar_fck = {
.name = "usbhost_sar_fck", .name = "usbhost_sar_fck",
.parent = &osc_sys_ck, .parent = &osc_sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
.enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2175,6 +2257,7 @@ static struct clk usim_fck = { ...@@ -2175,6 +2257,7 @@ static struct clk usim_fck = {
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
static struct clk gpt1_fck = { static struct clk gpt1_fck = {
.name = "gpt1_fck", .name = "gpt1_fck",
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -2184,13 +2267,16 @@ static struct clk gpt1_fck = { ...@@ -2184,13 +2267,16 @@ static struct clk gpt1_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk wkup_32k_fck = { static struct clk wkup_32k_fck = {
.name = "wkup_32k_fck", .name = "wkup_32k_fck",
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck, .parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2200,6 +2286,7 @@ static struct clk gpio1_fck = { ...@@ -2200,6 +2286,7 @@ static struct clk gpio1_fck = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT, .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2209,6 +2296,7 @@ static struct clk wdt2_fck = { ...@@ -2209,6 +2296,7 @@ static struct clk wdt2_fck = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT, .enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2216,6 +2304,7 @@ static struct clk wkup_l4_ick = { ...@@ -2216,6 +2304,7 @@ static struct clk wkup_l4_ick = {
.name = "wkup_l4_ick", .name = "wkup_l4_ick",
.parent = &sys_ck, .parent = &sys_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2227,6 +2316,7 @@ static struct clk usim_ick = { ...@@ -2227,6 +2316,7 @@ static struct clk usim_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2, .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2236,6 +2326,7 @@ static struct clk wdt2_ick = { ...@@ -2236,6 +2326,7 @@ static struct clk wdt2_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT, .enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2245,6 +2336,7 @@ static struct clk wdt1_ick = { ...@@ -2245,6 +2336,7 @@ static struct clk wdt1_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT, .enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2254,6 +2346,7 @@ static struct clk gpio1_ick = { ...@@ -2254,6 +2346,7 @@ static struct clk gpio1_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT, .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2263,15 +2356,18 @@ static struct clk omap_32ksync_ick = { ...@@ -2263,15 +2356,18 @@ static struct clk omap_32ksync_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT, .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = { static struct clk gpt12_ick = {
.name = "gpt12_ick", .name = "gpt12_ick",
.parent = &wkup_l4_ick, .parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT, .enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2281,6 +2377,7 @@ static struct clk gpt1_ick = { ...@@ -2281,6 +2377,7 @@ static struct clk gpt1_ick = {
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT, .enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2291,16 +2388,20 @@ static struct clk gpt1_ick = { ...@@ -2291,16 +2388,20 @@ static struct clk gpt1_ick = {
static struct clk per_96m_fck = { static struct clk per_96m_fck = {
.name = "per_96m_fck", .name = "per_96m_fck",
.parent = &omap_96m_alwon_fck, .parent = &omap_96m_alwon_fck,
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk per_48m_fck = { static struct clk per_48m_fck = {
.name = "per_48m_fck", .name = "per_48m_fck",
.parent = &omap_48m_fck, .parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2310,6 +2411,7 @@ static struct clk uart3_fck = { ...@@ -2310,6 +2411,7 @@ static struct clk uart3_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT, .enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2322,6 +2424,7 @@ static struct clk gpt2_fck = { ...@@ -2322,6 +2424,7 @@ static struct clk gpt2_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2334,6 +2437,7 @@ static struct clk gpt3_fck = { ...@@ -2334,6 +2437,7 @@ static struct clk gpt3_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2346,6 +2450,7 @@ static struct clk gpt4_fck = { ...@@ -2346,6 +2450,7 @@ static struct clk gpt4_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2358,6 +2463,7 @@ static struct clk gpt5_fck = { ...@@ -2358,6 +2463,7 @@ static struct clk gpt5_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2370,6 +2476,7 @@ static struct clk gpt6_fck = { ...@@ -2370,6 +2476,7 @@ static struct clk gpt6_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2382,6 +2489,7 @@ static struct clk gpt7_fck = { ...@@ -2382,6 +2489,7 @@ static struct clk gpt7_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2394,6 +2502,7 @@ static struct clk gpt8_fck = { ...@@ -2394,6 +2502,7 @@ static struct clk gpt8_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2406,12 +2515,14 @@ static struct clk gpt9_fck = { ...@@ -2406,12 +2515,14 @@ static struct clk gpt9_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel, .clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk per_32k_alwon_fck = { static struct clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck", .name = "per_32k_alwon_fck",
.parent = &omap_32k_fck, .parent = &omap_32k_fck,
.clkdm_name = "per_clkdm",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2422,6 +2533,7 @@ static struct clk gpio6_fck = { ...@@ -2422,6 +2533,7 @@ static struct clk gpio6_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT, .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2431,6 +2543,7 @@ static struct clk gpio5_fck = { ...@@ -2431,6 +2543,7 @@ static struct clk gpio5_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT, .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2440,6 +2553,7 @@ static struct clk gpio4_fck = { ...@@ -2440,6 +2553,7 @@ static struct clk gpio4_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT, .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2449,6 +2563,7 @@ static struct clk gpio3_fck = { ...@@ -2449,6 +2563,7 @@ static struct clk gpio3_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT, .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2458,6 +2573,7 @@ static struct clk gpio2_fck = { ...@@ -2458,6 +2573,7 @@ static struct clk gpio2_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT, .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2467,6 +2583,7 @@ static struct clk wdt3_fck = { ...@@ -2467,6 +2583,7 @@ static struct clk wdt3_fck = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT, .enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2475,6 +2592,7 @@ static struct clk per_l4_ick = { ...@@ -2475,6 +2592,7 @@ static struct clk per_l4_ick = {
.parent = &l4_ick, .parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK, PARENT_CONTROLS_CLOCK,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2484,6 +2602,7 @@ static struct clk gpio6_ick = { ...@@ -2484,6 +2602,7 @@ static struct clk gpio6_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT, .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2493,6 +2612,7 @@ static struct clk gpio5_ick = { ...@@ -2493,6 +2612,7 @@ static struct clk gpio5_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT, .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2502,6 +2622,7 @@ static struct clk gpio4_ick = { ...@@ -2502,6 +2622,7 @@ static struct clk gpio4_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT, .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2511,6 +2632,7 @@ static struct clk gpio3_ick = { ...@@ -2511,6 +2632,7 @@ static struct clk gpio3_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT, .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2520,6 +2642,7 @@ static struct clk gpio2_ick = { ...@@ -2520,6 +2642,7 @@ static struct clk gpio2_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT, .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2529,6 +2652,7 @@ static struct clk wdt3_ick = { ...@@ -2529,6 +2652,7 @@ static struct clk wdt3_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT, .enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2538,6 +2662,7 @@ static struct clk uart3_ick = { ...@@ -2538,6 +2662,7 @@ static struct clk uart3_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT, .enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2547,6 +2672,7 @@ static struct clk gpt9_ick = { ...@@ -2547,6 +2672,7 @@ static struct clk gpt9_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT, .enable_bit = OMAP3430_EN_GPT9_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2556,6 +2682,7 @@ static struct clk gpt8_ick = { ...@@ -2556,6 +2682,7 @@ static struct clk gpt8_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT, .enable_bit = OMAP3430_EN_GPT8_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2565,6 +2692,7 @@ static struct clk gpt7_ick = { ...@@ -2565,6 +2692,7 @@ static struct clk gpt7_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT, .enable_bit = OMAP3430_EN_GPT7_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2574,6 +2702,7 @@ static struct clk gpt6_ick = { ...@@ -2574,6 +2702,7 @@ static struct clk gpt6_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT, .enable_bit = OMAP3430_EN_GPT6_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2583,6 +2712,7 @@ static struct clk gpt5_ick = { ...@@ -2583,6 +2712,7 @@ static struct clk gpt5_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT, .enable_bit = OMAP3430_EN_GPT5_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2592,6 +2722,7 @@ static struct clk gpt4_ick = { ...@@ -2592,6 +2722,7 @@ static struct clk gpt4_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT, .enable_bit = OMAP3430_EN_GPT4_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2601,6 +2732,7 @@ static struct clk gpt3_ick = { ...@@ -2601,6 +2732,7 @@ static struct clk gpt3_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT, .enable_bit = OMAP3430_EN_GPT3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2610,6 +2742,7 @@ static struct clk gpt2_ick = { ...@@ -2610,6 +2742,7 @@ static struct clk gpt2_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT, .enable_bit = OMAP3430_EN_GPT2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2620,6 +2753,7 @@ static struct clk mcbsp2_ick = { ...@@ -2620,6 +2753,7 @@ static struct clk mcbsp2_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2630,6 +2764,7 @@ static struct clk mcbsp3_ick = { ...@@ -2630,6 +2764,7 @@ static struct clk mcbsp3_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2640,12 +2775,13 @@ static struct clk mcbsp4_ick = { ...@@ -2640,12 +2775,13 @@ static struct clk mcbsp4_ick = {
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static const struct clksel mcbsp_234_clksel[] = { static const struct clksel mcbsp_234_clksel[] = {
{ .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
{ .parent = NULL } { .parent = NULL }
}; };
...@@ -2659,6 +2795,7 @@ static struct clk mcbsp2_fck = { ...@@ -2659,6 +2795,7 @@ static struct clk mcbsp2_fck = {
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK, .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
.clksel = mcbsp_234_clksel, .clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2672,6 +2809,7 @@ static struct clk mcbsp3_fck = { ...@@ -2672,6 +2809,7 @@ static struct clk mcbsp3_fck = {
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK, .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel, .clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2685,6 +2823,7 @@ static struct clk mcbsp4_fck = { ...@@ -2685,6 +2823,7 @@ static struct clk mcbsp4_fck = {
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK, .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
.clksel = mcbsp_234_clksel, .clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2732,6 +2871,7 @@ static struct clk emu_src_ck = { ...@@ -2732,6 +2871,7 @@ static struct clk emu_src_ck = {
.clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clksel = emu_src_clksel, .clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2755,6 +2895,7 @@ static struct clk pclk_fck = { ...@@ -2755,6 +2895,7 @@ static struct clk pclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
.clksel = pclk_emu_clksel, .clksel = pclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2777,6 +2918,7 @@ static struct clk pclkx2_fck = { ...@@ -2777,6 +2918,7 @@ static struct clk pclkx2_fck = {
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
.clksel = pclkx2_emu_clksel, .clksel = pclkx2_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2792,6 +2934,7 @@ static struct clk atclk_fck = { ...@@ -2792,6 +2934,7 @@ static struct clk atclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
.clksel = atclk_emu_clksel, .clksel = atclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2802,6 +2945,7 @@ static struct clk traceclk_src_fck = { ...@@ -2802,6 +2945,7 @@ static struct clk traceclk_src_fck = {
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
.clksel = emu_src_clksel, .clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2824,6 +2968,7 @@ static struct clk traceclk_fck = { ...@@ -2824,6 +2968,7 @@ static struct clk traceclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
.clksel = traceclk_clksel, .clksel = traceclk_clksel,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
.clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
...@@ -2853,11 +2998,13 @@ static struct clk sr_l4_ick = { ...@@ -2853,11 +2998,13 @@ static struct clk sr_l4_ick = {
.name = "sr_l4_ick", .name = "sr_l4_ick",
.parent = &l4_ick, .parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
/* SECURE_32K_FCK clocks */ /* SECURE_32K_FCK clocks */
/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_fck = { static struct clk gpt12_fck = {
.name = "gpt12_fck", .name = "gpt12_fck",
.parent = &secure_32k_fck, .parent = &secure_32k_fck,
...@@ -2933,6 +3080,7 @@ static struct clk *onchip_34xx_clks[] __initdata = { ...@@ -2933,6 +3080,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&l3_ick, &l3_ick,
&l4_ick, &l4_ick,
&rm_ick, &rm_ick,
&gfx_l3_ck,
&gfx_l3_fck, &gfx_l3_fck,
&gfx_l3_ick, &gfx_l3_ick,
&gfx_cg1_ck, &gfx_cg1_ck,
...@@ -3014,12 +3162,10 @@ static struct clk *onchip_34xx_clks[] __initdata = { ...@@ -3014,12 +3162,10 @@ static struct clk *onchip_34xx_clks[] __initdata = {
&dss2_alwon_fck, &dss2_alwon_fck,
&dss_ick, &dss_ick,
&cam_mclk, &cam_mclk,
&cam_l3_ick, &cam_ick,
&cam_l4_ick,
&usbhost_120m_fck, &usbhost_120m_fck,
&usbhost_48m_fck, &usbhost_48m_fck,
&usbhost_l3_ick, &usbhost_ick,
&usbhost_l4_ick,
&usbhost_sar_fck, &usbhost_sar_fck,
&usim_fck, &usim_fck,
&gpt1_fck, &gpt1_fck,
......
arch/arm/mach-omap2/clockdomain.c 0 → 100644
View file @ fd9470ce
/*
* OMAP2/3 clockdomain framework functions
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
# define DEBUG
#endif
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/limits.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <mach/clock.h>
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include <mach/powerdomain.h>
#include <mach/clockdomain.h>
/* clkdm_list contains all registered struct clockdomains */
static LIST_HEAD(clkdm_list);
/* clkdm_mutex protects clkdm_list add and del ops */
static DEFINE_MUTEX(clkdm_mutex);
/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
static struct clkdm_pwrdm_autodep *autodeps;
/* Private functions */
/*
* _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
* @autodep: struct clkdm_pwrdm_autodep * to resolve
*
* Resolve autodep powerdomain names to powerdomain pointers via
* pwrdm_lookup() and store the pointers in the autodep structure. An
* "autodep" is a powerdomain sleep/wakeup dependency that is
* automatically added and removed whenever clocks in the associated
* clockdomain are enabled or disabled (respectively) when the
* clockdomain is in hardware-supervised mode. Meant to be called
* once at clockdomain layer initialization, since these should remain
* fixed for a particular architecture. No return value.
*/
static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
{
struct powerdomain *pwrdm;
if (!autodep)
return;
if (!omap_chip_is(autodep->omap_chip))
return;
pwrdm = pwrdm_lookup(autodep->pwrdm_name);
if (!pwrdm) {
pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
"does not exist\n", autodep->pwrdm_name);
WARN_ON(1);
return;
}
autodep->pwrdm = pwrdm;
return;
}
/*
* _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
* @clkdm: struct clockdomain *
*
* Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
* in hardware-supervised mode. Meant to be called from clock framework
* when a clock inside clockdomain 'clkdm' is enabled. No return value.
*/
static void _clkdm_add_autodeps(struct clockdomain *clkdm)
{
struct clkdm_pwrdm_autodep *autodep;
for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
if (!autodep->pwrdm)
continue;
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
"pwrdm %s\n", autodep->pwrdm_name,
clkdm->pwrdm->name);
pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
}
}
/*
* _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
* @clkdm: struct clockdomain *
*
* Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
* in hardware-supervised mode. Meant to be called from clock framework
* when a clock inside clockdomain 'clkdm' is disabled. No return value.
*/
static void _clkdm_del_autodeps(struct clockdomain *clkdm)
{
struct clkdm_pwrdm_autodep *autodep;
for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
if (!autodep->pwrdm)
continue;
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
"pwrdm %s\n", autodep->pwrdm_name,
clkdm->pwrdm->name);
pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
}
}
static struct clockdomain *_clkdm_lookup(const char *name)
{
struct clockdomain *clkdm, *temp_clkdm;
if (!name)
return NULL;
clkdm = NULL;
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
if (!strcmp(name, temp_clkdm->name)) {
clkdm = temp_clkdm;
break;
}
}
return clkdm;
}
/* Public functions */
/**
* clkdm_init - set up the clockdomain layer
* @clkdms: optional pointer to an array of clockdomains to register
* @init_autodeps: optional pointer to an array of autodeps to register
*
* Set up internal state. If a pointer to an array of clockdomains
* was supplied, loop through the list of clockdomains, register all
* that are available on the current platform. Similarly, if a
* pointer to an array of clockdomain-powerdomain autodependencies was
* provided, register those. No return value.
*/
void clkdm_init(struct clockdomain **clkdms,
struct clkdm_pwrdm_autodep *init_autodeps)
{
struct clockdomain **c = NULL;
struct clkdm_pwrdm_autodep *autodep = NULL;
if (clkdms)
for (c = clkdms; *c; c++)
clkdm_register(*c);
autodeps = init_autodeps;
if (autodeps)
for (autodep = autodeps; autodep->pwrdm_name; autodep++)
_autodep_lookup(autodep);
}
/**
* clkdm_register - register a clockdomain
* @clkdm: struct clockdomain * to register
*
* Adds a clockdomain to the internal clockdomain list.
* Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
* already registered by the provided name, or 0 upon success.
*/
int clkdm_register(struct clockdomain *clkdm)
{
int ret = -EINVAL;
struct powerdomain *pwrdm;
if (!clkdm || !clkdm->name)
return -EINVAL;
if (!omap_chip_is(clkdm->omap_chip))
return -EINVAL;
pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
if (!pwrdm) {
pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
"does not exist\n", clkdm->name, clkdm->pwrdm_name);
return -EINVAL;
}
clkdm->pwrdm = pwrdm;
mutex_lock(&clkdm_mutex);
/* Verify that the clockdomain is not already registered */
if (_clkdm_lookup(clkdm->name)) {
ret = -EEXIST;
goto cr_unlock;
};
list_add(&clkdm->node, &clkdm_list);
pwrdm_add_clkdm(pwrdm, clkdm);
pr_debug("clockdomain: registered %s\n", clkdm->name);
ret = 0;
cr_unlock:
mutex_unlock(&clkdm_mutex);
return ret;
}
/**
* clkdm_unregister - unregister a clockdomain
* @clkdm: struct clockdomain * to unregister
*
* Removes a clockdomain from the internal clockdomain list. Returns
* -EINVAL if clkdm argument is NULL.
*/
int clkdm_unregister(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
mutex_lock(&clkdm_mutex);
list_del(&clkdm->node);
mutex_unlock(&clkdm_mutex);
pr_debug("clockdomain: unregistered %s\n", clkdm->name);
return 0;
}
/**
* clkdm_lookup - look up a clockdomain by name, return a pointer
* @name: name of clockdomain
*
* Find a registered clockdomain by its name. Returns a pointer to the
* struct clockdomain if found, or NULL otherwise.
*/
struct clockdomain *clkdm_lookup(const char *name)
{
struct clockdomain *clkdm, *temp_clkdm;
if (!name)
return NULL;
clkdm = NULL;
mutex_lock(&clkdm_mutex);
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
if (!strcmp(name, temp_clkdm->name)) {
clkdm = temp_clkdm;
break;
}
}
mutex_unlock(&clkdm_mutex);
return clkdm;
}
/**
* clkdm_for_each - call function on each registered clockdomain
* @fn: callback function *
*
* Call the supplied function for each registered clockdomain.
* The callback function can return anything but 0 to bail
* out early from the iterator. The callback function is called with
* the clkdm_mutex held, so no clockdomain structure manipulation
* functions should be called from the callback, although hardware
* clockdomain control functions are fine. Returns the last return
* value of the callback function, which should be 0 for success or
* anything else to indicate failure; or -EINVAL if the function pointer
* is null.
*/
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
{
struct clockdomain *clkdm;
int ret = 0;
if (!fn)
return -EINVAL;
mutex_lock(&clkdm_mutex);
list_for_each_entry(clkdm, &clkdm_list, node) {
ret = (*fn)(clkdm);
if (ret)
break;
}
mutex_unlock(&clkdm_mutex);
return ret;
}
/**
* clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
* @clkdm: struct clockdomain *
*
* Return a pointer to the struct powerdomain that the specified clockdomain
* 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
*/
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
{
if (!clkdm)
return NULL;
return clkdm->pwrdm;
}
/* Hardware clockdomain control */
/**
* omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
* @clk: struct clk * of a clockdomain
*
* Return the clockdomain's current state transition mode from the
* corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk
* is NULL or the current mode upon success.
*/
static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
{
u32 v;
if (!clkdm)
return -EINVAL;
v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
v &= clkdm->clktrctrl_mask;
v >>= __ffs(clkdm->clktrctrl_mask);
return v;
}
/**
* omap2_clkdm_sleep - force clockdomain sleep transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
* clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if
* clockdomain does not support software-initiated sleep; 0 upon
* success.
*/
int omap2_clkdm_sleep(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
pr_debug("clockdomain: %s does not support forcing "
"sleep via software\n", clkdm->name);
return -EINVAL;
}
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
if (cpu_is_omap24xx()) {
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
} else if (cpu_is_omap34xx()) {
u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
__ffs(clkdm->clktrctrl_mask));
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
} else {
BUG();
};
return 0;
}
/**
* omap2_clkdm_wakeup - force clockdomain wakeup transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
* clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the
* clockdomain does not support software-controlled wakeup; 0 upon
* success.
*/
int omap2_clkdm_wakeup(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
pr_debug("clockdomain: %s does not support forcing "
"wakeup via software\n", clkdm->name);
return -EINVAL;
}
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
if (cpu_is_omap24xx()) {
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
} else if (cpu_is_omap34xx()) {
u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
__ffs(clkdm->clktrctrl_mask));
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
} else {
BUG();
};
return 0;
}
/**
* omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Allow the hardware to automatically switch the clockdomain into
* active or idle states, as needed by downstream clocks. If the
* clockdomain has any downstream clocks enabled in the clock
* framework, wkdep/sleepdep autodependencies are added; this is so
* device drivers can read and write to the device. No return value.
*/
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
{
u32 v;
if (!clkdm)
return;
if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
pr_debug("clock: automatic idle transitions cannot be enabled "
"on clockdomain %s\n", clkdm->name);
return;
}
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
if (cpu_is_omap24xx())
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
else if (cpu_is_omap34xx())
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
else
BUG();
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm->prcm_offs,
CM_CLKSTCTRL);
}
/**
* omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
* into inactive or idle states. If the clockdomain has downstream
* clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. No return value.
*/
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
{
u32 v;
if (!clkdm)
return;
if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
pr_debug("clockdomain: automatic idle transitions cannot be "
"disabled on %s\n", clkdm->name);
return;
}
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
if (cpu_is_omap24xx())
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
else if (cpu_is_omap34xx())
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
else
BUG();
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
}
/* Clockdomain-to-clock framework interface code */
/**
* omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
* Increment the usecount of this clockdomain 'clkdm' and ensure that
* it is awake. Intended to be called by clk_enable() code. If the
* clockdomain is in software-supervised idle mode, force the
* clockdomain to wake. If the clockdomain is in hardware-supervised
* idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
* in the clockdomain can be read from/written to by on-chip processors.
* Returns -EINVAL if passed null pointers; returns 0 upon success or
* if the clockdomain is in hwsup idle mode.
*/
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
{
int v;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
*/
if (!clkdm || !clk)
return -EINVAL;
if (atomic_inc_return(&clkdm->usecount) > 1)
return 0;
/* Clockdomain now has one enabled downstream clock */
pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
clk->name);
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
_clkdm_add_autodeps(clkdm);
else
omap2_clkdm_wakeup(clkdm);
return 0;
}
/**
* omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
*
* Decrement the usecount of this clockdomain 'clkdm'. Intended to be
* called by clk_disable() code. If the usecount goes to 0, put the
* clockdomain to sleep (software-supervised mode) or remove the
* clkdm-pwrdm autodependencies (hardware-supervised mode). Returns
* -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
* underflows and debugging is enabled; or returns 0 upon success or
* if the clockdomain is in hwsup idle mode.
*/
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
int v;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
*/
if (!clkdm || !clk)
return -EINVAL;
#ifdef DEBUG
if (atomic_read(&clkdm->usecount) == 0) {
WARN_ON(1); /* underflow */
return -ERANGE;
}
#endif
if (atomic_dec_return(&clkdm->usecount) > 0)
return 0;
/* All downstream clocks of this clockdomain are now disabled */
pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
clk->name);
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
_clkdm_del_autodeps(clkdm);
else
omap2_clkdm_sleep(clkdm);
return 0;
}
arch/arm/mach-omap2/clockdomains.h 0 → 100644
View file @ fd9470ce
/*
* OMAP2/3 clockdomains
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation
*
* Written by Paul Walmsley
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#include <mach/clockdomain.h>
/*
* OMAP2/3-common clockdomains
*/
/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
.name = "wkup_clkdm",
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
/*
* 2420-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2420)
static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
.pwrdm_name = "dsp_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
#endif /* CONFIG_ARCH_OMAP2420 */
/*
* 2430-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2430)
static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
.pwrdm_name = "mdm_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
#endif /* CONFIG_ARCH_OMAP2430 */
/*
* 24XX-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP24XX)
static struct clockdomain dsp_clkdm = {
.name = "dsp_clkdm",
.pwrdm_name = "dsp_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain gfx_24xx_clkdm = {
.name = "gfx_clkdm",
.pwrdm_name = "gfx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain core_l3_24xx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain core_l4_24xx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
static struct clockdomain dss_24xx_clkdm = {
.name = "dss_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
};
#endif /* CONFIG_ARCH_OMAP24XX */
/*
* 34xx clockdomains
*/
#if defined(CONFIG_ARCH_OMAP34XX)
static struct clockdomain mpu_34xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm_name = "mpu_pwrdm",
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
.pwrdm_name = "neon_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm_name = "iva2_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
.pwrdm_name = "gfx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};
static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
.pwrdm_name = "sgx_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
};
/*
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
* then that information was removed from the 34xx ES2+ TRM. It is
* unclear whether the core is still there, but the clockdomain logic
* is there, and must be programmed to an appropriate state if the
* CORE clockdomain is to become inactive.
*/
static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain core_l3_34xx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain core_l4_34xx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm_name = "core_pwrdm",
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain dss_34xx_clkdm = {
.name = "dss_clkdm",
.pwrdm_name = "dss_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
.pwrdm_name = "cam_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
.pwrdm_name = "usbhost_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
};
static struct clockdomain per_clkdm = {
.name = "per_clkdm",
.pwrdm_name = "per_pwrdm",
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm_name = "emu_pwrdm",
.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
#endif /* CONFIG_ARCH_OMAP34XX */
/*
* Clockdomain-powerdomain hwsup dependencies (34XX only)
*/
static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL }
};
/*
*
*/
static struct clockdomain *clockdomains_omap[] = {
&wkup_clkdm,
#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
&iva1_2420_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
&mpu_2430_clkdm,
&mdm_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP24XX
&dsp_clkdm,
&gfx_24xx_clkdm,
&core_l3_24xx_clkdm,
&core_l4_24xx_clkdm,
&dss_24xx_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP34XX
&mpu_34xx_clkdm,
&neon_clkdm,
&iva2_clkdm,
&gfx_3430es1_clkdm,
&sgx_clkdm,
&d2d_clkdm,
&core_l3_34xx_clkdm,
&core_l4_34xx_clkdm,
&dss_34xx_clkdm,
&cam_clkdm,
&usbhost_clkdm,
&per_clkdm,
&emu_clkdm,
#endif
NULL,
};
#endif
arch/arm/mach-omap2/cm-regbits-24xx.h
View file @ fd9470ce
...@@ -63,7 +63,8 @@ ...@@ -63,7 +63,8 @@
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
/* CM_CLKSTCTRL_MPU */ /* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU (1 << 0) #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits*/ /* CM_FCLKEN1_CORE specific bits*/
#define OMAP24XX_EN_TV_SHIFT 2 #define OMAP24XX_EN_TV_SHIFT 2
...@@ -238,9 +239,12 @@ ...@@ -238,9 +239,12 @@
#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
/* CM_CLKSTCTRL_CORE */ /* CM_CLKSTCTRL_CORE */
#define OMAP24XX_AUTOSTATE_DSS (1 << 2) #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
#define OMAP24XX_AUTOSTATE_L4 (1 << 1) #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
#define OMAP24XX_AUTOSTATE_L3 (1 << 0) #define OMAP24XX_AUTOSTATE_L4_SHIFT 1
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */ /* CM_FCLKEN_GFX */
#define OMAP24XX_EN_3D_SHIFT 2 #define OMAP24XX_EN_3D_SHIFT 2
...@@ -255,7 +259,8 @@ ...@@ -255,7 +259,8 @@
/* CM_CLKSEL_GFX specific bits */ /* CM_CLKSEL_GFX specific bits */
/* CM_CLKSTCTRL_GFX */ /* CM_CLKSTCTRL_GFX */
#define OMAP24XX_AUTOSTATE_GFX (1 << 0) #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */ /* CM_FCLKEN_WKUP specific bits */
...@@ -367,8 +372,10 @@ ...@@ -367,8 +372,10 @@
#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
/* CM_CLKSTCTRL_DSP */ /* CM_CLKSTCTRL_DSP */
#define OMAP2420_AUTOSTATE_IVA (1 << 8) #define OMAP2420_AUTOSTATE_IVA_SHIFT 8
#define OMAP24XX_AUTOSTATE_DSP (1 << 0) #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
/* CM_FCLKEN_MDM */ /* CM_FCLKEN_MDM */
/* 2430 only */ /* 2430 only */
...@@ -396,6 +403,7 @@ ...@@ -396,6 +403,7 @@
/* CM_CLKSTCTRL_MDM */ /* CM_CLKSTCTRL_MDM */
/* 2430 only */ /* 2430 only */
#define OMAP2430_AUTOSTATE_MDM (1 << 0) #define OMAP2430_AUTOSTATE_MDM_SHIFT 0
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
#endif #endif
arch/arm/mach-omap2/cm-regbits-34xx.h
View file @ fd9470ce
...@@ -96,7 +96,8 @@ ...@@ -96,7 +96,8 @@
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
/* CM_CLKSTST_IVA2 */ /* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
/* CM_REVISION specific bits */ /* CM_REVISION specific bits */
...@@ -140,7 +141,8 @@ ...@@ -140,7 +141,8 @@
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
/* CM_CLKSTST_MPU */ /* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU (1 << 0) #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits */ /* CM_FCLKEN1_CORE specific bits */
...@@ -300,9 +302,12 @@ ...@@ -300,9 +302,12 @@
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */ /* CM_CLKSTST_CORE */
#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
#define OMAP3430_CLKACTIVITY_L4 (1 << 1) #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
#define OMAP3430_CLKACTIVITY_L3 (1 << 0) #define OMAP3430_CLKACTIVITY_L4_SHIFT 1
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */ /* CM_FCLKEN_GFX */
#define OMAP3430ES1_EN_3D (1 << 2) #define OMAP3430ES1_EN_3D (1 << 2)
...@@ -323,7 +328,8 @@ ...@@ -323,7 +328,8 @@
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
/* CM_CLKSTST_GFX */ /* CM_CLKSTST_GFX */
#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
/* CM_FCLKEN_SGX */ /* CM_FCLKEN_SGX */
#define OMAP3430ES2_EN_SGX_SHIFT 1 #define OMAP3430ES2_EN_SGX_SHIFT 1
...@@ -333,6 +339,14 @@ ...@@ -333,6 +339,14 @@
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
/* CM_CLKSTCTRL_SGX */
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
/* CM_CLKSTST_SGX */
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */ /* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
...@@ -498,7 +512,8 @@ ...@@ -498,7 +512,8 @@
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
/* CM_CLKSTST_DSS */ /* CM_CLKSTST_DSS */
#define OMAP3430_CLKACTIVITY_DSS (1 << 0) #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
/* CM_FCLKEN_CAM specific bits */ /* CM_FCLKEN_CAM specific bits */
...@@ -522,7 +537,8 @@ ...@@ -522,7 +537,8 @@
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
/* CM_CLKSTST_CAM */ /* CM_CLKSTST_CAM */
#define OMAP3430_CLKACTIVITY_CAM (1 << 0) #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
/* CM_FCLKEN_PER specific bits */ /* CM_FCLKEN_PER specific bits */
...@@ -598,7 +614,8 @@ ...@@ -598,7 +614,8 @@
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
/* CM_CLKSTST_PER */ /* CM_CLKSTST_PER */
#define OMAP3430_CLKACTIVITY_PER (1 << 0) #define OMAP3430_CLKACTIVITY_PER_SHIFT 0
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
/* CM_CLKSEL1_EMU */ /* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24 #define OMAP3430_DIV_DPLL4_SHIFT 24
...@@ -623,7 +640,8 @@ ...@@ -623,7 +640,8 @@
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
/* CM_CLKSTST_EMU */ /* CM_CLKSTST_EMU */
#define OMAP3430_CLKACTIVITY_EMU (1 << 0) #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
/* CM_CLKSEL2_EMU specific bits */ /* CM_CLKSEL2_EMU specific bits */
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
...@@ -673,6 +691,8 @@ ...@@ -673,6 +691,8 @@
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
/* CM_CLKSTST_USBHOST */
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
#endif #endif
arch/arm/mach-omap2/io.c
View file @ fd9470ce
...@@ -24,6 +24,13 @@ ...@@ -24,6 +24,13 @@
#include <mach/mux.h> #include <mach/mux.h>
#include <mach/omapfb.h> #include <mach/omapfb.h>
#include <mach/powerdomain.h>
#include "powerdomains.h"
#include <mach/clockdomain.h>
#include "clockdomains.h"
extern void omap_sram_init(void); extern void omap_sram_init(void);
extern int omap2_clk_init(void); extern int omap2_clk_init(void);
extern void omap2_check_revision(void); extern void omap2_check_revision(void);
...@@ -101,6 +108,8 @@ void __init omap2_map_common_io(void) ...@@ -101,6 +108,8 @@ void __init omap2_map_common_io(void)
void __init omap2_init_common_hw(void) void __init omap2_init_common_hw(void)
{ {
omap2_mux_init(); omap2_mux_init();
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init(); omap2_clk_init();
/* /*
* Need to Fix this for 2430 * Need to Fix this for 2430
......
arch/arm/mach-omap2/powerdomain.c 0 → 100644
View file @ fd9470ce
/*
* OMAP powerdomain control
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
# define DEBUG
#endif
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/atomic.h>
#include "cm.h"
#include "cm-regbits-34xx.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include <mach/cpu.h>
#include <mach/powerdomain.h>
#include <mach/clockdomain.h>
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
/*
* pwrdm_rwlock protects pwrdm_list add and del ops - also reused to
* protect pwrdm_clkdms[] during clkdm add/del ops
*/
static DEFINE_RWLOCK(pwrdm_rwlock);
/* Private functions */
static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
u32 v;
v = prm_read_mod_reg(domain, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
static struct powerdomain *_pwrdm_lookup(const char *name)
{
struct powerdomain *pwrdm, *temp_pwrdm;
pwrdm = NULL;
list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
if (!strcmp(name, temp_pwrdm->name)) {
pwrdm = temp_pwrdm;
break;
}
}
return pwrdm;
}
/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */
static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
struct pwrdm_dep *deps)
{
struct pwrdm_dep *pd;
if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
return ERR_PTR(-EINVAL);
for (pd = deps; pd; pd++) {
if (!omap_chip_is(pd->omap_chip))
continue;
if (!pd->pwrdm && pd->pwrdm_name)
pd->pwrdm = pwrdm_lookup(pd->pwrdm_name);
if (pd->pwrdm == pwrdm)
break;
}
if (!pd)
return ERR_PTR(-ENOENT);
return pd->pwrdm;
}
/* Public functions */
/**
* pwrdm_init - set up the powerdomain layer
*
* Loop through the list of powerdomains, registering all that are
* available on the current CPU. If pwrdm_list is supplied and not
* null, all of the referenced powerdomains will be registered. No
* return value.
*/
void pwrdm_init(struct powerdomain **pwrdm_list)
{
struct powerdomain **p = NULL;
if (pwrdm_list)
for (p = pwrdm_list; *p; p++)
pwrdm_register(*p);
}
/**
* pwrdm_register - register a powerdomain
* @pwrdm: struct powerdomain * to register
*
* Adds a powerdomain to the internal powerdomain list. Returns
* -EINVAL if given a null pointer, -EEXIST if a powerdomain is
* already registered by the provided name, or 0 upon success.
*/
int pwrdm_register(struct powerdomain *pwrdm)
{
unsigned long flags;
int ret = -EINVAL;
if (!pwrdm)
return -EINVAL;
if (!omap_chip_is(pwrdm->omap_chip))
return -EINVAL;
write_lock_irqsave(&pwrdm_rwlock, flags);
if (_pwrdm_lookup(pwrdm->name)) {
ret = -EEXIST;
goto pr_unlock;
}
list_add(&pwrdm->node, &pwrdm_list);
pr_debug("powerdomain: registered %s\n", pwrdm->name);
ret = 0;
pr_unlock:
write_unlock_irqrestore(&pwrdm_rwlock, flags);
return ret;
}
/**
* pwrdm_unregister - unregister a powerdomain
* @pwrdm: struct powerdomain * to unregister
*
* Removes a powerdomain from the internal powerdomain list. Returns
* -EINVAL if pwrdm argument is NULL.
*/
int pwrdm_unregister(struct powerdomain *pwrdm)
{
unsigned long flags;
if (!pwrdm)
return -EINVAL;
write_lock_irqsave(&pwrdm_rwlock, flags);
list_del(&pwrdm->node);
write_unlock_irqrestore(&pwrdm_rwlock, flags);
pr_debug("powerdomain: unregistered %s\n", pwrdm->name);
return 0;
}
/**
* pwrdm_lookup - look up a powerdomain by name, return a pointer
* @name: name of powerdomain
*
* Find a registered powerdomain by its name. Returns a pointer to the
* struct powerdomain if found, or NULL otherwise.
*/
struct powerdomain *pwrdm_lookup(const char *name)
{
struct powerdomain *pwrdm;
unsigned long flags;
if (!name)
return NULL;
read_lock_irqsave(&pwrdm_rwlock, flags);
pwrdm = _pwrdm_lookup(name);
read_unlock_irqrestore(&pwrdm_rwlock, flags);
return pwrdm;
}
/**
* pwrdm_for_each - call function on each registered clockdomain
* @fn: callback function *
*
* Call the supplied function for each registered powerdomain. The
* callback function can return anything but 0 to bail out early from
* the iterator. The callback function is called with the pwrdm_rwlock
* held for reading, so no powerdomain structure manipulation
* functions should be called from the callback, although hardware
* powerdomain control functions are fine. Returns the last return
* value of the callback function, which should be 0 for success or
* anything else to indicate failure; or -EINVAL if the function
* pointer is null.
*/
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
{
struct powerdomain *temp_pwrdm;
unsigned long flags;
int ret = 0;
if (!fn)
return -EINVAL;
read_lock_irqsave(&pwrdm_rwlock, flags);
list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
ret = (*fn)(temp_pwrdm);
if (ret)
break;
}
read_unlock_irqrestore(&pwrdm_rwlock, flags);
return ret;
}
/**
* pwrdm_add_clkdm - add a clockdomain to a powerdomain
* @pwrdm: struct powerdomain * to add the clockdomain to
* @clkdm: struct clockdomain * to associate with a powerdomain
*
* Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This
* enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if
* presented with invalid pointers; -ENOMEM if memory could not be allocated;
* or 0 upon success.
*/
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
{
unsigned long flags;
int i;
int ret = -EINVAL;
if (!pwrdm || !clkdm)
return -EINVAL;
pr_debug("powerdomain: associating clockdomain %s with powerdomain "
"%s\n", clkdm->name, pwrdm->name);
write_lock_irqsave(&pwrdm_rwlock, flags);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
if (!pwrdm->pwrdm_clkdms[i])
break;
#ifdef DEBUG
if (pwrdm->pwrdm_clkdms[i] == clkdm) {
ret = -EINVAL;
goto pac_exit;
}
#endif
}
if (i == PWRDM_MAX_CLKDMS) {
pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
"pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
WARN_ON(1);
ret = -ENOMEM;
goto pac_exit;
}
pwrdm->pwrdm_clkdms[i] = clkdm;
ret = 0;
pac_exit:
write_unlock_irqrestore(&pwrdm_rwlock, flags);
return ret;
}
/**
* pwrdm_del_clkdm - remove a clockdomain from a powerdomain
* @pwrdm: struct powerdomain * to add the clockdomain to
* @clkdm: struct clockdomain * to associate with a powerdomain
*
* Dissociate the clockdomain 'clkdm' from the powerdomain
* 'pwrdm'. Returns -EINVAL if presented with invalid pointers;
* -ENOENT if the clkdm was not associated with the powerdomain, or 0
* upon success.
*/
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
{
unsigned long flags;
int ret = -EINVAL;
int i;
if (!pwrdm || !clkdm)
return -EINVAL;
pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
"%s\n", clkdm->name, pwrdm->name);
write_lock_irqsave(&pwrdm_rwlock, flags);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
if (i == PWRDM_MAX_CLKDMS) {
pr_debug("powerdomain: clkdm %s not associated with pwrdm "
"%s ?!\n", clkdm->name, pwrdm->name);
ret = -ENOENT;
goto pdc_exit;
}
pwrdm->pwrdm_clkdms[i] = NULL;
ret = 0;
pdc_exit:
write_unlock_irqrestore(&pwrdm_rwlock, flags);
return ret;
}
/**
* pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
* @pwrdm: struct powerdomain * to iterate over
* @fn: callback function *
*
* Call the supplied function for each clockdomain in the powerdomain
* 'pwrdm'. The callback function can return anything but 0 to bail
* out early from the iterator. The callback function is called with
* the pwrdm_rwlock held for reading, so no powerdomain structure
* manipulation functions should be called from the callback, although
* hardware powerdomain control functions are fine. Returns -EINVAL
* if presented with invalid pointers; or passes along the last return
* value of the callback function, which should be 0 for success or
* anything else to indicate failure.
*/
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
int (*fn)(struct powerdomain *pwrdm,
struct clockdomain *clkdm))
{
unsigned long flags;
int ret = 0;
int i;
if (!fn)
return -EINVAL;
read_lock_irqsave(&pwrdm_rwlock, flags);
for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
read_unlock_irqrestore(&pwrdm_rwlock, flags);
return ret;
}
/**
* pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1
* @pwrdm1: wake this struct powerdomain * up (dependent)
* @pwrdm2: when this struct powerdomain * wakes up (source)
*
* When the powerdomain represented by pwrdm2 wakes up (due to an
* interrupt), wake up pwrdm1. Implemented in hardware on the OMAP,
* this feature is designed to reduce wakeup latency of the dependent
* powerdomain. Returns -EINVAL if presented with invalid powerdomain
* pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
* 0 upon success.
*/
int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
return IS_ERR(p);
}
pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
pwrdm1->name, pwrdm2->name);
prm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
pwrdm1->prcm_offs, PM_WKDEP);
return 0;
}
/**
* pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1
* @pwrdm1: wake this struct powerdomain * up (dependent)
* @pwrdm2: when this struct powerdomain * wakes up (source)
*
* Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2
* wakes up. Returns -EINVAL if presented with invalid powerdomain
* pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
* 0 upon success.
*/
int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
return IS_ERR(p);
}
pr_debug("powerdomain: hardware will no longer wake up %s after %s "
"wakes up\n", pwrdm1->name, pwrdm2->name);
prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
pwrdm1->prcm_offs, PM_WKDEP);
return 0;
}
/**
* pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1
* @pwrdm1: wake this struct powerdomain * up (dependent)
* @pwrdm2: when this struct powerdomain * wakes up (source)
*
* Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be
* awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL
* if either powerdomain pointer is invalid; or -ENOENT if the hardware
* is incapable.
*
* REVISIT: Currently this function only represents software-controllable
* wakeup dependencies. Wakeup dependencies fixed in hardware are not
* yet handled here.
*/
int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
return IS_ERR(p);
}
return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
(1 << pwrdm2->dep_bit));
}
/**
* pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1
* @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
* @pwrdm2: when this struct powerdomain * is active (source)
*
* Prevent pwrdm1 from automatically going inactive (and then to
* retention or off) if pwrdm2 is still active. Returns -EINVAL if
* presented with invalid powerdomain pointers or called on a machine
* that does not support software-configurable hardware sleep dependencies,
* -ENOENT if the specified dependency cannot be set in hardware, or
* 0 upon success.
*/
int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
if (!cpu_is_omap34xx())
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", pwrdm1->name,
pwrdm2->name);
return IS_ERR(p);
}
pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
pwrdm1->name, pwrdm2->name);
cm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
return 0;
}
/**
* pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1
* @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
* @pwrdm2: when this struct powerdomain * is active (source)
*
* Allow pwrdm1 to automatically go inactive (and then to retention or
* off), independent of the activity state of pwrdm2. Returns -EINVAL
* if presented with invalid powerdomain pointers or called on a machine
* that does not support software-configurable hardware sleep dependencies,
* -ENOENT if the specified dependency cannot be cleared in hardware, or
* 0 upon success.
*/
int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
if (!cpu_is_omap34xx())
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", pwrdm1->name,
pwrdm2->name);
return IS_ERR(p);
}
pr_debug("powerdomain: will no longer prevent %s from sleeping if "
"%s is active\n", pwrdm1->name, pwrdm2->name);
cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
return 0;
}
/**
* pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1
* @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
* @pwrdm2: when this struct powerdomain * is active (source)
*
* Return 1 if a hardware sleep dependency exists wherein pwrdm1 will
* not be allowed to automatically go inactive if pwrdm2 is active;
* 0 if pwrdm1's automatic power state inactivity transition is independent
* of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called
* on a machine that does not support software-configurable hardware sleep
* dependencies; or -ENOENT if the hardware is incapable.
*
* REVISIT: Currently this function only represents software-controllable
* sleep dependencies. Sleep dependencies fixed in hardware are not
* yet handled here.
*/
int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
{
struct powerdomain *p;
if (!pwrdm1)
return -EINVAL;
if (!cpu_is_omap34xx())
return -EINVAL;
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
if (IS_ERR(p)) {
pr_debug("powerdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", pwrdm1->name,
pwrdm2->name);
return IS_ERR(p);
}
return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
(1 << pwrdm2->dep_bit));
}
/**
* pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
* @pwrdm: struct powerdomain *
*
* Return the number of controllable memory banks in powerdomain pwrdm,
* starting with 1. Returns -EINVAL if the powerdomain pointer is null.
*/
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
return pwrdm->banks;
}
/**
* pwrdm_set_next_pwrst - set next powerdomain power state
* @pwrdm: struct powerdomain * to set
* @pwrst: one of the PWRDM_POWER_* macros
*
* Set the powerdomain pwrdm's next power state to pwrst. The powerdomain
* may not enter this state immediately if the preconditions for this state
* have not been satisfied. Returns -EINVAL if the powerdomain pointer is
* null or if the power state is invalid for the powerdomin, or returns 0
* upon success.
*/
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
if (!pwrdm)
return -EINVAL;
if (!(pwrdm->pwrsts & (1 << pwrst)))
return -EINVAL;
pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
pwrdm->name, pwrst);
prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_read_next_pwrst - get next powerdomain power state
* @pwrdm: struct powerdomain * to get power state
*
* Return the powerdomain pwrdm's next power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the next power state
* upon success.
*/
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
}
/**
* pwrdm_read_pwrst - get current powerdomain power state
* @pwrdm: struct powerdomain * to get power state
*
* Return the powerdomain pwrdm's current power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the current power state
* upon success.
*/
int pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
OMAP_POWERSTATEST_MASK);
}
/**
* pwrdm_read_prev_pwrst - get previous powerdomain power state
* @pwrdm: struct powerdomain * to get previous power state
*
* Return the powerdomain pwrdm's previous power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the previous power state
* upon success.
*/
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
OMAP3430_LASTPOWERSTATEENTERED_MASK);
}
/**
* pwrdm_set_logic_retst - set powerdomain logic power state upon retention
* @pwrdm: struct powerdomain * to set
* @pwrst: one of the PWRDM_POWER_* macros
*
* Set the next power state that the logic portion of the powerdomain
* pwrdm will enter when the powerdomain enters retention. This will
* be either RETENTION or OFF, if supported. Returns -EINVAL if the
* powerdomain pointer is null or the target power state is not not
* supported, or returns 0 upon success.
*/
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
{
if (!pwrdm)
return -EINVAL;
if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
return -EINVAL;
pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
pwrdm->name, pwrst);
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
(pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
pwrdm->prcm_offs, PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_set_mem_onst - set memory power state while powerdomain ON
* @pwrdm: struct powerdomain * to set
* @bank: memory bank number to set (0-3)
* @pwrst: one of the PWRDM_POWER_* macros
*
* Set the next power state that memory bank x of the powerdomain
* pwrdm will enter when the powerdomain enters the ON state. Bank
* will be a number from 0 to 3, and represents different types of
* memory, depending on the powerdomain. Returns -EINVAL if the
* powerdomain pointer is null or the target power state is not not
* supported for this memory bank, -EEXIST if the target memory bank
* does not exist or is not controllable, or returns 0 upon success.
*/
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
{
u32 m;
if (!pwrdm)
return -EINVAL;
if (pwrdm->banks < (bank + 1))
return -EEXIST;
if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
return -EINVAL;
pr_debug("powerdomain: setting next memory powerstate for domain %s "
"bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
switch (bank) {
case 0:
m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK;
break;
case 1:
m = OMAP3430_L1FLATMEMONSTATE_MASK;
break;
case 2:
m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK;
break;
case 3:
m = OMAP3430_L2FLATMEMONSTATE_MASK;
break;
default:
WARN_ON(1); /* should never happen */
return -EEXIST;
}
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
pwrdm->prcm_offs, PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_set_mem_retst - set memory power state while powerdomain in RET
* @pwrdm: struct powerdomain * to set
* @bank: memory bank number to set (0-3)
* @pwrst: one of the PWRDM_POWER_* macros
*
* Set the next power state that memory bank x of the powerdomain
* pwrdm will enter when the powerdomain enters the RETENTION state.
* Bank will be a number from 0 to 3, and represents different types
* of memory, depending on the powerdomain. pwrst will be either
* RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain
* pointer is null or the target power state is not not supported for
* this memory bank, -EEXIST if the target memory bank does not exist
* or is not controllable, or returns 0 upon success.
*/
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
{
u32 m;
if (!pwrdm)
return -EINVAL;
if (pwrdm->banks < (bank + 1))
return -EEXIST;
if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
return -EINVAL;
pr_debug("powerdomain: setting next memory powerstate for domain %s "
"bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
switch (bank) {
case 0:
m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
break;
case 1:
m = OMAP3430_L1FLATMEMRETSTATE;
break;
case 2:
m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
break;
case 3:
m = OMAP3430_L2FLATMEMRETSTATE;
break;
default:
WARN_ON(1); /* should never happen */
return -EEXIST;
}
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
* @pwrdm: struct powerdomain * to get current logic retention power state
*
* Return the current power state that the logic portion of
* powerdomain pwrdm will enter
* Returns -EINVAL if the powerdomain pointer is null or returns the
* current logic retention power state upon success.
*/
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
OMAP3430_LOGICSTATEST);
}
/**
* pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
* @pwrdm: struct powerdomain * to get previous logic power state
*
* Return the powerdomain pwrdm's logic power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the previous logic
* power state upon success.
*/
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
OMAP3430_LASTLOGICSTATEENTERED);
}
/**
* pwrdm_read_mem_pwrst - get current memory bank power state
* @pwrdm: struct powerdomain * to get current memory bank power state
* @bank: memory bank number (0-3)
*
* Return the powerdomain pwrdm's current memory power state for bank
* x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
* the target memory bank does not exist or is not controllable, or
* returns the current memory power state upon success.
*/
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
{
u32 m;
if (!pwrdm)
return -EINVAL;
if (pwrdm->banks < (bank + 1))
return -EEXIST;
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
switch (bank) {
case 0:
m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK;
break;
case 1:
m = OMAP3430_L1FLATMEMSTATEST_MASK;
break;
case 2:
m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK;
break;
case 3:
m = OMAP3430_L2FLATMEMSTATEST_MASK;
break;
default:
WARN_ON(1); /* should never happen */
return -EEXIST;
}
return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);
}
/**
* pwrdm_read_prev_mem_pwrst - get previous memory bank power state
* @pwrdm: struct powerdomain * to get previous memory bank power state
* @bank: memory bank number (0-3)
*
* Return the powerdomain pwrdm's previous memory power state for bank
* x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
* the target memory bank does not exist or is not controllable, or
* returns the previous memory power state upon success.
*/
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
{
u32 m;
if (!pwrdm)
return -EINVAL;
if (pwrdm->banks < (bank + 1))
return -EEXIST;
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
* but the type of value returned is the same for each
* powerdomain.
*/
switch (bank) {
case 0:
m = OMAP3430_LASTMEM1STATEENTERED_MASK;
break;
case 1:
m = OMAP3430_LASTMEM2STATEENTERED_MASK;
break;
case 2:
m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
break;
case 3:
m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
break;
default:
WARN_ON(1); /* should never happen */
return -EEXIST;
}
return prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_PM_PREPWSTST, m);
}
/**
* pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
* @pwrdm: struct powerdomain * to clear
*
* Clear the powerdomain's previous power state register. Clears the
* entire register, including logic and memory bank previous power states.
* Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon
* success.
*/
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
/*
* XXX should get the powerdomain's current state here;
* warn & fail if it is not ON.
*/
pr_debug("powerdomain: clearing previous power state reg for %s\n",
pwrdm->name);
prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
return 0;
}
/**
* pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
* @pwrdm: struct powerdomain *
*
* Enable automatic context save-and-restore upon power state change
* for some devices in a powerdomain. Warning: this only affects a
* subset of devices in a powerdomain; check the TRM closely. Returns
* -EINVAL if the powerdomain pointer is null or if the powerdomain
* does not support automatic save-and-restore, or returns 0 upon
* success.
*/
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return -EINVAL;
pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
pwrdm->name);
prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
pwrdm->prcm_offs, PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
* @pwrdm: struct powerdomain *
*
* Disable automatic context save-and-restore upon power state change
* for some devices in a powerdomain. Warning: this only affects a
* subset of devices in a powerdomain; check the TRM closely. Returns
* -EINVAL if the powerdomain pointer is null or if the powerdomain
* does not support automatic save-and-restore, or returns 0 upon
* success.
*/
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return -EINVAL;
pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
pwrdm->name);
prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
pwrdm->prcm_offs, PM_PWSTCTRL);
return 0;
}
/**
* pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
* @pwrdm: struct powerdomain *
*
* Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
* for some devices, or 0 if it does not.
*/
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
{
return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
}
/**
* pwrdm_wait_transition - wait for powerdomain power transition to finish
* @pwrdm: struct powerdomain * to wait for
*
* If the powerdomain pwrdm is in the process of a state transition,
* spin until it completes the power transition, or until an iteration
* bailout value is reached. Returns -EINVAL if the powerdomain
* pointer is null, -EAGAIN if the bailout value was reached, or
* returns 0 upon success.
*/
int pwrdm_wait_transition(struct powerdomain *pwrdm)
{
u32 c = 0;
if (!pwrdm)
return -EINVAL;
/*
* REVISIT: pwrdm_wait_transition() may be better implemented
* via a callback and a periodic timer check -- how long do we expect
* powerdomain transitions to take?
*/
/* XXX Is this udelay() value meaningful? */
while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &
OMAP_INTRANSITION) &&
(c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1);
if (c >= PWRDM_TRANSITION_BAILOUT) {
printk(KERN_ERR "powerdomain: waited too long for "
"powerdomain %s to complete transition\n", pwrdm->name);
return -EAGAIN;
}
pr_debug("powerdomain: completed transition in %d loops\n", c);
return 0;
}
arch/arm/mach-omap2/powerdomains.h 0 → 100644
View file @ fd9470ce
/*
* OMAP2/3 common powerdomain definitions
*
* Copyright (C) 2007-8 Texas Instruments, Inc.
* Copyright (C) 2007-8 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
/*
* This file contains all of the powerdomains that have some element
* of software control for the OMAP24xx and OMAP34XX chips.
*
* A few notes:
*
* This is not an exhaustive listing of powerdomains on the chips; only
* powerdomains that can be controlled in software.
*
* A useful validation rule for struct powerdomain:
* Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
* must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
* just software-controllable dependencies. Non-software-controllable
* dependencies do exist, but they are not encoded below (yet).
*
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
*
*/
/*
* The names for the DSP/IVA2 powerdomains are confusing.
*
* Most OMAP chips have an on-board DSP.
*
* On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
* powerdomain is called the "DSP power domain." On the 2430, the
* on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
* powerdomain is still called the "DSP power domain." On the 3430,
* the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
* its powerdomain is now called the "IVA2 power domain."
*
* The 2420 also has something called the IVA, which is a separate ARM
* core, and has nothing to do with the DSP/IVA2.
*
* Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
* address offset is different between the C55 and C64 DSPs.
*
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
*/
/*
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
* sanity check?
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
#include <mach/powerdomain.h>
#include "prcm-common.h"
#include "prm.h"
#include "cm.h"
/* OMAP2/3-common powerdomains and wakeup dependencies */
/*
* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
*/
static struct pwrdm_dep gfx_sgx_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* 3430: CM_SLEEPDEP_CAM: MPU
* 3430ES1: CM_SLEEPDEP_GFX: MPU
* 3430ES2: CM_SLEEPDEP_SGX: MPU
*/
static struct pwrdm_dep cam_gfx_sleepdeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
#include "powerdomains24xx.h"
#include "powerdomains34xx.h"
/*
* OMAP2/3 common powerdomains
*/
/*
* The GFX powerdomain is not present on 3430ES2, but currently we do not
* have a macro to filter it out at compile-time.
*/
static struct powerdomain gfx_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = GFX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1),
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = cam_gfx_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain wkup_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = WKUP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
.dep_bit = OMAP_EN_WKUP_SHIFT,
};
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap[] __initdata = {
&gfx_pwrdm,
&wkup_pwrdm,
#ifdef CONFIG_ARCH_OMAP24XX
&dsp_pwrdm,
&mpu_24xx_pwrdm,
&core_24xx_pwrdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
&mdm_pwrdm,
#endif
#ifdef CONFIG_ARCH_OMAP34XX
&iva2_pwrdm,
&mpu_34xx_pwrdm,
&neon_pwrdm,
&core_34xx_pwrdm,
&cam_pwrdm,
&dss_pwrdm,
&per_pwrdm,
&emu_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
#endif
NULL
};
#endif
arch/arm/mach-omap2/powerdomains24xx.h 0 → 100644
View file @ fd9470ce
/*
* OMAP24XX powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
/*
* N.B. If powerdomains are added or removed from this file, update
* the array in mach-omap2/powerdomains.h.
*/
#include <mach/powerdomain.h>
#include "prcm-common.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
/* 24XX powerdomains and dependencies */
#ifdef CONFIG_ARCH_OMAP24XX
/* Wakeup dependency source arrays */
/*
* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
* 2430 PM_WKDEP_MDM: same as above
*/
static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{ NULL },
};
/*
* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
* 2430 adds MDM
*/
static struct pwrdm_dep mpu_24xx_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "dsp_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "mdm_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
},
{ NULL },
};
/*
* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
* 2430 adds MDM
*/
static struct pwrdm_dep core_24xx_wkdeps[] = {
{
.pwrdm_name = "dsp_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "gfx_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
},
{
.pwrdm_name = "mdm_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
},
{ NULL },
};
/* Powerdomains */
static struct powerdomain dsp_pwrdm = {
.name = "dsp_pwrdm",
.prcm_offs = OMAP24XX_DSP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
.wkdep_srcs = dsp_mdm_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET,
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON,
},
};
static struct powerdomain mpu_24xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.dep_bit = OMAP24XX_EN_MPU_SHIFT,
.wkdep_srcs = mpu_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET,
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON,
},
};
static struct powerdomain core_24xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.wkdep_srcs = core_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
[2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
[2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
},
};
#endif /* CONFIG_ARCH_OMAP24XX */
/*
* 2430-specific powerdomains
*/
#ifdef CONFIG_ARCH_OMAP2430
/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
/* Another case of bit name collisions between several registers: EN_MDM */
static struct powerdomain mdm_pwrdm = {
.name = "mdm_pwrdm",
.prcm_offs = OMAP2430_MDM_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
.wkdep_srcs = dsp_mdm_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
#endif /* CONFIG_ARCH_OMAP2430 */
#endif
arch/arm/mach-omap2/powerdomains34xx.h 0 → 100644
View file @ fd9470ce
/*
* OMAP34XX powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
/*
* N.B. If powerdomains are added or removed from this file, update
* the array in mach-omap2/powerdomains.h.
*/
#include <mach/powerdomain.h>
#include "prcm-common.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"
/*
* 34XX-specific powerdomains, dependencies
*/
#ifdef CONFIG_ARCH_OMAP34XX
/*
* 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
* (USBHOST is ES2 only)
*/
static struct pwrdm_dep per_usbhost_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
*/
static struct pwrdm_dep mpu_34xx_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "dss_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "per_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
*/
static struct pwrdm_dep iva2_wkdeps[] = {
{
.pwrdm_name = "core_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "dss_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "per_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
static struct pwrdm_dep cam_dss_wkdeps[] = {
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "wkup_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* 3430: PM_WKDEP_NEON: MPU */
static struct pwrdm_dep neon_wkdeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
/*
* 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
*/
static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
{
.pwrdm_name = "mpu_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
.pwrdm_name = "iva2_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{ NULL },
};
/*
* Powerdomains
*/
static struct powerdomain iva2_pwrdm = {
.name = "iva2_pwrdm",
.prcm_offs = OMAP3430_IVA2_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
.wkdep_srcs = iva2_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
[1] = PWRSTS_OFF_RET,
[2] = PWRSTS_OFF_RET,
[3] = PWRSTS_OFF_RET,
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON,
[1] = PWRDM_POWER_ON,
[2] = PWRSTS_OFF_ON,
[3] = PWRDM_POWER_ON,
},
};
static struct powerdomain mpu_34xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.dep_bit = OMAP3430_EN_MPU_SHIFT,
.wkdep_srcs = mpu_34xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_ON,
},
};
/* No wkdeps or sleepdeps for 34xx core apparently */
static struct powerdomain core_34xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
},
};
/* Another case of bit name collisions between several registers: EN_DSS */
static struct powerdomain dss_pwrdm = {
.name = "dss_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_DSS_MOD,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
.wkdep_srcs = cam_dss_wkdeps,
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain sgx_pwrdm = {
.name = "sgx_pwrdm",
.prcm_offs = OMAP3430ES2_SGX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = cam_gfx_sleepdeps,
/* XXX This is accurate for 3430 SGX, but what about GFX? */
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain cam_pwrdm = {
.name = "cam_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_CAM_MOD,
.wkdep_srcs = cam_dss_wkdeps,
.sleepdep_srcs = cam_gfx_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain per_pwrdm = {
.name = "per_pwrdm",
.prcm_offs = OMAP3430_PER_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.dep_bit = OMAP3430_EN_PER_SHIFT,
.wkdep_srcs = per_usbhost_wkdeps,
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
static struct powerdomain emu_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = OMAP3430_EMU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static struct powerdomain neon_pwrdm = {
.name = "neon_pwrdm",
.prcm_offs = OMAP3430_NEON_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.wkdep_srcs = neon_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
};
static struct powerdomain usbhost_pwrdm = {
.name = "usbhost_pwrdm",
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
.wkdep_srcs = per_usbhost_wkdeps,
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
},
};
#endif /* CONFIG_ARCH_OMAP34XX */
#endif
arch/arm/mach-omap2/prcm-common.h
View file @ fd9470ce
...@@ -312,7 +312,8 @@ ...@@ -312,7 +312,8 @@
#define OMAP3430_ST_GPT2 (1 << 3) #define OMAP3430_ST_GPT2 (1 << 3)
/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
#define OMAP3430_EN_CORE (1 << 0) #define OMAP3430_EN_CORE_SHIFT 0
#define OMAP3430_EN_CORE_MASK (1 << 0)
#endif #endif
arch/arm/mach-omap2/prm-regbits-24xx.h
View file @ fd9470ce
...@@ -29,8 +29,10 @@ ...@@ -29,8 +29,10 @@
#define OMAP24XX_WKUP1_EN (1 << 0) #define OMAP24XX_WKUP1_EN (1 << 0)
/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
#define OMAP24XX_EN_MPU (1 << 1) #define OMAP24XX_EN_MPU_SHIFT 1
#define OMAP24XX_EN_CORE (1 << 0) #define OMAP24XX_EN_MPU_MASK (1 << 1)
#define OMAP24XX_EN_CORE_SHIFT 0
#define OMAP24XX_EN_CORE_MASK (1 << 0)
/* /*
* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
...@@ -140,8 +142,10 @@ ...@@ -140,8 +142,10 @@
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
/* PM_WKDEP_MPU specific bits */ /* PM_WKDEP_MPU specific bits */
#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
/* PM_EVGENCTRL_MPU specific bits */ /* PM_EVGENCTRL_MPU specific bits */
......
arch/arm/mach-omap2/prm-regbits-34xx.h
View file @ fd9470ce
...@@ -68,7 +68,8 @@ ...@@ -68,7 +68,8 @@
#define OMAP3430_VPINIDLE (1 << 0) #define OMAP3430_VPINIDLE (1 << 0)
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
#define OMAP3430_EN_PER (1 << 7) #define OMAP3430_EN_PER_SHIFT 7
#define OMAP3430_EN_PER_MASK (1 << 7)
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
#define OMAP3430_MEMORYCHANGE (1 << 3) #define OMAP3430_MEMORYCHANGE (1 << 3)
...@@ -77,7 +78,7 @@ ...@@ -77,7 +78,7 @@
#define OMAP3430_LOGICSTATEST (1 << 2) #define OMAP3430_LOGICSTATEST (1 << 2)
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
/* /*
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
...@@ -278,8 +279,10 @@ ...@@ -278,8 +279,10 @@
#define OMAP3430_EMULATION_MPU_RST (1 << 11) #define OMAP3430_EMULATION_MPU_RST (1 << 11)
/* PM_WKDEP_MPU specific bits */ /* PM_WKDEP_MPU specific bits */
#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
/* PM_EVGENCTRL_MPU */ /* PM_EVGENCTRL_MPU */
#define OMAP3430_OFFLOADMODE_SHIFT 3 #define OMAP3430_OFFLOADMODE_SHIFT 3
......
arch/arm/mach-omap2/prm.h
View file @ fd9470ce
...@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) ...@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
* PM_WKDEP_PER * PM_WKDEP_PER
*/ */
#define OMAP_EN_WKUP (1 << 4) #define OMAP_EN_WKUP_SHIFT 4
#define OMAP_EN_WKUP_MASK (1 << 4)
/* /*
* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
......
arch/arm/plat-omap/Kconfig
View file @ fd9470ce
...@@ -29,6 +29,30 @@ config OMAP_DEBUG_LEDS ...@@ -29,6 +29,30 @@ config OMAP_DEBUG_LEDS
depends on OMAP_DEBUG_DEVICES depends on OMAP_DEBUG_DEVICES
default y if LEDS || LEDS_OMAP_DEBUG default y if LEDS || LEDS_OMAP_DEBUG
config OMAP_DEBUG_POWERDOMAIN
bool "Emit debug messages from powerdomain layer"
depends on ARCH_OMAP2 || ARCH_OMAP3
default n
help
Say Y here if you want to compile in powerdomain layer
debugging messages for OMAP2/3. These messages can
provide more detail as to why some powerdomain calls
may be failing, and will also emit a descriptive message
for every powerdomain register write. However, the
extra detail costs some memory.
config OMAP_DEBUG_CLOCKDOMAIN
bool "Emit debug messages from clockdomain layer"
depends on ARCH_OMAP2 || ARCH_OMAP3
default n
help
Say Y here if you want to compile in clockdomain layer
debugging messages for OMAP2/3. These messages can
provide more detail as to why some clockdomain calls
may be failing, and will also emit a descriptive message
for every clockdomain register write. However, the
extra detail costs some memory.
config OMAP_RESET_CLOCKS config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot" bool "Reset unused clocks during boot"
depends on ARCH_OMAP depends on ARCH_OMAP
......
arch/arm/plat-omap/include/mach/clock.h
View file @ fd9470ce
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
struct module; struct module;
struct clk; struct clk;
struct clockdomain;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
...@@ -79,6 +80,8 @@ struct clk { ...@@ -79,6 +80,8 @@ struct clk {
u32 clksel_mask; u32 clksel_mask;
const struct clksel *clksel; const struct clksel *clksel;
struct dpll_data *dpll_data; struct dpll_data *dpll_data;
const char *clkdm_name;
struct clockdomain *clkdm;
#else #else
__u8 rate_offset; __u8 rate_offset;
__u8 src_offset; __u8 src_offset;
......
arch/arm/plat-omap/include/mach/clockdomain.h 0 → 100644
View file @ fd9470ce
/*
* linux/include/asm-arm/arch-omap/clockdomain.h
*
* OMAP2/3 clockdomain framework functions
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation
*
* Written by Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
#include <mach/powerdomain.h>
#include <mach/clock.h>
#include <mach/cpu.h>
/* Clockdomain capability flags */
#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
/*
* struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
* and sleepdeps added when a powerdomain should stay active in hwsup mode;
* and conversely, removed when the powerdomain should be allowed to go
* inactive in hwsup mode.
*/
struct clkdm_pwrdm_autodep {
/* Name of the powerdomain to add a wkdep/sleepdep on */
const char *pwrdm_name;
/* Powerdomain pointer (looked up at clkdm_init() time) */
struct powerdomain *pwrdm;
/* OMAP chip types that this clockdomain dep is valid on */
const struct omap_chip_id omap_chip;
};
struct clockdomain {
/* Clockdomain name */
const char *name;
/* Powerdomain enclosing this clockdomain */
const char *pwrdm_name;
/* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
const u16 clktrctrl_mask;
/* Clockdomain capability flags */
const u8 flags;
/* OMAP chip types that this clockdomain is valid on */
const struct omap_chip_id omap_chip;
/* Usecount tracking */
atomic_t usecount;
/* Powerdomain pointer assigned at clkdm_register() */
struct powerdomain *pwrdm;
struct list_head node;
};
void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
int clkdm_register(struct clockdomain *clkdm);
int clkdm_unregister(struct clockdomain *clkdm);
struct clockdomain *clkdm_lookup(const char *name);
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
int omap2_clkdm_wakeup(struct clockdomain *clkdm);
int omap2_clkdm_sleep(struct clockdomain *clkdm);
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
#endif
arch/arm/plat-omap/include/mach/powerdomain.h 0 → 100644
View file @ fd9470ce
/*
* OMAP2/3 powerdomain control
*
* Copyright (C) 2007-8 Texas Instruments, Inc.
* Copyright (C) 2007-8 Nokia Corporation
*
* Written by Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
#include <linux/types.h>
#include <linux/list.h>
#include <asm/atomic.h>
#include <mach/cpu.h>
/* Powerdomain basic power states */
#define PWRDM_POWER_OFF 0x0
#define PWRDM_POWER_RET 0x1
#define PWRDM_POWER_INACTIVE 0x2
#define PWRDM_POWER_ON 0x3
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_ON))
#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_RET))
#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
/* Powerdomain flags */
#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
/*
* Number of memory banks that are power-controllable. On OMAP3430, the
* maximum is 4.
*/
#define PWRDM_MAX_MEM_BANKS 4
/*
* Maximum number of clockdomains that can be associated with a powerdomain.
* CORE powerdomain is probably the worst case.
*/
#define PWRDM_MAX_CLKDMS 3
/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 100000
struct clockdomain;
struct powerdomain;
/* Encodes dependencies between powerdomains - statically defined */
struct pwrdm_dep {
/* Powerdomain name */
const char *pwrdm_name;
/* Powerdomain pointer - resolved by the powerdomain code */
struct powerdomain *pwrdm;
/* Flags to mark OMAP chip restrictions, etc. */
const struct omap_chip_id omap_chip;
};
struct powerdomain {
/* Powerdomain name */
const char *name;
/* the address offset from CM_BASE/PRM_BASE */
const s16 prcm_offs;
/* Used to represent the OMAP chip types containing this pwrdm */
const struct omap_chip_id omap_chip;
/* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
const u8 dep_bit;
/* Powerdomains that can be told to wake this powerdomain up */
struct pwrdm_dep *wkdep_srcs;
/* Powerdomains that can be told to keep this pwrdm from inactivity */
struct pwrdm_dep *sleepdep_srcs;
/* Possible powerdomain power states */
const u8 pwrsts;
/* Possible logic power states when pwrdm in RETENTION */
const u8 pwrsts_logic_ret;
/* Powerdomain flags */
const u8 flags;
/* Number of software-controllable memory banks in this powerdomain */
const u8 banks;
/* Possible memory bank pwrstates when pwrdm in RETENTION */
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
/* Possible memory bank pwrstates when pwrdm is ON */
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
/* Clockdomains in this powerdomain */
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
struct list_head node;
};
void pwrdm_init(struct powerdomain **pwrdm_list);
int pwrdm_register(struct powerdomain *pwrdm);
int pwrdm_unregister(struct powerdomain *pwrdm);
struct powerdomain *pwrdm_lookup(const char *name);
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
int (*fn)(struct powerdomain *pwrdm,
struct clockdomain *clkdm));
int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
#endif
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