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Commit fdb0a1a6 authored by Russell King's avatar Russell King Committed by Russell King
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Merge branch 'next-merged' of git://aeryn.fluff.org.uk/bjdooks/linux into devel

parents fc0b7a20 7bb56d01
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Showing with 10761 additions and 1189 deletions
arch/arm/Kconfig
View file @ fdb0a1a6
......@@ -518,6 +518,13 @@ config ARCH_S3C2410
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
the Samsung SMDK2410 development board (and derivatives).
config ARCH_S3C64XX
bool "Samsung S3C64XX"
select GENERIC_GPIO
select HAVE_CLK
help
Samsung S3C64XX series based systems
config ARCH_SHARK
bool "Shark"
select CPU_SA110
......@@ -621,6 +628,7 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
if ARCH_S3C2410
......@@ -632,6 +640,11 @@ source "arch/arm/mach-s3c2442/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig"
endif
if ARCH_S3C64XX
source "arch/arm/mach-s3c6400/Kconfig"
source "arch/arm/mach-s3c6410/Kconfig"
endif
source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-imx/Kconfig"
......
arch/arm/Makefile
View file @ fdb0a1a6
......@@ -121,7 +121,10 @@ endif
machine-$(CONFIG_ARCH_OMAP3) := omap2
plat-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_IMX) := imx
......
arch/arm/common/vic.c
View file @ fdb0a1a6
......@@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
/*
* Make sure we clear all existing interrupts
*/
writel(0, base + VIC_VECT_ADDR);
writel(0, base + VIC_PL190_VECT_ADDR);
for (i = 0; i < 19; i++) {
unsigned int value;
value = readl(base + VIC_VECT_ADDR);
writel(value, base + VIC_VECT_ADDR);
value = readl(base + VIC_PL190_VECT_ADDR);
writel(value, base + VIC_PL190_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
......@@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
writel(VIC_VECT_CNTL_ENABLE | i, reg);
}
writel(32, base + VIC_DEF_VECT_ADDR);
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
......
arch/arm/configs/s3c6400_defconfig 0 → 100644
View file @ fdb0a1a6
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc3
# Mon Nov 3 10:10:30 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
CONFIG_NO_IOPORT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
CONFIG_LBD=y
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_LSF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
CONFIG_ARCH_S3C64XX=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM is not set
CONFIG_PLAT_S3C64XX=y
CONFIG_CPU_S3C6400_INIT=y
CONFIG_CPU_S3C6400_CLOCK=y
CONFIG_S3C64XX_SETUP_I2C0=y
CONFIG_S3C64XX_SETUP_I2C1=y
CONFIG_PLAT_S3C=y
#
# Boot options
#
CONFIG_S3C_BOOT_ERROR_RESET=y
#
# Power management
#
CONFIG_S3C_LOWLEVEL_UART_PORT=0
CONFIG_S3C_GPIO_SPACE=0
CONFIG_S3C_GPIO_TRACK=y
CONFIG_S3C_GPIO_PULL_UPDOWN=y
CONFIG_S3C_GPIO_CFG_S3C24XX=y
CONFIG_S3C_GPIO_CFG_S3C64XX=y
CONFIG_S3C_DEV_HSMMC=y
CONFIG_S3C_DEV_HSMMC1=y
CONFIG_S3C_DEV_I2C1=y
CONFIG_CPU_S3C6410=y
CONFIG_S3C6410_SETUP_SDHCI=y
CONFIG_MACH_SMDK6410=y
CONFIG_SMDK6410_SD_CH0=y
# CONFIG_SMDK6410_SD_CH1 is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v6=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_ARM_VIC=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_NET is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_GPIO is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_UARTS=4
# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_S3C6400=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_S3C2410=y
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
CONFIG_AT24=y
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
# CONFIG_HID_PID is not set
#
# Special HID drivers
#
# CONFIG_HID_COMPAT is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# Enable Host or Gadget support to see Inventra options
#
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
# CONFIG_USB_GADGET is not set
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=y
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S3C=y
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
CONFIG_GENERIC_ACL=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
CONFIG_ROMFS_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FUNCTION_TRACER=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_S3C_PORT=y
CONFIG_DEBUG_S3C_UART=0
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
arch/arm/include/asm/hardware/vic.h
View file @ fdb0a1a6
......@@ -29,15 +29,17 @@
#define VIC_INT_SOFT 0x18
#define VIC_INT_SOFT_CLEAR 0x1c
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_VECT_CNTL_ENABLE (1 << 5)
#define VIC_PL192_VECT_ADDR 0xF00
#ifndef __ASSEMBLY__
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
#endif
......
arch/arm/mach-s3c2410/Kconfig
View file @ fdb0a1a6
......@@ -33,11 +33,6 @@ config S3C2410_GPIO
help
GPIO code for S3C2410 and similar processors
config S3C2410_CLOCK
bool
help
Clock code for the S3C2410, and similar processors
config SIMTEC_NOR
bool
help
......@@ -85,6 +80,7 @@ config ARCH_BAST
select PM_SIMTEC if PM
select SIMTEC_NOR
select MACH_BAST_IDE
select S3C24XX_DCLK
select ISA
help
Say Y here if you are using the Simtec Electronics EB2410ITX
......@@ -122,6 +118,7 @@ config MACH_TCT_HAMMER
config MACH_VR1000
bool "Thorcom VR1000"
select PM_SIMTEC if PM
select S3C24XX_DCLK
select SIMTEC_NOR
select MACH_BAST_IDE
select CPU_S3C2410
......
arch/arm/mach-s3c2410/Makefile
View file @ fdb0a1a6
......@@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
obj-$(CONFIG_S3C2410_CLOCK) += clock.o
# Machine support
......
arch/arm/mach-s3c2410/include/mach/gpio-core.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
#include <plat/gpio-core.h>
#include <mach/regs-gpio.h>
extern struct s3c_gpio_chip s3c24xx_gpios[];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG10)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */
arch/arm/mach-s3c2410/include/mach/gpio.h
View file @ fdb0a1a6
......@@ -15,4 +15,10 @@
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/* some boards require extra gpio capacity to support external
* devices that need GPIO.
*/
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#include <asm-generic/gpio.h>
arch/arm/mach-s3c2410/include/mach/irqs.h
View file @ fdb0a1a6
......@@ -134,6 +134,8 @@
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
......@@ -160,6 +162,12 @@
#define NR_IRQS (IRQ_S3C2440_AC97+1)
#endif
/* compatibility define. */
#define IRQ_UART3 IRQ_S3C2443_UART3
#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
#define FIQ_START IRQ_EINT0
......
arch/arm/mach-s3c2410/include/mach/map.h
View file @ fdb0a1a6
......@@ -13,34 +13,20 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
#include <plat/map-base.h>
#include <plat/map.h>
#define S3C2410_ADDR(x) S3C_ADDR(x)
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define S3C24XX_VA_IRQ S3C_VA_IRQ
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */
#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
#define S3C24XX_SZ_USBHOST SZ_1M
/* DMA controller */
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */
#define S3C24XX_VA_CLKPWR S3C_VA_SYS
#define S3C2410_PA_CLKPWR (0x4C000000)
#define S3C24XX_SZ_CLKPWR SZ_1M
/* LCD controller */
#define S3C2410_PA_LCD (0x4D000000)
......@@ -48,48 +34,12 @@
/* NAND flash controller */
#define S3C2410_PA_NAND (0x4E000000)
#define S3C24XX_SZ_NAND SZ_1M
/* UARTs */
#define S3C24XX_VA_UART S3C_VA_UART
#define S3C2410_PA_UART (0x50000000)
#define S3C24XX_SZ_UART SZ_1M
/* Timers */
#define S3C24XX_VA_TIMER S3C_VA_TIMER
#define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M
/* USB Device port */
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */
#define S3C2410_PA_IIC (0x54000000)
#define S3C24XX_SZ_IIC SZ_1M
/* IIS controller */
#define S3C2410_PA_IIS (0x55000000)
#define S3C24XX_SZ_IIS SZ_1M
/* GPIO ports */
/* the calculation for the VA of this must ensure that
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
* is done as a 1:1 maping. This puts it (currently) at
* 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/
#define S3C2410_PA_GPIO (0x56000000)
#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M
/* RTC */
#define S3C2410_PA_RTC (0x57000000)
......@@ -97,15 +47,12 @@
/* ADC */
#define S3C2410_PA_ADC (0x58000000)
#define S3C24XX_SZ_ADC SZ_1M
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
#define S3C24XX_SZ_SPI SZ_1M
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
#define S3C24XX_SZ_SDI SZ_1M
/* CAMIF */
#define S3C2440_PA_CAMIF (0x4F000000)
......@@ -120,13 +67,6 @@
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256)
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
*/
#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
......@@ -152,27 +92,16 @@
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2410_PA_IIC
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
#ifdef CONFIG_CPU_S3C2412_ONLY
#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
#else
#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
#endif
#else
#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s3c2410/include/mach/regs-clock.h
View file @ fdb0a1a6
......@@ -42,13 +42,6 @@
#define S3C2410_CLKCON_IIS (1<<17)
#define S3C2410_CLKCON_SPI (1<<18)
#define S3C2410_PLLCON_MDIVSHIFT 12
#define S3C2410_PLLCON_PDIVSHIFT 4
#define S3C2410_PLLCON_SDIVSHIFT 0
#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
#define S3C2410_PLLCON_SDIVMASK 3
/* DCLKCON register addresses in gpio.h */
#define S3C2410_DCLKCON_DCLK0EN (1<<0)
......@@ -76,32 +69,6 @@
#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
#ifndef __ASSEMBLY__
#include <asm/div64.h>
static inline unsigned int
s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
mdiv &= S3C2410_PLLCON_MDIVMASK;
pdiv &= S3C2410_PLLCON_PDIVMASK;
sdiv &= S3C2410_PLLCON_SDIVMASK;
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
#endif /* __ASSEMBLY__ */
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
/* extra registers */
......
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View file @ fdb0a1a6
......@@ -1053,13 +1053,6 @@
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
/* values for S3C2410_EXTINT0/1/2 */
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
#define S3C2410_EXTINT_FALLEDGE (0x02)
#define S3C2410_EXTINT_RISEEDGE (0x04)
#define S3C2410_EXTINT_BOTHEDGE (0x06)
/* interrupt filtering conrrol for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
......
arch/arm/mach-s3c2410/include/mach/spi.h
View file @ fdb0a1a6
......@@ -22,5 +22,12 @@ struct s3c2410_spi_info {
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
/* Standard setup / suspend routines for SPI GPIO pins. */
extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable);
extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable);
#endif /* __ASM_ARCH_SPI_H */
arch/arm/mach-s3c2410/include/mach/tick.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - timer tick support
*/
#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
static inline int s3c24xx_ostimer_pending(void)
{
return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
}
arch/arm/mach-s3c2410/include/mach/uncompress.h
View file @ fdb0a1a6
/* arch/arm/mach-s3c2410/include/mach/uncompress.h
*
* Copyright (c) 2003, 2007 Simtec Electronics
......
arch/arm/mach-s3c2410/mach-amlm5900.c
View file @ fdb0a1a6
......@@ -52,6 +52,7 @@
#include <mach/regs-lcd.h>
#include <mach/regs-gpio.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......@@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = {
#endif
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
......@@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
#ifdef CONFIG_FB_S3C2410
s3c24xx_fb_set_platdata(&amlm5900_fb_info);
#endif
s3c_i2c0_set_platdata(NULL);
platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
}
......
arch/arm/mach-s3c2410/mach-bast.c
View file @ fdb0a1a6
......@@ -406,7 +406,7 @@ static struct platform_device bast_sio = {
* standard 100KHz i2c bus frequency
*/
static struct s3c2410_platform_i2c bast_i2c_info = {
static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
......@@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&bast_device_dm9k,
......@@ -588,7 +588,8 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
s3c_device_i2c.dev.platform_data = &bast_i2c_info;
s3c_i2c0_set_platdata(&bast_i2c_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);
......
arch/arm/mach-s3c2410/mach-h1940.c
View file @ fdb0a1a6
......@@ -39,10 +39,12 @@
#include <mach/h1940-latch.h>
#include <mach/fb.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/pm.h>
static struct map_desc h1940_iodesc[] __initdata = {
......@@ -183,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&s3c_device_leds,
......@@ -215,6 +217,7 @@ static void __init h1940_init(void)
s3c24xx_fb_set_platdata(&h1940_fb_info);
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
s3c_i2c0_set_platdata(NULL);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
......@@ -223,10 +226,9 @@ static void __init h1940_init(void)
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
tmp = (
0x78 << S3C2410_PLLCON_MDIVSHIFT)
| (0x02 << S3C2410_PLLCON_PDIVSHIFT)
| (0x03 << S3C2410_PLLCON_SDIVSHIFT);
tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
writel(tmp, S3C2410_UPLLCON);
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
......
arch/arm/mach-s3c2410/mach-n30.c
View file @ fdb0a1a6
......@@ -17,7 +17,6 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/init.h>
#include <linux/input.h>
......@@ -320,7 +319,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usb,
&s3c_device_usbgadget,
......@@ -332,7 +331,7 @@ static struct platform_device *n30_devices[] __initdata = {
static struct platform_device *n35_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&n35_button_device,
......@@ -501,7 +500,7 @@ static void __init n30_init_irq(void)
static void __init n30_init(void)
{
s3c24xx_fb_set_platdata(&n30_fb_info);
s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
s3c24xx_udc_set_platdata(&n30_udc_cfg);
/* Turn off suspend on both USB ports, and switch the
......
arch/arm/mach-s3c2410/mach-otom.c
View file @ fdb0a1a6
......@@ -35,6 +35,7 @@
#include <plat/s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/cpu.h>
static struct map_desc otom11_iodesc[] __initdata = {
......@@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&otom_device_nor,
......@@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
static void __init otom11_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
}
......
arch/arm/mach-s3c2410/mach-qt2410.c
View file @ fdb0a1a6
......@@ -54,6 +54,7 @@
#include <plat/udc.h>
#include <mach/spi.h>
#include <mach/spi-gpio.h>
#include <plat/iic.h>
#include <plat/common-smdk.h>
#include <plat/devs.h>
......@@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_sdi,
&s3c_device_usbgadget,
......@@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void)
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
......
arch/arm/mach-s3c2410/mach-smdk2410.c
View file @ fdb0a1a6
......@@ -47,6 +47,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......@@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
......@@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
static void __init smdk2410_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
smdk_machine_init();
}
......
arch/arm/mach-s3c2410/mach-tct_hammer.c
View file @ fdb0a1a6
......@@ -45,6 +45,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......@@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
static struct platform_device *tct_hammer_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
......@@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void)
static void __init tct_hammer_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
}
......
arch/arm/mach-s3c2410/mach-vr1000.c
View file @ fdb0a1a6
......@@ -47,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
......@@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_adc,
&serial_device,
&vr1000_dm9k0,
......@@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
static void __init vr1000_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
i2c_register_board_info(0, vr1000_i2c_devs,
......
arch/arm/mach-s3c2410/s3c2410.c
View file @ fdb0a1a6
......@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
......@@ -28,6 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
......@@ -35,6 +38,7 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pll.h>
/* Initial IO mappings */
......@@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
* machine specific initialisation.
*/
void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2410_map_io(void)
{
/* register our io-tables */
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
iotable_init(mach_desc, mach_size);
}
void __init s3c2410_init_clocks(int xtal)
void __init_or_cpufreq s3c2410_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
......@@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal)
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2410_init_clocks(int xtal)
{
s3c24xx_register_baseclocks(xtal);
s3c2410_setup_clocks();
s3c2410_baseclk_add();
}
......
arch/arm/mach-s3c2412/clock.c
View file @ fdb0a1a6
......@@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
/* clock selections */
/* CPU EXTCLK input */
static struct clk clk_ext = {
.name = "extclk",
.id = -1,
};
static struct clk clk_erefclk = {
.name = "erefclk",
.id = -1,
......@@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void)
s3c2412_clkcon_enable(clkp, 0);
}
s3c_pwmclk_init();
return 0;
}
arch/arm/mach-s3c2412/mach-jive.c
View file @ fdb0a1a6
......@@ -17,7 +17,6 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
......@@ -53,6 +52,7 @@
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/udc.h>
#include <plat/iic.h>
static struct map_desc jive_iodesc[] __initdata = {
};
......@@ -398,11 +398,12 @@ static struct s3c2410_spigpio_info jive_lcd_spi = {
.bus_num = 1,
.pin_clk = S3C2410_GPG8,
.pin_mosi = S3C2410_GPB8,
.num_chipselect = 1,
.chip_select = jive_lcd_spi_chipselect,
};
static struct platform_device jive_device_lcdspi = {
.name = "s3c24xx-spi-gpio",
.name = "spi_s3c24xx_gpio",
.id = 1,
.num_resources = 0,
.dev.platform_data = &jive_lcd_spi,
......@@ -419,11 +420,12 @@ static struct s3c2410_spigpio_info jive_wm8750_spi = {
.bus_num = 2,
.pin_clk = S3C2410_GPB4,
.pin_mosi = S3C2410_GPB9,
.num_chipselect = 1,
.chip_select = jive_wm8750_chipselect,
};
static struct platform_device jive_device_wm8750 = {
.name = "s3c24xx-spi-gpio",
.name = "spi_s3c24xx_gpio",
.id = 2,
.num_resources = 0,
.dev.platform_data = &jive_wm8750_spi,
......@@ -450,14 +452,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
/* I2C bus and device configuration. */
static struct s3c2410_platform_i2c jive_i2c_cfg = {
static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
.max_freq = 80 * 1000,
.bus_freq = 50 * 1000,
.flags = S3C_IICFLG_FILTER,
.sda_delay = 2,
};
static struct i2c_board_info jive_i2c_devs[] = {
static struct i2c_board_info jive_i2c_devs[] __initdata = {
[0] = {
I2C_BOARD_INFO("lis302dl", 0x1c),
.irq = IRQ_EINT14,
......@@ -470,7 +472,7 @@ static struct platform_device *jive_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_lcd,
&jive_device_lcdspi,
&jive_device_wm8750,
......@@ -663,7 +665,7 @@ static void __init jive_machine_init(void)
spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
s3c_i2c0_set_platdata(&jive_i2c_cfg);
i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
pm_power_off = jive_power_off;
......
arch/arm/mach-s3c2412/mach-smdk2413.c
View file @ fdb0a1a6
......@@ -38,6 +38,7 @@
#include <mach/idle.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <mach/fb.h>
#include <plat/s3c2410.h>
......@@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = {
&s3c_device_usb,
//&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
};
......@@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void)
s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
smdk_machine_init();
......
arch/arm/mach-s3c2412/mach-vstms.c
View file @ fdb0a1a6
......@@ -39,6 +39,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/nand.h>
#include <plat/s3c2410.h>
......@@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = {
static struct platform_device *vstms_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_nand,
......@@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
static void __init vstms_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}
......
arch/arm/mach-s3c2412/s3c2412.c
View file @ fdb0a1a6
......@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
......@@ -33,6 +34,8 @@
#include <mach/reset.h>
#include <mach/idle.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-power.h>
......@@ -47,6 +50,7 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pm.h>
#include <plat/pll.h>
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
......@@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void)
* machine specific initialisation.
*/
void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2412_map_io(void)
{
/* move base of IO */
......@@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
/* register our io-tables */
iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
iotable_init(mach_desc, mach_size);
}
void __init s3c2412_init_clocks(int xtal)
void __init_or_cpufreq s3c2412_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
clk_mpll.rate = fclk;
......@@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal)
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2412_init_clocks(int xtal)
{
/* initialise the clocks here, to allow other things like the
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_register_baseclocks(xtal);
s3c2412_setup_clocks();
s3c2412_baseclk_add();
}
......
arch/arm/mach-s3c2440/Kconfig
View file @ fdb0a1a6
......@@ -29,8 +29,10 @@ menu "S3C2440 Machines"
config MACH_ANUBIS
bool "Simtec Electronics ANUBIS"
select CPU_S3C2440
select S3C24XX_DCLK
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
select S3C24XX_GPIO_EXTRA64
help
Say Y here if you are using the Simtec Electronics ANUBIS
development system
......@@ -38,7 +40,9 @@ config MACH_ANUBIS
config MACH_OSIRIS
bool "Simtec IM2440D20 (OSIRIS) module"
select CPU_S3C2440
select S3C24XX_DCLK
select PM_SIMTEC if PM
select S3C24XX_GPIO_EXTRA128
help
Say Y here if you are using the Simtec IM2440D20 module, also
known as the Osiris.
......
arch/arm/mach-s3c2440/mach-anubis.c
View file @ fdb0a1a6
......@@ -40,6 +40,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
......@@ -366,6 +367,8 @@ static struct sm501_initdata anubis_sm501_initdata = {
.mask = 0,
},
.devices = SM501_USE_GPIO,
/* set the SDRAM and bus clocks */
.mclk = 72 * MHZ,
.m1xclk = 144 * MHZ,
......@@ -373,10 +376,12 @@ static struct sm501_initdata anubis_sm501_initdata = {
static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
[0] = {
.bus_num = 1,
.pin_scl = 44,
.pin_sda = 45,
},
[1] = {
.bus_num = 2,
.pin_scl = 40,
.pin_sda = 41,
},
......@@ -384,6 +389,7 @@ static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
static struct sm501_platdata anubis_sm501_platdata = {
.init = &anubis_sm501_initdata,
.gpio_base = -1,
.gpio_i2c = anubis_sm501_gpio_i2c,
.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
};
......@@ -404,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&anubis_device_ide0,
......@@ -468,6 +474,7 @@ static void __init anubis_map_io(void)
static void __init anubis_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
i2c_register_board_info(0, anubis_i2c_devs,
......
arch/arm/mach-s3c2440/mach-at2440evb.c
View file @ fdb0a1a6
......@@ -28,6 +28,7 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/fb.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
......@@ -36,6 +37,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
......@@ -45,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <asm/plat-s3c24xx/mci.h>
static struct map_desc at2440evb_iodesc[] __initdata = {
/* Nothing here */
......@@ -162,19 +165,60 @@ static struct platform_device at2440evb_device_eth = {
},
};
static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
.gpio_detect = S3C2410_GPG10,
};
/* 7" LCD panel */
static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
.lcdcon5 = S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_PWREN |
S3C2410_LCDCON5_HWSWP,
.type = S3C2410_LCDCON1_TFT,
.width = 800,
.height = 480,
.pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
.xres = 800,
.yres = 480,
.bpp = 16,
.left_margin = 88,
.right_margin = 40,
.hsync_len = 128,
.upper_margin = 32,
.lower_margin = 11,
.vsync_len = 2,
};
static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
.displays = &at2440evb_lcd_cfg,
.num_displays = 1,
.default_display = 0,
};
static struct platform_device *at2440evb_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_sdi,
&s3c_device_lcd,
&at2440evb_device_eth,
};
static void __init at2440evb_map_io(void)
{
s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
s3c24xx_init_clocks(16934400);
......@@ -183,6 +227,9 @@ static void __init at2440evb_map_io(void)
static void __init at2440evb_init(void)
{
s3c24xx_fb_set_platdata(&at2440evb_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}
......
arch/arm/mach-s3c2440/mach-nexcoder.c
View file @ fdb0a1a6
......@@ -37,6 +37,7 @@
//#include <asm/debug-ll.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
......@@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_camif,
......@@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
static void __init nexcoder_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
};
......
arch/arm/mach-s3c2440/mach-osiris.c
View file @ fdb0a1a6
......@@ -38,6 +38,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
......@@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
/* Standard Osiris devices */
static struct platform_device *osiris_devices[] __initdata = {
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_wdt,
&s3c_device_nand,
&osiris_pcmcia,
......@@ -398,6 +399,8 @@ static void __init osiris_init(void)
sysdev_class_register(&osiris_pm_sysclass);
sysdev_register(&osiris_pm_sysdev);
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, osiris_i2c_devs,
ARRAY_SIZE(osiris_i2c_devs));
......
arch/arm/mach-s3c2440/mach-rx3715.c
View file @ fdb0a1a6
......@@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_nand,
};
......
arch/arm/mach-s3c2440/mach-smdk2440.c
View file @ fdb0a1a6
......@@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
......@@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
......@@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
static void __init smdk2440_machine_init(void)
{
s3c24xx_fb_set_platdata(&smdk2440_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
smdk_machine_init();
......
arch/arm/mach-s3c2443/Kconfig
View file @ fdb0a1a6
......@@ -24,6 +24,7 @@ config MACH_SMDK2443
bool "SMDK2443"
select CPU_S3C2443
select MACH_SMDK
select S3C_DEV_HSMMC
help
Say Y here if you are using an SMDK2443
......
arch/arm/mach-s3c2443/clock.c
View file @ fdb0a1a6
......@@ -29,7 +29,6 @@
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/io.h>
......@@ -39,6 +38,8 @@
#include <mach/regs-s3c2443-clock.h>
#include <plat/cpu-freq.h>
#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/cpu.h>
......@@ -145,12 +146,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
/* clock selections */
/* CPU EXTCLK input */
static struct clk clk_ext = {
.name = "ext",
.id = -1,
};
static struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
......@@ -165,14 +160,6 @@ static struct clk clk_mpll = {
};
#endif
static struct clk clk_epllref;
static struct clk clk_epll = {
.name = "epll",
.parent = &clk_epllref,
.id = -1,
};
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
.id = -1,
......@@ -1011,22 +998,20 @@ static struct clk *clks[] __initdata = {
&clk_prediv,
};
void __init s3c2443_init_clocks(int xtal)
void __init_or_cpufreq s3c2443_setup_clocks(void)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
struct clk *clkp;
int ret;
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.rate = pll;
......@@ -1036,13 +1021,29 @@ void __init s3c2443_init_clocks(int xtal)
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2443_init_clocks(int xtal)
{
struct clk *clkp;
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
int ret;
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
s3c24xx_register_baseclocks(xtal);
s3c2443_setup_clocks();
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
......@@ -1056,7 +1057,7 @@ void __init s3c2443_init_clocks(int xtal)
}
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_epll.parent = &clk_epllref;
clk_usb_bus.parent = &clk_usb_bus_host;
/* ensure usb bus clock is within correct rate of 48MHz */
......@@ -1105,4 +1106,6 @@ void __init s3c2443_init_clocks(int xtal)
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
arch/arm/mach-s3c2443/mach-smdk2443.c
View file @ fdb0a1a6
......@@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
......@@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
static struct platform_device *smdk2443_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_hsmmc,
&s3c_device_i2c0,
&s3c_device_hsmmc0,
};
static void __init smdk2443_map_io(void)
......@@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
static void __init smdk2443_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
smdk_machine_init();
}
......
arch/arm/mach-s3c2443/s3c2443.c
View file @ fdb0a1a6
......@@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
* machine specific initialisation.
*/
void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2443_map_io(void)
{
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
iotable_init(mach_desc, mach_size);
}
/* need to register class before we actually register the device, and
......
arch/arm/mach-s3c24a0/include/mach/debug-macro.S 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C24XX_PA_UART
ldrne \rx, = S3C24XX_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>
arch/arm/mach-s3c24a0/include/mach/irqs.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_IRQS_H
#define __ASM_ARCH_24A0_IRQS_H __FILE__
#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
/* for generic entry-macro.S */
#define IRQ_EINT0 IRQ_EINT0t2
#define IRQ_EINT3t6 S3C2410_IRQ(1)
#define IRQ_EINT7t10 S3C2410_IRQ(2)
#define IRQ_EINT11t14 S3C2410_IRQ(3)
#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
#define IRQ_TICK S3C2410_IRQ(5)
#define IRQ_DCTQ S3C2410_IRQ(6)
#define IRQ_MC S3C2410_IRQ(7)
#define IRQ_ME S3C2410_IRQ(8) /* 24 */
#define IRQ_KEYPAD S3C2410_IRQ(9)
#define IRQ_TIMER0 S3C2410_IRQ(10)
#define IRQ_TIMER1 S3C2410_IRQ(11)
#define IRQ_TIMER2 S3C2410_IRQ(12)
#define IRQ_TIMER3_4 S3C2410_IRQ(13)
#define IRQ_OS_TIMER IRQ_TIMER3_4
#define IRQ_LCD S3C2410_IRQ(14)
#define IRQ_CAM_C S3C2410_IRQ(15)
#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
#define IRQ_UART0 S3C2410_IRQ(17)
#define IRQ_CAM_P S3C2410_IRQ(18)
#define IRQ_MODEM S3C2410_IRQ(19)
#define IRQ_DMA S3C2410_IRQ(20)
#define IRQ_SDI S3C2410_IRQ(21)
#define IRQ_SPI0 S3C2410_IRQ(22)
#define IRQ_UART1 S3C2410_IRQ(23)
#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
#define IRQ_USBD S3C2410_IRQ(25)
#define IRQ_USBH S3C2410_IRQ(26)
#define IRQ_IIC S3C2410_IRQ(27)
#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
#define IRQ_ADC_PEN S3C2410_IRQ(31)
/* interrupts generated from the external interrupts sources */
#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
#define IRQ_EINT1 S3C2410_IRQ(33)
#define IRQ_EINT2 S3C2410_IRQ(34)
#define IRQ_EINT3 S3C2410_IRQ(35)
#define IRQ_EINT4 S3C2410_IRQ(36)
#define IRQ_EINT5 S3C2410_IRQ(37)
#define IRQ_EINT6 S3C2410_IRQ(38)
#define IRQ_EINT7 S3C2410_IRQ(39)
#define IRQ_EINT8 S3C2410_IRQ(40)
#define IRQ_EINT9 S3C2410_IRQ(41)
#define IRQ_EINT10 S3C2410_IRQ(42)
#define IRQ_EINT11 S3C2410_IRQ(43)
#define IRQ_EINT12 S3C2410_IRQ(44)
#define IRQ_EINT13 S3C2410_IRQ(45)
#define IRQ_EINT14 S3C2410_IRQ(46)
#define IRQ_EINT15 S3C2410_IRQ(47)
#define IRQ_EINT16 S3C2410_IRQ(48)
#define IRQ_EINT17 S3C2410_IRQ(49)
#define IRQ_EINT18 S3C2410_IRQ(50)
/* SUB IRQS */
#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
#define IRQ_S3CUART_RX2 (0x0)
#define IRQ_S3CUART_TX2 (0x0)
#define IRQ_S3CUART_ERR2 (0x0)
#define IRQ_IRDA S3C2410_IRQ(57)
#define IRQ_MSTICK S3C2410_IRQ(58)
#define IRQ_RESERVED0 S3C2410_IRQ(59)
#define IRQ_RESERVED1 S3C2410_IRQ(60)
#define IRQ_RESERVED2 S3C2410_IRQ(61)
#define IRQ_TIMER3 S3C2410_IRQ(62)
#define IRQ_TIMER4 S3C2410_IRQ(63)
#define IRQ_WDT S3C2410_IRQ(64)
#define IRQ_BATFLT S3C2410_IRQ(65)
#define IRQ_POST S3C2410_IRQ(66)
#define IRQ_DISP_FIFO S3C2410_IRQ(67)
#define IRQ_PENUP S3C2410_IRQ(68)
#define IRQ_PENDN S3C2410_IRQ(69)
#define IRQ_ADC S3C2410_IRQ(70)
#define IRQ_DISP_FRAME S3C2410_IRQ(71)
#define IRQ_NFLASH S3C2410_IRQ(72)
#define IRQ_AC97 S3C2410_IRQ(73)
#define IRQ_SPI1 S3C2410_IRQ(74)
#define IRQ_VLX S3C2410_IRQ(75)
#define IRQ_DMA0 S3C2410_IRQ(76)
#define IRQ_DMA1 S3C2410_IRQ(77)
#define IRQ_DMA2 S3C2410_IRQ(78)
#define IRQ_DMA3 S3C2410_IRQ(79)
#define IRQ_TC (0x0)
#define NR_IRQS (IRQ_DMA3+1)
#endif /* __ASM_ARCH_24A0_IRQS_H */
arch/arm/mach-s3c24a0/include/mach/map.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
*
* Copyright 2003,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MAP_H
#define __ASM_ARCH_24A0_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map.h>
#define S3C24A0_PA_IO_BASE (0x40000000)
#define S3C24A0_PA_CLKPWR (0x40000000)
#define S3C24A0_PA_IRQ (0x40200000)
#define S3C24A0_PA_DMA (0x40400000)
#define S3C24A0_PA_MEMCTRL (0x40C00000)
#define S3C24A0_PA_NAND (0x40C00000)
#define S3C24A0_PA_SROM (0x40C20000)
#define S3C24A0_PA_SDRAM (0x40C40000)
#define S3C24A0_PA_BUSM (0x40CE0000)
#define S3C24A0_PA_USBHOST (0x41000000)
#define S3C24A0_PA_MODEMIF (0x41180000)
#define S3C24A0_PA_IRDA (0x41800000)
#define S3C24A0_PA_TIMER (0x44000000)
#define S3C24A0_PA_WATCHDOG (0x44100000)
#define S3C24A0_PA_RTC (0x44200000)
#define S3C24A0_PA_UART (0x44400000)
#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
#define S3C24A0_PA_SPI (0x44500000)
#define S3C24A0_PA_IIC (0x44600000)
#define S3C24A0_PA_IIS (0x44700000)
#define S3C24A0_PA_GPIO (0x44800000)
#define S3C24A0_PA_KEYIF (0x44900000)
#define S3C24A0_PA_USBDEV (0x44A00000)
#define S3C24A0_PA_AC97 (0x45000000)
#define S3C24A0_PA_ADC (0x45800000)
#define S3C24A0_PA_SDI (0x46000000)
#define S3C24A0_PA_MS (0x46100000)
#define S3C24A0_PA_LCD (0x4A000000)
#define S3C24A0_PA_VPOST (0x4A100000)
/* physical addresses of all the chip-select areas */
#define S3C24A0_CS0 (0x00000000)
#define S3C24A0_CS1 (0x04000000)
#define S3C24A0_CS2 (0x08000000)
#define S3C24A0_CS3 (0x0C000000)
#define S3C24A0_CS4 (0x10000000)
#define S3C24A0_CS5 (0x40000000)
#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
#define S3C24XX_PA_DMA S3C24A0_PA_DMA
#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
#define S3C24XX_PA_LCD S3C24A0_PA_LCD
#define S3C24XX_PA_UART S3C24A0_PA_UART
#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
#define S3C24XX_PA_IIS S3C24A0_PA_IIS
#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
#define S3C24XX_PA_RTC S3C24A0_PA_RTC
#define S3C24XX_PA_ADC S3C24A0_PA_ADC
#define S3C24XX_PA_SPI S3C24A0_PA_SPI
#define S3C24XX_PA_SDI S3C24A0_PA_SDI
#define S3C24XX_PA_NAND S3C24A0_PA_NAND
#define S3C_PA_UART S3C24A0_PA_UART
#define S3C_PA_IIC S3C24A0_PA_IIC
#endif /* __ASM_ARCH_24A0_MAP_H */
arch/arm/mach-s3c24a0/include/mach/memory.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
* from linux/include/asm-arm/arch-rpc/memory.h
*
* Copyright (C) 1996,1997,1998 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MEMORY_H
#define __ASM_ARCH_24A0_MEMORY_H __FILE__
#define PHYS_OFFSET UL(0x10000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
arch/arm/mach-s3c24a0/include/mach/regs-clock.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
*
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 clock register definitions
*/
#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
/* CLKCON register bits */
#define S3C24A0_CLKCON_VLX (1<<29)
#define S3C24A0_CLKCON_VPOST (1<<28)
#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
#define S3C24A0_CLKCON_VPOSTIF (1<<25)
#define S3C24A0_CLKCON_MPEG4IF (1<<24)
#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
#define S3C24A0_CLKCON_LCDC (1<<22)
#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
#define S3C24A0_CLKCON_MPEG4 (1<<20)
#define S3C24A0_CLKCON_KEYPAD (1<<19)
#define S3C24A0_CLKCON_ADC (1<<18)
#define S3C24A0_CLKCON_SDI (1<<17)
#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
#define S3C24A0_CLKCON_USBD (1<<15)
#define S3C24A0_CLKCON_GPIO (1<<14)
#define S3C24A0_CLKCON_IIS (1<<13)
#define S3C24A0_CLKCON_IIC (1<<12)
#define S3C24A0_CLKCON_SPI (1<<11)
#define S3C24A0_CLKCON_UART1 (1<<10)
#define S3C24A0_CLKCON_UART0 (1<<9)
#define S3C24A0_CLKCON_PWMT (1<<8)
#define S3C24A0_CLKCON_USBH (1<<7)
#define S3C24A0_CLKCON_AC97 (1<<6)
#define S3C24A0_CLKCON_IrDA (1<<4)
#define S3C24A0_CLKCON_IDLE (1<<2)
#define S3C24A0_CLKCON_MON (1<<1)
#define S3C24A0_CLKCON_STOP (1<<0)
/* CLKSRC register bits */
#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
#define S3C24A0_CLKSRC_UPLL (1<<7)
#define S3C24A0_CLKSRC_MPLL (1<<5)
#define S3C24A0_CLKSRC_EXT (1<<4)
/* Use a single interface with the common code, for s3c24xx */
#define S3C2410_MPLLCON S3C24A0_MPLLCON
#define S3C2410_UPLLCON S3C24A0_UPLLCON
#define S3C2410_CLKCON S3C24A0_CLKCON
#define S3C2410_CLKSLOW S3C24A0_CLKSRC
#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
#define S3C2410_CLKSLOW_SLOW (0xFF)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
arch/arm/mach-s3c24a0/include/mach/regs-irq.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
arch/arm/mach-s3c24a0/include/mach/system.h 0 → 100644
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/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - System function defines and includes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
#include <asm/io.h>
#include <mach/map.h>
static void arch_idle(void)
{
/* currently no specific idle support. */
}
void (*s3c24xx_reset_hook)(void);
#include <asm/plat-s3c24xx/system-reset.h>
arch/arm/mach-s3c24a0/include/mach/tick.h 0 → 100644
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/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24A0 - timer tick support
*/
#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
static inline int s3c24xx_ostimer_pending(void)
{
return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
}
arch/arm/mach-s3c24a0/include/mach/timex.h 0 → 100644
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/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */
arch/arm/mach-s3c24a0/include/mach/vmalloc.h 0 → 100644
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/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
*
* Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s3c6400/Kconfig 0 → 100644
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# arch/arm/mach-s3c6400/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
# Currently nothing here, this will be added later
arch/arm/mach-s3c6400/Makefile 0 → 100644
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# arch/arm/mach-s3c6400/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6400 system
obj-n += blank.o
arch/arm/mach-s3c6400/Makefile.boot 0 → 100644
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zreladdr-y := 0x50008000
params_phys-y := 0x50000100
arch/arm/mach-s3c6400/include/mach/debug-macro.S 0 → 100644
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/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C_PA_UART
ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
#if CONFIG_DEBUG_S3C_UART != 0
add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>
arch/arm/mach-s3c6400/include/mach/dma.h 0 → 100644
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/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - DMA support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/entry-macro.S 0 → 100644
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/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Low-level IRQ helper macros for the Samsung S3C64XX series
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =S3C_VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, # S3C_IRQ_OFFSET + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm
arch/arm/mach-s3c6400/include/mach/gpio-core.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
/* currently we just include the platform support */
#include <plat/gpio-core.h>
#endif /* __ASM_ARCH_GPIO_CORE_H */
arch/arm/mach-s3c6400/include/mach/gpio.h 0 → 100644
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/* arch/arm/mach-s3c6400/include/mach/gpio.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C6400 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S3C64XX_GPIO_A_NR (8)
#define S3C64XX_GPIO_B_NR (7)
#define S3C64XX_GPIO_C_NR (8)
#define S3C64XX_GPIO_D_NR (5)
#define S3C64XX_GPIO_E_NR (5)
#define S3C64XX_GPIO_F_NR (16)
#define S3C64XX_GPIO_G_NR (7)
#define S3C64XX_GPIO_H_NR (10)
#define S3C64XX_GPIO_I_NR (16)
#define S3C64XX_GPIO_J_NR (12)
#define S3C64XX_GPIO_K_NR (16)
#define S3C64XX_GPIO_L_NR (15)
#define S3C64XX_GPIO_M_NR (6)
#define S3C64XX_GPIO_N_NR (16)
#define S3C64XX_GPIO_O_NR (16)
#define S3C64XX_GPIO_P_NR (15)
#define S3C64XX_GPIO_Q_NR (9)
/* GPIO bank numbes */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S3C64XX_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
S3C64XX_GPIO_A_START = 0,
S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
};
/* S3C64XX GPIO number definitions. */
#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
/* the end of the S3C64XX specific gpios */
#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#define S3C_GPIO_END S3C64XX_GPIO_END
/* define the number of gpios we need to the one after the GPQ() range */
#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#include <asm-generic/gpio.h>
arch/arm/mach-s3c6400/include/mach/hardware.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - Hardware support
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/irqs.h 0 → 100644
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/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - IRQ definitions
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#ifndef __ASM_ARM_IRQ_H
#error "Do not include this directly, instead #include <asm/irq.h>"
#endif
#include <plat/irqs.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/map.h 0 → 100644
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/* linux/arch/arm/mach-s3c6400/include/mach/map.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/* HSMMC units */
#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
#define S3C_PA_UART (0x7F005000)
#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
#define S3C_PA_UART2 (S3C_PA_UART + 0x800)
#define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
#define S3C_UART_OFFSET (0x400)
/* See notes on UART VA mapping in debug-macro.S */
#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
#define S3C_VA_UART0 S3C_VA_UARTx(0)
#define S3C_VA_UART1 S3C_VA_UARTx(1)
#define S3C_VA_UART2 S3C_VA_UARTx(2)
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_SYSCON (0x7E00F000)
#define S3C64XX_PA_TIMER (0x7F006000)
#define S3C64XX_PA_IIC0 (0x7F004000)
#define S3C64XX_PA_IIC1 (0x7F00F000)
#define S3C64XX_PA_GPIO (0x7F008000)
#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
#define S3C64XX_SZ_GPIO SZ_4K
#define S3C64XX_PA_SDRAM (0x50000000)
#define S3C64XX_PA_VIC0 (0x71200000)
#define S3C64XX_PA_VIC1 (0x71300000)
/* place VICs close together */
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
/* compatibiltiy defines. */
#define S3C_PA_TIMER S3C64XX_PA_TIMER
#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
#define S3C_PA_IIC S3C64XX_PA_IIC0
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
#define S3C_PA_FB S3C64XX_PA_FB
#endif /* __ASM_ARCH_6400_MAP_H */
arch/arm/mach-s3c6400/include/mach/memory.h 0 → 100644
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/* arch/arm/mach-s3c6400/include/mach/memory.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x50000000)
#endif
arch/arm/mach-s3c6400/include/mach/pwm-clock.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
arch/arm/mach-s3c6400/include/mach/regs-fb.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards and specifically the S3C64XX series
* S3C6400 and S3C6410.
*
* The file contains the cpu specific items which change between whichever
* architecture is selected. See <plat/regs-fb.h> for the core definitions
* that are the same.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* include the core definitions here, in case we really do need to
* override them at a later date.
*/
#include <plat/regs-fb.h>
#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
/* Window position controls */
#define WINCON(_win) (0x20 + ((_win) * 4))
/* OSD1 and OSD4 do not have register D */
#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDINTCON0 (0x130)
#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
/* WINCONx */
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_YCbCr (1 << 13)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_BLD_PIX (1 << 6)
#define WINCON2_ALPHA_SEL (1 << 1)
#define WINCON2_BPPMODE_MASK (0xf << 2)
#define WINCON2_BPPMODE_SHIFT (2)
#define WINCON2_BPPMODE_1BPP (0x0 << 2)
#define WINCON2_BPPMODE_2BPP (0x1 << 2)
#define WINCON2_BPPMODE_4BPP (0x2 << 2)
#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON3_BLD_PIX (1 << 6)
#define WINCON3_ALPHA_SEL (1 << 1)
#define WINCON3_BPPMODE_MASK (0xf << 2)
#define WINCON3_BPPMODE_SHIFT (2)
#define WINCON3_BPPMODE_1BPP (0x0 << 2)
#define WINCON3_BPPMODE_2BPP (0x1 << 2)
#define WINCON3_BPPMODE_4BPP (0x2 << 2)
#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define DITHMODE (0x170)
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT (5)
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT (3)
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT (1)
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#define DITHMODE_DITH_EN (1 << 0)
#define WPALCON (0x1A0)
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
/* Palette registers */
#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
/* system specific implementation code for palette sizes, and other
* information that changes depending on which architecture is being
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
static inline void s3c_fb_init_palette(unsigned int window,
struct s3c_fb_palette *palette)
{
if (window < 2) {
/* Windows 0/1 are 8/8/8 or A/8/8/8 */
palette->r.offset = 16;
palette->r.length = 8;
palette->g.offset = 8;
palette->g.length = 8;
palette->b.offset = 0;
palette->b.length = 8;
} else {
/* currently we assume RGB 5/6/5 */
palette->r.offset = 11;
palette->r.length = 5;
palette->g.offset = 5;
palette->g.length = 6;
palette->b.offset = 0;
palette->b.length = 5;
}
}
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/
arch/arm/mach-s3c6400/include/mach/regs-irq.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <asm/hardware/vic.h>
#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
arch/arm/mach-s3c6400/include/mach/system.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6400/include/mach/system.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - system implementation
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void)
{
/* nothing here yet */
}
static void arch_reset(char mode)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/tick.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
/* note, the timer interrutps turn up in 2 places, the vic and then
* the timer block. We take the VIC as the base at the moment.
*/
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_6400_TICK_H */
arch/arm/mach-s3c6400/include/mach/uncompress.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c6400/include/mach/uncompress.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C6400 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
arch/arm/mach-s3c6410/Kconfig 0 → 100644
View file @ fdb0a1a6
# arch/arm/mach-s3c6410/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
# Configuration options for the S3C6410 CPU
config CPU_S3C6410
bool
select CPU_S3C6400_INIT
select CPU_S3C6400_CLOCK
help
Enable S3C6410 CPU support
config S3C6410_SETUP_SDHCI
bool
help
Internal helper functions for S3C6410 based SDHCI systems
config MACH_SMDK6410
bool "SMDK6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
select S3C_DEV_FB
select S3C6410_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_FB_24BPP
help
Machine support for the Samsung SMDK6410
# At least some of the SMDK6410s were shipped with the card detect
# for the MMC/SD slots connected to the same input. This means that
# either the boards need to be altered to have channel0 to an alternate
# configuration or that only one slot can be used.
choice
prompt "SMDK6410 MMC/SD slot setup"
depends on MACH_SMDK6410
config SMDK6410_SD_CH0
bool "Use channel 0 only"
depends on MACH_SMDK6410
help
Select CON7 (channel 0) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
config SMDK6410_SD_CH1
bool "Use channel 1 only"
depends on MACH_SMDK6410
help
Select CON6 (channel 1) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
endchoice
arch/arm/mach-s3c6410/Makefile 0 → 100644
View file @ fdb0a1a6
# arch/arm/plat-s3c6410/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6410 system
obj-$(CONFIG_CPU_S3C6410) += cpu.o
# Helper and device support
obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
arch/arm/mach-s3c6410/cpu.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6410/cpu.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* Initial IO mappings */
static struct map_desc s3c6410_iodesc[] __initdata = {
};
/* s3c6410_map_io
*
* register the standard cpu IO areas
*/
void __init s3c6410_map_io(void)
{
iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
}
void __init s3c6410_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks();
s3c6400_setup_clocks();
}
void __init s3c6410_init_irq(void)
{
/* VIC0 is missing IRQ7, VIC1 is fully populated. */
s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
}
struct sysdev_class s3c6410_sysclass = {
.name = "s3c6410-core",
};
static struct sys_device s3c6410_sysdev = {
.cls = &s3c6410_sysclass,
};
static int __init s3c6410_core_init(void)
{
return sysdev_class_register(&s3c6410_sysclass);
}
core_initcall(s3c6410_core_init);
int __init s3c6410_init(void)
{
printk("S3C6410: Initialising architecture\n");
return sysdev_register(&s3c6410_sysdev);
}
arch/arm/mach-s3c6410/mach-smdk6410.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
/* framebuffer and LCD setup. */
/* GPF15 = LCD backlight control
* GPF13 => Panel power
* GPN5 = LCD nRESET signal
* PWM_TOUT1 => backlight brightness
*/
static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
gpio_direction_output(S3C64XX_GPF(13), 1);
gpio_direction_output(S3C64XX_GPF(15), 1);
/* fire nRESET on power up */
gpio_direction_output(S3C64XX_GPN(5), 0);
msleep(10);
gpio_direction_output(S3C64XX_GPN(5), 1);
msleep(1);
} else {
gpio_direction_output(S3C64XX_GPF(15), 0);
gpio_direction_output(S3C64XX_GPF(13), 0);
}
}
static struct plat_lcd_data smdk6410_lcd_power_data = {
.set_power = smdk6410_lcd_power_set,
};
static struct platform_device smdk6410_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdk6410_lcd_power_data,
};
static struct s3c_fb_pd_win smdk6410_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &smdk6410_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
&s3c_device_hsmmc1,
#endif
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&smdk6410_lcd_powerdev,
};
static struct i2c_board_info i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("WM8580", 0X1b), },
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
};
static void __init smdk6410_map_io(void)
{
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
}
static void __init smdk6410_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}
MACHINE_START(SMDK6410, "SMDK6410")
/* Maintainer: Ben Dooks <ben@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = smdk6410_map_io,
.init_machine = smdk6410_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c6410/setup-sdhci.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <mach/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
};
void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPG(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
}
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything acording to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}
arch/arm/plat-s3c/Kconfig
View file @ fdb0a1a6
......@@ -6,8 +6,8 @@
config PLAT_S3C
bool
depends on ARCH_S3C2410
default y if ARCH_S3C2410
depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
default y
select NO_IOPORT
help
Base platform code for any Samsung S3C device
......@@ -16,24 +16,24 @@ config PLAT_S3C
config CPU_LLSERIAL_S3C2410_ONLY
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
......@@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET
Say y here to use the watchdog to reset the system if the
kernel decompressor detects an error during decompression.
config S3C_BOOT_UART_FORCE_FIFO
bool "Force UART FIFO on during boot process"
depends on PLAT_S3C
default y
help
Say Y here to force the UART FIFOs on during the kernel
uncompressor
comment "Power management"
config S3C2410_PM_DEBUG
......@@ -102,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT
such as the `Uncompressing...` at start time. The value of
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
# options for gpiolib support
config S3C_GPIO_SPACE
int "Space between gpio banks"
default 0
help
Add a number of spare GPIO entries between each bank for debugging
purposes. This allows any problems where an counter overflows from
one bank to another to be caught, at the expense of using a little
more memory.
config S3C_GPIO_TRACK
bool
help
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
config S3C_GPIO_PULL_UPDOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_DOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_UP
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_CFG_S3C24XX
bool
help
Internal configuration to enable S3C24XX style GPIO configuration
functions.
config S3C_GPIO_CFG_S3C64XX
bool
help
Internal configuration to enable S3C64XX style GPIO configuration
functions.
# device definitions to compile in
config S3C_DEV_HSMMC
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC code
config S3C_DEV_HSMMC1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC channel 1
config S3C_DEV_I2C1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for I2C channel 1
config S3C_DEV_FB
bool
depends on PLAT_S3C
help
Compile in platform device definition for framebuffer
arch/arm/plat-s3c/Makefile
View file @ fdb0a1a6
# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
# arch/arm/plat-s3c/Makefile
#
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-n := dummy.o
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for all Samsung SoCs
obj-y += init.o
obj-y += time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
# devices
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
arch/arm/plat-s3c/clock.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/clock.c
*
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Core clock control support
*
* Based on, and code from linux/arch/arm/mach-versatile/clock.c
**
** Copyright (C) 2004 ARM Limited.
** Written by Deep Blue Solutions Limited.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
/* clock information */
static LIST_HEAD(clocks);
/* We originally used an mutex here, but some contexts (see resume)
* are calling functions such as clk_set_parent() with IRQs disabled
* causing an BUG to be triggered.
*/
DEFINE_SPINLOCK(clocks_lock);
/* enable and disable calls for use with the clk struct */
static int clk_null_enable(struct clk *clk, int enable)
{
return 0;
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p;
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
spin_lock(&clocks_lock);
list_for_each_entry(p, &clocks, list) {
if (p->id == idno &&
strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
/* check for the case where a device was supplied, but the
* clock that was being searched for is not device specific */
if (IS_ERR(clk)) {
list_for_each_entry(p, &clocks, list) {
if (p->id == -1 && strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
}
spin_unlock(&clocks_lock);
return clk;
}
void clk_put(struct clk *clk)
{
module_put(clk->owner);
}
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return -EINVAL;
clk_enable(clk->parent);
spin_lock(&clocks_lock);
if ((clk->usage++) == 0)
(clk->enable)(clk, 1);
spin_unlock(&clocks_lock);
return 0;
}
void clk_disable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return;
spin_lock(&clocks_lock);
if ((--clk->usage) == 0)
(clk->enable)(clk, 0);
spin_unlock(&clocks_lock);
clk_disable(clk->parent);
}
unsigned long clk_get_rate(struct clk *clk)
{
if (IS_ERR(clk))
return 0;
if (clk->rate != 0)
return clk->rate;
if (clk->get_rate != NULL)
return (clk->get_rate)(clk);
if (clk->parent != NULL)
return clk_get_rate(clk->parent);
return clk->rate;
}
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (!IS_ERR(clk) && clk->round_rate)
return (clk->round_rate)(clk, rate);
return rate;
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (IS_ERR(clk))
return -EINVAL;
/* We do not default just do a clk->rate = rate as
* the clock may have been made this way by choice.
*/
WARN_ON(clk->set_rate == NULL);
if (clk->set_rate == NULL)
return -EINVAL;
spin_lock(&clocks_lock);
ret = (clk->set_rate)(clk, rate);
spin_unlock(&clocks_lock);
return ret;
}
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = 0;
if (IS_ERR(clk))
return -EINVAL;
spin_lock(&clocks_lock);
if (clk->set_parent)
ret = (clk->set_parent)(clk, parent);
spin_unlock(&clocks_lock);
return ret;
}
EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);
/* base clocks */
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
struct clk clk_xtal = {
.name = "xtal",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_ext = {
.name = "ext",
.id = -1,
};
struct clk clk_epll = {
.name = "epll",
.id = -1,
};
struct clk clk_mpll = {
.name = "mpll",
.id = -1,
.set_rate = clk_default_setrate,
};
struct clk clk_upll = {
.name = "upll",
.id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
.id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_h = {
.name = "hclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_p = {
.name = "pclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_usb_bus = {
.name = "usb-bus",
.id = -1,
.rate = 0,
.parent = &clk_upll,
};
struct clk s3c24xx_uclk = {
.name = "uclk",
.id = -1,
};
/* initialise the clock system */
int s3c24xx_register_clock(struct clk *clk)
{
clk->owner = THIS_MODULE;
if (clk->enable == NULL)
clk->enable = clk_null_enable;
/* add to the list of available clocks */
/* Quick check to see if this clock has already been registered. */
BUG_ON(clk->list.prev != clk->list.next);
spin_lock(&clocks_lock);
list_add(&clk->list, &clocks);
spin_unlock(&clocks_lock);
return 0;
}
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
int fails = 0;
for (; nr_clks > 0; nr_clks--, clks++) {
if (s3c24xx_register_clock(*clks) < 0)
fails++;
}
return fails;
}
/* initalise all the clocks */
int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
clk_xtal.rate = xtal;
/* register our clocks */
if (s3c24xx_register_clock(&clk_xtal) < 0)
printk(KERN_ERR "failed to register master xtal\n");
if (s3c24xx_register_clock(&clk_mpll) < 0)
printk(KERN_ERR "failed to register mpll clock\n");
if (s3c24xx_register_clock(&clk_upll) < 0)
printk(KERN_ERR "failed to register upll clock\n");
if (s3c24xx_register_clock(&clk_f) < 0)
printk(KERN_ERR "failed to register cpu fclk\n");
if (s3c24xx_register_clock(&clk_h) < 0)
printk(KERN_ERR "failed to register cpu hclk\n");
if (s3c24xx_register_clock(&clk_p) < 0)
printk(KERN_ERR "failed to register cpu pclk\n");
return 0;
}
arch/arm/plat-s3c/dev-fb.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/dev-fb.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for framebuffer device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <plat/fb.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_fb_resource[] = {
[0] = {
.start = S3C_PA_FB,
.end = S3C_PA_FB + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD_VSYNC,
.end = IRQ_LCD_VSYNC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_LCD_FIFO,
.end = IRQ_LCD_FIFO,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_LCD_SYSTEM,
.end = IRQ_LCD_SYSTEM,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_fb = {
.name = "s3c-fb",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_fb_resource),
.resource = s3c_fb_resource,
.dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
.dev.coherent_dma_mask = 0xffffffffUL,
};
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
struct s3c_fb_platdata *npd;
if (!pd) {
printk(KERN_ERR "%s: no platform data\n", __func__);
return;
}
npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s3c_device_fb.dev.platform_data = npd;
}
arch/arm/plat-s3c/dev-hsmmc.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/dev-hsmmc.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C_PA_HSMMC0,
.end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC0,
.end = IRQ_HSMMC0,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc0 = {
.name = "s3c-sdhci",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc0_def_platdata,
},
};
void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}
arch/arm/plat-s3c/dev-hsmmc1.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc1_resource[] = {
[0] = {
.start = S3C_PA_HSMMC1,
.end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC1,
.end = IRQ_HSMMC1,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc1 = {
.name = "s3c-sdhci",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
.resource = s3c_hsmmc1_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc1_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc1_def_platdata,
},
};
void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}
arch/arm/plat-s3c/dev-i2c0.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/dev-i2c0.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 0
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC,
.end = S3C_PA_IIC + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c0 = {
.name = "s3c2410-i2c",
#ifdef CONFIG_S3C_DEV_I2C1
.id = 0,
#else
.id = -1,
#endif
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data0;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c0_cfg_gpio;
s3c_device_i2c0.dev.platform_data = npd;
}
arch/arm/plat-s3c/dev-i2c1.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/dev-i2c1.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC1,
.end = S3C_PA_IIC1 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC1,
.end = IRQ_IIC1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c1 = {
.name = "s3c2410-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data1;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c1_cfg_gpio;
s3c_device_i2c1.dev.platform_data = npd;
}
arch/arm/plat-s3c/gpio-config.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/gpio-config.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO configuration core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset;
int ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setcfg(chip, offset, config);
local_irq_restore(flags);
return ret;
}
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset, ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setpull(chip, offset, pull);
local_irq_restore(flags);
return ret;
}
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
/* Map output to 0, and SFN2 to 1 */
cfg -= 1;
if (cfg > 1)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x1 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off * 2;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
if (cfg > 3)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x3 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif
#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio >= 8)
reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup;
pup = __raw_readl(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
__raw_writel(pup, reg);
return 0;
}
s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup = __raw_readl(reg);
pup >>= shift;
pup &= 0x3;
return (__force s3c_gpio_pull_t)pup;
}
#endif
arch/arm/plat-s3c/gpio.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/gpio.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#ifdef CONFIG_S3C_GPIO_TRACK
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
{
unsigned int gpn;
int i;
gpn = chip->chip.base;
for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
s3c_gpios[gpn] = chip;
}
}
#endif /* CONFIG_S3C_GPIO_TRACK */
/* Default routines for controlling GPIO, based on the original S3C24XX
* GPIO functions which deal with the case where each gpio bank of the
* chip is as following:
*
* base + 0x00: Control register, 2 bits per gpio
* gpio n: 2 bits starting at (2*n)
* 00 = input, 01 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*/
static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
int ret;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
if (!gc->direction_input)
gc->direction_input = s3c_gpiolib_input;
if (!gc->direction_output)
gc->direction_output = s3c_gpiolib_output;
if (!gc->set)
gc->set = s3c_gpiolib_set;
if (!gc->get)
gc->get = s3c_gpiolib_get;
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add(gc);
if (ret >= 0)
s3c_gpiolib_track(chip);
}
arch/arm/plat-s3c/include/mach/io.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c/include/mach/io.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for plat-s3c based systems, such as S3C24A0
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif
arch/arm/mach-s3c2410/include/mach/vmalloc.h → arch/arm/plat-s3c/include/mach/vmalloc.h
View file @ fdb0a1a6
/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
/* arch/arm/plat-s3c/include/mach/vmalloc.h
*
* from arch/arm/mach-iop3xx/include/mach/vmalloc.h
*
......
arch/arm/plat-s3c/include/plat/adc.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c/include/plat/adc.h
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simnte.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX ADC driver information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_ADC_H
#define __ASM_PLAT_ADC_H __FILE__
struct s3c_adc_client;
extern int s3c_adc_start(struct s3c_adc_client *client,
unsigned int channel, unsigned int nr_samples);
extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned selected),
void (*conv)(unsigned d0, unsigned d1),
unsigned int is_ts);
extern void s3c_adc_release(struct s3c_adc_client *client);
#endif /* __ASM_PLAT_ADC_H */
arch/arm/plat-s3c24xx/include/plat/clock.h → arch/arm/plat-s3c/include/plat/clock.h
View file @ fdb0a1a6
/* linux/include/asm-arm/plat-s3c24xx/clock.h
* linux/arch/arm/mach-s3c2410/clock.h
/* linux/arch/arm/plat-s3c/include/plat/clock.h
*
* Copyright (c) 2004-2005 Simtec Electronics
* http://www.simtec.co.uk/products/SWLINUX/
......@@ -10,6 +9,8 @@
* published by the Free Software Foundation.
*/
#include <linux/spinlock.h>
struct clk {
struct list_head list;
struct module *owner;
......@@ -44,21 +45,44 @@ extern struct clk clk_h;
extern struct clk clk_p;
extern struct clk clk_mpll;
extern struct clk clk_upll;
extern struct clk clk_epll;
extern struct clk clk_xtal;
extern struct clk clk_ext;
/* S3C64XX specific clocks */
extern struct clk clk_27m;
extern struct clk clk_48m;
/* exports for arch/arm/mach-s3c2410
*
* Please DO NOT use these outside of arch/arm/mach-s3c2410
*/
extern struct mutex clocks_mutex;
extern spinlock_t clocks_lock;
extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
extern int s3c24xx_register_clock(struct clk *clk);
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
extern int s3c24xx_setup_clocks(unsigned long xtal,
unsigned long fclk,
unsigned long hclk,
unsigned long pclk);
extern int s3c24xx_register_baseclocks(unsigned long xtal);
extern void s3c64xx_register_clocks(void);
extern void s3c24xx_setup_clocks(unsigned long fclk,
unsigned long hclk,
unsigned long pclk);
extern void s3c2410_setup_clocks(void);
extern void s3c2412_setup_clocks(void);
extern void s3c244x_setup_clocks(void);
extern void s3c2443_setup_clocks(void);
/* S3C64XX specific functions and clocks */
extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
/* Init for pwm clock code */
extern void s3c_pwmclk_init(void);
arch/arm/plat-s3c/include/plat/cpu-freq.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
*
* Copyright (c) 2006,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C CPU frequency scaling support - driver and board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/cpufreq.h>
struct s3c_cpufreq_info;
struct s3c_cpufreq_board;
struct s3c_iotimings;
struct s3c_freq {
unsigned long fclk;
unsigned long armclk;
unsigned long hclk_tns; /* in 10ths of ns */
unsigned long hclk;
unsigned long pclk;
};
/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
* notification can use this information that is not provided by just
* having the core frequency alone.
*/
struct s3c_cpufreq_freqs {
struct cpufreq_freqs freqs;
struct s3c_freq old;
struct s3c_freq new;
};
#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
struct s3c_clkdivs {
int p_divisor; /* fclk / pclk */
int h_divisor; /* fclk / hclk */
int arm_divisor; /* not all cpus have this. */
unsigned char dvs; /* using dvs mode to arm. */
};
#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
struct s3c_pllval {
unsigned long freq;
unsigned long pll_reg;
};
struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_pllval pll;
struct s3c_clkdivs divs;
struct s3c_cpufreq_info *info; /* for core, not drivers */
struct s3c_cpufreq_board *board;
};
/* s3c_cpufreq_board
*
* per-board configuraton information, such as memory refresh and
* how to initialise IO timings.
*/
struct s3c_cpufreq_board {
unsigned int refresh; /* refresh period in ns */
unsigned int auto_io:1; /* automatically init io timings. */
unsigned int need_io:1; /* set if needs io timing support. */
/* any non-zero field in here is taken as an upper limit. */
struct s3c_freq max; /* frequency limits */
};
/* Things depending on frequency scaling. */
#ifdef CONFIG_CPU_FREQ_S3C
#define __init_or_cpufreq
#else
#define __init_or_cpufreq __init
#endif
/* Board functions */
#ifdef CONFIG_CPU_FREQ_S3C
extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
#else
static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
{
return 0;
}
#endif /* CONFIG_CPU_FREQ_S3C */
arch/arm/plat-s3c24xx/include/plat/cpu.h → arch/arm/plat-s3c/include/plat/cpu.h
View file @ fdb0a1a6
/* linux/include/asm-arm/plat-s3c24xx/cpu.h
/* linux/arch/arm/plat-s3c/include/plat/cpu.h
*
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
......@@ -18,7 +18,7 @@
#define MHZ (1000*1000)
#endif
#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/* forward declaration */
struct s3c24xx_uart_resources;
......@@ -26,11 +26,28 @@ struct platform_device;
struct s3c2410_uartcfg;
struct map_desc;
/* per-cpu initialisation function table. */
struct cpu_table {
unsigned long idcode;
unsigned long idmask;
void (*map_io)(void);
void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
void (*init_clocks)(int xtal);
int (*init)(void);
const char *name;
};
extern void s3c_init_cpu(unsigned long idcode,
struct cpu_table *cpus, unsigned int cputab_size);
/* core initialisation functions */
extern void s3c24xx_init_irq(void);
extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c/include/plat/debug-macro.S
View file @ fdb0a1a6
......@@ -20,7 +20,7 @@
.endm
#ifndef fifo_level
#define fifo_level fifo_level_s3c2410
#define fifo_level fifo_level_s3c2440
#endif
.macro fifo_full_s3c2440 rd, rx
......
arch/arm/plat-s3c24xx/include/plat/devs.h → arch/arm/plat-s3c/include/plat/devs.h
View file @ fdb0a1a6
......@@ -17,21 +17,26 @@ struct s3c24xx_uart_resources {
};
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
extern struct platform_device *s3c24xx_uart_devs[];
extern struct platform_device *s3c24xx_uart_src[];
extern struct platform_device s3c_device_timer[];
extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
extern struct platform_device s3c_device_i2c;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_hsmmc0;
extern struct platform_device s3c_device_hsmmc1;
extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;
......
arch/arm/plat-s3c/include/plat/fb.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - FB platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_FB_H
#define __PLAT_S3C_FB_H __FILE__
/**
* struct s3c_fb_pd_win - per window setup data
* @win_mode: The display parameters to initialise (not for window 0)
* @virtual_x: The virtual X size.
* @virtual_y: The virtual Y size.
*/
struct s3c_fb_pd_win {
struct fb_videomode win_mode;
unsigned short default_bpp;
unsigned short max_bpp;
unsigned short virtual_x;
unsigned short virtual_y;
};
/**
* struct s3c_fb_platdata - S3C driver platform specific information
* @setup_gpio: Setup the external GPIO pins to the right state to transfer
* the data from the display system to the connected display
* device.
* @vidcon0: The base vidcon0 values to control the panel data format.
* @vidcon1: The base vidcon1 values to control the panel data output.
* @win: The setup data for each hardware window, or NULL for unused.
* @display_mode: The LCD output display mode.
*
* The platform data supplies the video driver with all the information
* it requires to work with the display(s) attached to the machine. It
* controls the initial mode, the number of display windows (0 is always
* the base framebuffer) that are initialised etc.
*
*/
struct s3c_fb_platdata {
void (*setup_gpio)(void);
struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
u32 vidcon0;
u32 vidcon1;
};
/**
* s3c_fb_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */
arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration helper definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This is meant for core cpu support, machine or other driver files
* should not be including this header.
*/
#ifndef __PLAT_GPIO_CFG_HELPERS_H
#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
/* As a note, all gpio configuration functions are entered exclusively, either
* with the relevant lock held or the system prevented from doing anything else
* by disabling interrupts.
*/
static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int config)
{
return (chip->config->set_config)(chip, off, config);
}
static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
return (chip->config->set_pull)(chip, off, pull);
}
/**
* s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has two bits of configuration per gpio, which have the following
* functions:
* 00 = input
* 01 = output
* 1x = special function
*/
extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has one bit of configuration for the gpio, where setting the bit
* means the pin is in special function mode and unset means output.
*/
extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependant on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a seperate set of functions for
* each case.
*/
extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/* Pull-{up,down} resistor controls.
*
* S3C2410,S3C2440,S3C24A0 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]
*/
/**
* s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-up resistor.
*/
extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
* @chip: The gpio chip that is being configured
* @off: The offset for the GPIO being configured
* @param: pull: The pull mode being requested
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-down resistor.
*/
extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = No pull resistor connected
* 01 = Pull-up resistor connected
* 10 = Pull-down resistor connected
*/
extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
* @chip: The gpio chip that the GPIO pin belongs to
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off);
/**
* s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = Pull-up resistor connected
* 10 = Pull-down resistor connected
* x1 = No pull up resistor
*/
extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
* @chip: The gpio chip that the GPIO pin belongs to.
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off);
#endif /* __PLAT_GPIO_CFG_HELPERS_H */
arch/arm/plat-s3c/include/plat/gpio-cfg.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
/* Note, this interface is being added to the s3c64xx arch first and will
* be added to the s3c24xx systems later.
*/
#ifndef __PLAT_GPIO_CFG_H
#define __PLAT_GPIO_CFG_H __FILE__
typedef unsigned int __bitwise__ s3c_gpio_pull_t;
/* forward declaration if gpio-core.h hasn't been included */
struct s3c_gpio_chip;
/**
* struct s3c_gpio_cfg GPIO configuration
* @cfg_eint: Configuration setting when used for external interrupt source
* @get_pull: Read the current pull configuration for the GPIO
* @set_pull: Set the current pull configuraiton for the GPIO
* @set_config: Set the current configuration for the GPIO
* @get_config: Read the current configuration for the GPIO
*
* Each chip can have more than one type of GPIO bank available and some
* have different capabilites even when they have the same control register
* layouts. Provide an point to vector control routine and provide any
* per-bank configuration information that other systems such as the
* external interrupt code will need.
*/
struct s3c_gpio_cfg {
unsigned int cfg_eint;
s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
s3c_gpio_pull_t pull);
unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
unsigned config);
};
#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
/* Defines for generic pin configurations */
#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
#define s3c_gpio_is_cfg_special(_cfg) \
(((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
/**
* s3c_gpio_cfgpin() - Change the GPIO function of a pin.
* @pin pin The pin number to configure.
* @pin to The configuration for the pin's function.
*
* Configure which function is actually connected to the external
* pin, such as an gpio input, output or some form of special function
* connected to an internal peripheral block.
*/
extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
/* Define values for the pull-{up,down} available for each gpio pin.
*
* These values control the state of the weak pull-{up,down} resistors
* available on most pins on the S3C series. Not all chips support both
* up or down settings, and it may be dependant on the chip that is being
* used to whether the particular mode is available.
*/
#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
/**
* s3c_gpio_setpull() - set the state of a gpio pin pull resistor
* @pin: The pin number to configure the pull resistor.
* @pull: The configuration for the pull resistor.
*
* This function sets the state of the pull-{up,down} resistor for the
* specified pin. It will return 0 if successfull, or a negative error
* code if the pin cannot support the requested pull setting.
*/
extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull() - get the pull resistor state of a gpio pin
* @pin: The pin number to get the settings for
*
* Read the pull resistor value for the specified pin.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
#endif /* __PLAT_GPIO_CFG_H */
arch/arm/plat-s3c/include/plat/gpio-core.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Define the core gpiolib support functions that the s3c platforms may
* need to extend or change depending on the hardware and the s3c chip
* selected at build or found at run time.
*
* These definitions are not intended for driver inclusion, there is
* nothing here that should not live outside the platform and core
* specific code.
*/
struct s3c_gpio_cfg;
/**
* struct s3c_gpio_chip - wrapper for specific implementation of gpio
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
*/
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg *config;
void __iomem *base;
};
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c_gpio_chip, chip);
}
/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
* @chip: The chip to register
*
* This is a wrapper to gpiochip_add() that takes our specific gpio chip
* information and makes the necessary alterations for the platform and
* notes the information for use with the configuration systems and any
* other parts of the system.
*/
extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
* for use with the configuration calls, and other parts of the s3c gpiolib
* support code.
*
* Not all s3c support code will need this, as some configurations of cpu
* may only support one or two different configuration options and have an
* easy gpio to s3c_gpio_chip mapping function. If this is the case, then
* the machine support file should provide its own s3c_gpiolib_getchip()
* and any other necessary functions.
*/
#ifdef CONFIG_S3C_GPIO_TRACK
extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
{
return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
}
#else
/* machine specific code should provide s3c_gpiolib_getchip */
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
#endif
arch/arm/plat-s3c/include/plat/iic-core.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/mach-s3c2410/include/mach/iic-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IIC_CORE_H
#define __ASM_ARCH_IIC_CORE_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
/* re-define device name depending on support. */
static inline void s3c_i2c0_setname(char *name)
{
/* currently this device is always compiled in */
s3c_device_i2c0.name = name;
}
static inline void s3c_i2c1_setname(char *name)
{
#ifdef CONFIG_S3C_DEV_I2C1
s3c_device_i2c1.name = name;
#endif
}
#endif /* __ASM_ARCH_IIC_H */
arch/arm/plat-s3c/include/plat/iic.h
View file @ fdb0a1a6
......@@ -28,6 +28,30 @@ struct s3c2410_platform_i2c {
unsigned long max_freq; /* max frequency for the bus */
unsigned long min_freq; /* min frequency for the bus */
unsigned int sda_delay; /* pclks (s3c2440 only) */
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARCH_IIC_H */
arch/arm/plat-s3c/include/plat/regs-fb.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c/include/plat/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards into the S3C2416, S3C2450 and the
* S3C64XX series such as the S3C6400 and S3C6410.
*
* The file does not contain the cpu specific items which are based on
* whichever architecture is selected, it only contains the core of the
* register set. See <mach/regs-fb.h> to get the specifics.
*
* Note, we changed to using regs-fb.h as it avoids any clashes with
* the original regs-lcd.h so out of the way of regs-lcd.h as well as
* indicating the newer block is much more than just an LCD interface.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Please do not include this file directly, use <mach/regs-fb.h> to
* ensure all the localised SoC support is included as necessary.
*/
/* VIDCON0 */
#define VIDCON0 (0x00)
#define VIDCON0_INTERLACE (1 << 29)
#define VIDCON0_VIDOUT_MASK (0x3 << 26)
#define VIDCON0_VIDOUT_SHIFT (26)
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT (23)
#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
#define VIDCON0_L0_DATA_MASK (0x7 << 20)
#define VIDCON0_L0_DATA_SHIFT (20)
#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
#define VIDCON0_PNRMODE_MASK (0x3 << 17)
#define VIDCON0_PNRMODE_SHIFT (17)
#define VIDCON0_PNRMODE_RGB (0x0 << 17)
#define VIDCON0_PNRMODE_BGR (0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
#define VIDCON0_CLKVALUP (1 << 16)
#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
#define VIDCON0_CLKVAL_F_SHIFT (6)
#define VIDCON0_CLKVAL_F_LIMIT (0xff)
#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
#define VIDCON0_VLCKFREE (1 << 5)
#define VIDCON0_CLKDIR (1 << 4)
#define VIDCON0_CLKSEL_MASK (0x3 << 2)
#define VIDCON0_CLKSEL_SHIFT (2)
#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
#define VIDCON0_CLKSEL_LCD (0x1 << 2)
#define VIDCON0_CLKSEL_27M (0x3 << 2)
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
#define VIDCON1 (0x04)
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT (16)
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
#define VIDCON1_VSTATUS_MASK (0x3 << 13)
#define VIDCON1_VSTATUS_SHIFT (13)
#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
#define VIDCON1_INV_VCLK (1 << 7)
#define VIDCON1_INV_HSYNC (1 << 6)
#define VIDCON1_INV_VSYNC (1 << 5)
#define VIDCON1_INV_VDEN (1 << 4)
/* VIDCON2 */
#define VIDCON2 (0x08)
#define VIDCON2_EN601 (1 << 23)
#define VIDCON2_TVFMTSEL_SW (1 << 14)
#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
#define VIDCON2_TVFMTSEL1_SHIFT (12)
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
/* VIDTCON0 */
#define VIDTCON0_VBPDE_MASK (0xff << 24)
#define VIDTCON0_VBPDE_SHIFT (24)
#define VIDTCON0_VBPDE_LIMIT (0xff)
#define VIDTCON0_VBPDE(_x) ((_x) << 24)
#define VIDTCON0_VBPD_MASK (0xff << 16)
#define VIDTCON0_VBPD_SHIFT (16)
#define VIDTCON0_VBPD_LIMIT (0xff)
#define VIDTCON0_VBPD(_x) ((_x) << 16)
#define VIDTCON0_VFPD_MASK (0xff << 8)
#define VIDTCON0_VFPD_SHIFT (8)
#define VIDTCON0_VFPD_LIMIT (0xff)
#define VIDTCON0_VFPD(_x) ((_x) << 8)
#define VIDTCON0_VSPW_MASK (0xff << 0)
#define VIDTCON0_VSPW_SHIFT (0)
#define VIDTCON0_VSPW_LIMIT (0xff)
#define VIDTCON0_VSPW(_x) ((_x) << 0)
/* VIDTCON1 */
#define VIDTCON1_VFPDE_MASK (0xff << 24)
#define VIDTCON1_VFPDE_SHIFT (24)
#define VIDTCON1_VFPDE_LIMIT (0xff)
#define VIDTCON1_VFPDE(_x) ((_x) << 24)
#define VIDTCON1_HBPD_MASK (0xff << 16)
#define VIDTCON1_HBPD_SHIFT (16)
#define VIDTCON1_HBPD_LIMIT (0xff)
#define VIDTCON1_HBPD(_x) ((_x) << 16)
#define VIDTCON1_HFPD_MASK (0xff << 8)
#define VIDTCON1_HFPD_SHIFT (8)
#define VIDTCON1_HFPD_LIMIT (0xff)
#define VIDTCON1_HFPD(_x) ((_x) << 8)
#define VIDTCON1_HSPW_MASK (0xff << 0)
#define VIDTCON1_HSPW_SHIFT (0)
#define VIDTCON1_HSPW_LIMIT (0xff)
#define VIDTCON1_HSPW(_x) ((_x) << 0)
#define VIDTCON2 (0x18)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT (0)
#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
/* WINCONx */
#define WINCONx_BITSWP (1 << 18)
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT (9)
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
#define WINCONx_ENWIN (1 << 0)
#define WINCON0_BPPMODE_MASK (0xf << 2)
#define WINCON0_BPPMODE_SHIFT (2)
#define WINCON0_BPPMODE_1BPP (0x0 << 2)
#define WINCON0_BPPMODE_2BPP (0x1 << 2)
#define WINCON0_BPPMODE_4BPP (0x2 << 2)
#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BLD_PIX (1 << 6)
#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
#define WINCON1_BPPMODE_SHIFT (2)
#define WINCON1_BPPMODE_1BPP (0x0 << 2)
#define WINCON1_BPPMODE_2BPP (0x1 << 2)
#define WINCON1_BPPMODE_4BPP (0x2 << 2)
#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
#define VIDISD14C_ALPHA0_G_SHIFT (16)
#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
#define VIDISD14C_ALPHA0_B_SHIFT (12)
#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
#define VIDISD14C_ALPHA1_R_SHIFT (8)
#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
#define VIDISD14C_ALPHA1_G_SHIFT (4)
#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
#define VIDISD14C_ALPHA1_B_SHIFT (0)
#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
/* Interrupt controls and status */
#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
#define VIDINTCON0_INT_I80IFDONE (1 << 17)
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
#define VIDINTCON0_FRAMESEL0_SHIFT (15)
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
#define VIDINTCON0_FRAMESEL1 (1 << 14)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
#define VIDINTCON0_FIFIOSEL_SHIFT (5)
#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
#define VIDINTCON0_INT_FIFO_SHIFT (0)
#define VIDINTCON0_INT_ENABLE (1 << 0)
#define VIDINTCON1 (0x134)
#define VIDINTCON1_INT_I180 (1 << 2)
#define VIDINTCON1_INT_FRAME (1 << 1)
#define VIDINTCON1_INT_FIFO (1 << 0)
/* Window colour-key control registers */
#define WxKEYCON0_KEYBL_EN (1 << 26)
#define WxKEYCON0_KEYEN_F (1 << 25)
#define WxKEYCON0_DIRCON (1 << 24)
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
#define WxKEYCON0_COMPKEY_SHIFT (0)
#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
#define WxKEYCON1_COLVAL_SHIFT (0)
#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
/* Window blanking (MAP) */
#define WINxMAP_MAP (1 << 24)
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
#define WINxMAP_MAP_COLOUR_SHIFT (0)
#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
#define WPALCON_PAL_UPDATE (1 << 9)
#define WPALCON_W1PAL_MASK (0x7 << 3)
#define WPALCON_W1PAL_SHIFT (3)
#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
#define WPALCON_W1PAL_24BPP (0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
#define WPALCON_W1PAL_18BPP (0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
#define WPALCON_W0PAL_MASK (0x7 << 0)
#define WPALCON_W0PAL_SHIFT (0)
#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
#define WPALCON_W0PAL_24BPP (0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
#define WPALCON_W0PAL_18BPP (0x4 << 0)
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
arch/arm/plat-s3c/include/plat/regs-irqtype.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C - IRQ detection types.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
* the S3C64XX
*/
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
#define S3C2410_EXTINT_FALLEDGE (0x02)
#define S3C2410_EXTINT_RISEEDGE (0x04)
#define S3C2410_EXTINT_BOTHEDGE (0x06)
arch/arm/plat-s3c/include/plat/regs-sdhci.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_REGS_H
#define __PLAT_S3C_SDHCI_REGS_H __FILE__
#define S3C_SDHCI_CONTROL2 (0x80)
#define S3C_SDHCI_CONTROL3 (0x84)
#define S3C64XX_SDHCI_CONTROL4 (0x8C)
#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
#endif /* __PLAT_S3C_SDHCI_REGS_H */
arch/arm/plat-s3c/include/plat/regs-serial.h
View file @ fdb0a1a6
......@@ -77,6 +77,12 @@
#define S3C2440_UCON_FCLK (3<<10)
#define S3C2443_UCON_EPLL (3<<10)
#define S3C6400_UCON_CLKMASK (3<<10)
#define S3C6400_UCON_PCLK (0<<10)
#define S3C6400_UCON_PCLK2 (2<<10)
#define S3C6400_UCON_UCLK0 (1<<10)
#define S3C6400_UCON_UCLK1 (3<<10)
#define S3C2440_UCON2_FCLK_EN (1<<15)
#define S3C2440_UCON0_DIVMASK (15 << 12)
#define S3C2440_UCON1_DIVMASK (15 << 12)
......@@ -149,6 +155,14 @@
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)
/* UFSTAT S3C24A0 */
#define S3C24A0_UFSTAT_TXFULL (1 << 14)
#define S3C24A0_UFSTAT_RXFULL (1 << 6)
#define S3C24A0_UFSTAT_TXMASK (63 << 8)
#define S3C24A0_UFSTAT_TXSHIFT (8)
#define S3C24A0_UFSTAT_RXMASK (63)
#define S3C24A0_UFSTAT_RXSHIFT (0)
/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL (1<<14)
#define S3C2440_UFSTAT_RXFULL (1<<6)
......@@ -224,7 +238,7 @@ struct s3c2410_uartcfg {
* or platform_add_device() before the console_initcall()
*/
extern struct platform_device *s3c24xx_uart_devs[3];
extern struct platform_device *s3c24xx_uart_devs[4];
#endif /* __ASSEMBLY__ */
......
arch/arm/plat-s3c/include/plat/regs-timer.h
View file @ fdb0a1a6
......@@ -10,7 +10,6 @@
* S3C2410 Timer configuration
*/
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H
......@@ -21,6 +20,8 @@
#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
#define S3C2410_TCON S3C_TIMERREG(0x08)
#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
......@@ -72,6 +73,14 @@
#define S3C2410_TCFG1_MUX_TCLK (4<<0)
#define S3C2410_TCFG1_MUX_MASK (15<<0)
#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
#define S3C64XX_TCFG1_MUX_MASK (15<<0)
#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
/* for each timer, we have an count buffer, an compare buffer and
......
arch/arm/plat-s3c/include/plat/sdhci.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
struct platform_device;
struct mmc_host;
struct mmc_card;
struct mmc_ios;
/**
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cfg_gpio: Configure the GPIO for a specific card bit-width
* @cfg_card: Configure the interface for a specific card and speed. This
* is necessary the controllers and/or GPIO blocks require the
* changing of driver-strength and other controls dependant on
* the card and speed of operation.
*
* Initialisation data specific to either the machine or the platform
* for the device driver to use or call-back when configuring gpio or
* card speed information.
*/
struct s3c_sdhci_platdata {
unsigned int max_width;
unsigned int host_caps;
char **clocks; /* set of clock sources */
void (*cfg_gpio)(struct platform_device *dev, int width);
void (*cfg_card)(struct platform_device *dev,
void __iomem *regbase,
struct mmc_ios *ios,
struct mmc_card *card);
};
/**
* s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
* @pd: Platform data to register to device.
*
* Register the given platform data for use withe S3C SDHCI device.
* The call will copy the platform data, so the board definitions can
* make the structure itself __initdata.
*/
extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
/* Default platform data, exported so that per-cpu initialisation can
* set the correct one when there are more than one cpu type selected.
*/
extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
/* Helper function availablity */
#ifdef CONFIG_S3C6410_SETUP_SDHCI
extern char *s3c6410_hsmmc_clksrcs[4];
extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s3c6410_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6410_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C6410_SETUP_SDHCI */
#endif /* __PLAT_S3C_SDHCI_H */
arch/arm/plat-s3c/include/plat/uncompress.h
View file @ fdb0a1a6
......@@ -37,7 +37,7 @@ static void arch_detect_cpu(void);
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
static __inline__ void
uart_wr(unsigned int reg, unsigned int val)
......@@ -139,6 +139,28 @@ static void arch_decomp_error(const char *x)
static void error(char *err);
#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
static inline void arch_enable_uart_fifo(void)
{
u32 fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
fifocon |= S3C2410_UFCON_RESETBOTH;
uart_wr(S3C2410_UFCON, fifocon);
/* wait for fifo reset to complete */
while (1) {
fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_RESETBOTH))
break;
}
}
}
#else
#define arch_enable_uart_fifo() do { } while(0)
#endif
static void
arch_decomp_setup(void)
{
......@@ -149,6 +171,12 @@ arch_decomp_setup(void)
arch_detect_cpu();
arch_decomp_wdog_start();
/* Enable the UART FIFOs if they where not enabled and our
* configuration says we should turn them on.
*/
arch_enable_uart_fifo();
}
......
arch/arm/plat-s3c/init.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c/init.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series CPU initialisation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/regs-serial.h>
static struct cpu_table *cpu;
static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
struct cpu_table *tab,
unsigned int count)
{
for (; count != 0; count--, tab++) {
if ((idcode & tab->idmask) == tab->idcode)
return tab;
}
return NULL;
}
void __init s3c_init_cpu(unsigned long idcode,
struct cpu_table *cputab, unsigned int cputab_size)
{
cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
if (cpu == NULL) {
printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
panic("Unknown S3C24XX CPU");
}
printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
if (cpu->map_io == NULL || cpu->init == NULL) {
printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
panic("Unsupported Samsung CPU");
}
cpu->map_io();
}
/* s3c24xx_init_clocks
*
* Initialise the clock subsystem and associated information from the
* given master crystal value.
*
* xtal = 0 -> use default PLL crystal value (normally 12MHz)
* != 0 -> PLL crystal value in Hz
*/
void __init s3c24xx_init_clocks(int xtal)
{
if (xtal == 0)
xtal = 12*1000*1000;
if (cpu == NULL)
panic("s3c24xx_init_clocks: no cpu setup?\n");
if (cpu->init_clocks == NULL)
panic("s3c24xx_init_clocks: cpu has no clock init\n");
else
(cpu->init_clocks)(xtal);
}
/* uart management */
static int nr_uarts __initdata = 0;
static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
/* s3c24xx_init_uartdevs
*
* copy the specified platform data and configuration into our central
* set of devices, before the data is thrown away after the init process.
*
* This also fills in the array passed to the serial driver for the
* early initialisation of the console.
*/
void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
int uart;
memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
platdev = s3c24xx_uart_src[cfgptr->hwport];
resp = res + cfgptr->hwport;
s3c24xx_uart_devs[uart] = platdev;
platdev->name = name;
platdev->resource = resp->resources;
platdev->num_resources = resp->nr_resources;
platdev->dev.platform_data = cfgptr;
}
nr_uarts = no;
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
if (cpu == NULL)
return;
if (cpu->init_uarts == NULL) {
printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
} else
(cpu->init_uarts)(cfg, no);
}
static int __init s3c_arch_init(void)
{
int ret;
// do the correct init for cpu
if (cpu == NULL)
panic("s3c_arch_init: NULL cpu\n");
ret = (cpu->init)();
if (ret != 0)
return ret;
ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
return ret;
}
arch_initcall(s3c_arch_init);
arch/arm/plat-s3c24xx/pwm-clock.c → arch/arm/plat-s3c/pwm-clock.c
View file @ fdb0a1a6
......@@ -14,20 +14,20 @@
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/regs-timer.h>
#include <mach/pwm-clock.h>
/* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers.
......@@ -73,11 +73,13 @@
* tclk -------------------------/
*/
static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
static struct clk clk_timer_scaler[];
static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
{
unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
if (clk->id == 1) {
if (clk == &clk_timer_scaler[1]) {
tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
} else {
......@@ -87,18 +89,61 @@ static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
return clk_get_rate(clk->parent) / (tcfg0 + 1);
}
/* TODO - add set rate calls. */
static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
unsigned long rate)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
unsigned long divisor = parent_rate / rate;
if (divisor > 256)
divisor = 256;
else if (divisor < 2)
divisor = 2;
return parent_rate / divisor;
}
static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
unsigned long tcfg0;
unsigned long divisor;
unsigned long flags;
divisor = clk_get_rate(clk->parent) / round;
divisor--;
local_irq_save(flags);
tcfg0 = __raw_readl(S3C2410_TCFG0);
if (clk == &clk_timer_scaler[1]) {
tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
} else {
tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
tcfg0 |= divisor;
}
__raw_writel(tcfg0, S3C2410_TCFG0);
local_irq_restore(flags);
return 0;
}
static struct clk clk_timer_scaler[] = {
[0] = {
.name = "pwm-scaler0",
.id = -1,
.get_rate = clk_pwm_scaler_getrate,
.get_rate = clk_pwm_scaler_get_rate,
.set_rate = clk_pwm_scaler_set_rate,
.round_rate = clk_pwm_scaler_round_rate,
},
[1] = {
.name = "pwm-scaler1",
.id = -1,
.get_rate = clk_pwm_scaler_getrate,
.get_rate = clk_pwm_scaler_get_rate,
.set_rate = clk_pwm_scaler_set_rate,
.round_rate = clk_pwm_scaler_round_rate,
},
};
......@@ -123,11 +168,6 @@ static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
return container_of(clk, struct pwm_tdiv_clk, clk);
}
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
}
static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
{
unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
......@@ -136,7 +176,7 @@ static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
if (pwm_cfg_src_is_tclk(tcfg1))
divisor = to_tdiv(clk)->divisor;
else
divisor = tcfg_to_divisor(tcfg1);
......@@ -153,7 +193,9 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
parent_rate = clk_get_rate(clk->parent);
divisor = parent_rate / rate;
if (divisor <= 2)
if (divisor <= 1 && pwm_tdiv_has_div1())
divisor = 1;
else if (divisor <= 2)
divisor = 2;
else if (divisor <= 4)
divisor = 4;
......@@ -167,25 +209,7 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
{
unsigned long bits;
switch (divclk->divisor) {
case 2:
bits = S3C2410_TCFG1_MUX_DIV2;
break;
case 4:
bits = S3C2410_TCFG1_MUX_DIV4;
break;
case 8:
bits = S3C2410_TCFG1_MUX_DIV8;
break;
case 16:
default:
bits = S3C2410_TCFG1_MUX_DIV16;
break;
}
return bits;
return pwm_tdiv_div_bits(divclk->divisor);
}
static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
......@@ -226,7 +250,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
/* Update the current MUX settings if we are currently
* selected as the clock source for this clock. */
if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
if (!pwm_cfg_src_is_tclk(tcfg1))
clk_pwm_tdiv_update(divclk);
return 0;
......@@ -313,7 +337,7 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
unsigned long shift = S3C2410_TCFG1_SHIFT(id);
if (parent == s3c24xx_pwmclk_tclk(id))
bits = S3C2410_TCFG1_MUX_TCLK << shift;
bits = S3C_TCFG1_MUX_TCLK << shift;
else if (parent == s3c24xx_pwmclk_tdiv(id))
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
else
......@@ -375,7 +399,7 @@ static __init int clk_pwm_tin_register(struct clk *pwm)
tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
if (pwm_cfg_src_is_tclk(tcfg1))
parent = s3c24xx_pwmclk_tclk(id);
else
parent = s3c24xx_pwmclk_tdiv(id);
......@@ -383,7 +407,16 @@ static __init int clk_pwm_tin_register(struct clk *pwm)
return clk_set_parent(pwm, parent);
}
static __init int s3c24xx_pwmclk_init(void)
/**
* s3c_pwmclk_init() - initialise pwm clocks
*
* Initialise and register the clocks which provide the inputs for the
* pwm timer blocks.
*
* Note, this call is required by the time core, so must be called after
* the base clocks are added and before any of the initcalls are run.
*/
__init void s3c_pwmclk_init(void)
{
struct clk *clk_timers;
unsigned int clk;
......@@ -392,7 +425,7 @@ static __init int s3c24xx_pwmclk_init(void)
clk_timers = clk_get(NULL, "timers");
if (IS_ERR(clk_timers)) {
printk(KERN_ERR "%s: no parent clock\n", __func__);
return -EINVAL;
return;
}
for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
......@@ -400,7 +433,7 @@ static __init int s3c24xx_pwmclk_init(void)
ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
goto err;
return;
}
}
......@@ -408,7 +441,7 @@ static __init int s3c24xx_pwmclk_init(void)
ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pww tclk%d\n", clk);
goto err;
return;
}
}
......@@ -416,7 +449,7 @@ static __init int s3c24xx_pwmclk_init(void)
ret = clk_pwm_tdiv_register(clk);
if (ret < 0) {
printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
goto err;
return;
}
}
......@@ -424,14 +457,7 @@ static __init int s3c24xx_pwmclk_init(void)
ret = clk_pwm_tin_register(&clk_tin[clk]);
if (ret < 0) {
printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
goto err;
return;
}
}
return 0;
err:
return ret;
}
arch_initcall(s3c24xx_pwmclk_init);
arch/arm/plat-s3c24xx/time.c → arch/arm/plat-s3c/time.c
View file @ fdb0a1a6
......@@ -26,6 +26,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/system.h>
#include <asm/leds.h>
......@@ -36,6 +37,7 @@
#include <plat/regs-timer.h>
#include <mach/regs-irq.h>
#include <asm/mach/time.h>
#include <mach/tick.h>
#include <plat/clock.h>
#include <plat/cpu.h>
......@@ -43,6 +45,10 @@
static unsigned long timer_startval;
static unsigned long timer_usec_ticks;
#ifndef TICK_MAX
#define TICK_MAX (0xffff)
#endif
#define TIMER_USEC_SHIFT 16
/* we use the shifted arithmetic to work out the ratio of timer ticks
......@@ -91,23 +97,19 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
* IRQs are disabled before entering here from do_gettimeofday()
*/
#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
static unsigned long s3c2410_gettimeoffset (void)
{
unsigned long tdone;
unsigned long irqpend;
unsigned long tval;
/* work out how many ticks have gone since last timer interrupt */
tval = __raw_readl(S3C2410_TCNTO(4));
tval = __raw_readl(S3C2410_TCNTO(4));
tdone = timer_startval - tval;
/* check to see if there is an interrupt pending */
irqpend = __raw_readl(S3C2410_SRCPND);
if (irqpend & SRCPND_TIMER4) {
if (s3c24xx_ostimer_pending()) {
/* re-read the timer, and try and fix up for the missed
* interrupt. Note, the interrupt may go off before the
* timer has re-loaded from wrapping.
......@@ -144,7 +146,11 @@ static struct irqaction s3c2410_timer_irq = {
machine_is_bast() || \
machine_is_vr1000() || \
machine_is_anubis() || \
machine_is_osiris() )
machine_is_osiris())
static struct clk *tin;
static struct clk *tdiv;
static struct clk *timerclk;
/*
* Set up timer interrupt, and return the current time in seconds.
......@@ -159,13 +165,7 @@ static void s3c2410_timer_setup (void)
unsigned long tcfg1;
unsigned long tcfg0;
tcnt = 0xffff; /* default value for tcnt */
/* read the current timer configuration bits */
tcon = __raw_readl(S3C2410_TCON);
tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg0 = __raw_readl(S3C2410_TCFG0);
tcnt = TICK_MAX; /* default value for tcnt */
/* configure the system for whichever machine is in use */
......@@ -174,11 +174,13 @@ static void s3c2410_timer_setup (void)
timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
tcnt = 12000000 / HZ;
tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
__raw_writel(tcfg1, S3C2410_TCFG1);
} else {
unsigned long pclk;
struct clk *clk;
struct clk *tscaler;
/* for the h1940 (and others), we use the pclk from the core
* to generate the timer values. since values around 50 to
......@@ -189,38 +191,34 @@ static void s3c2410_timer_setup (void)
* (8.45 ticks per usec)
*/
/* this is used as default if no other timer can be found */
clk = clk_get(NULL, "timers");
if (IS_ERR(clk))
panic("failed to get clock for system timer");
clk_enable(clk);
pclk = clk_get_rate(clk);
pclk = clk_get_rate(timerclk);
/* configure clock tick */
timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
tscaler = clk_get_parent(tdiv);
tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
clk_set_rate(tscaler, pclk / 3);
clk_set_rate(tdiv, pclk / 6);
clk_set_parent(tin, tdiv);
tcnt = (pclk / 6) / HZ;
tcnt = clk_get_rate(tin) / HZ;
}
tcon = __raw_readl(S3C2410_TCON);
tcfg0 = __raw_readl(S3C2410_TCFG0);
tcfg1 = __raw_readl(S3C2410_TCFG1);
/* timers reload after counting zero, so reduce the count by 1 */
tcnt--;
printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
/* check to see if timer is within 16bit range... */
if (tcnt > 0xffff) {
if (tcnt > TICK_MAX) {
panic("setup_timer: HZ is too small, cannot configure timer!");
return;
}
......@@ -247,8 +245,35 @@ static void s3c2410_timer_setup (void)
__raw_writel(tcon, S3C2410_TCON);
}
static void __init s3c2410_timer_init (void)
static void __init s3c2410_timer_resources(void)
{
struct platform_device tmpdev;
tmpdev.dev.bus = &platform_bus_type;
tmpdev.id = 4;
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
panic("failed to get clock for system timer");
clk_enable(timerclk);
if (!use_tclk1_12()) {
tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer");
tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv))
panic("failed to get pwm-tdiv clock for system timer");
}
clk_enable(tin);
}
static void __init s3c2410_timer_init(void)
{
s3c2410_timer_resources();
s3c2410_timer_setup();
setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
}
......
arch/arm/plat-s3c24xx/Kconfig
View file @ fdb0a1a6
......@@ -6,8 +6,8 @@
config PLAT_S3C24XX
bool
depends on ARCH_S3C2410
default y if ARCH_S3C2410
depends on ARCH_S3C2410 || ARCH_S3C24A0
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
help
......@@ -15,6 +15,19 @@ config PLAT_S3C24XX
if PLAT_S3C24XX
# code that is shared between a number of the s3c24xx implementations
config S3C2410_CLOCK
bool
help
Clock code for the S3C2410, and similar processors which
is currently includes the S3C2410, S3C2440, S3C2442.
config S3C24XX_DCLK
bool
help
Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
config CPU_S3C244X
bool
depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
......@@ -28,6 +41,27 @@ config S3C24XX_PWM
Support for exporting the PWM timer blocks via the pwm device
system.
# gpio configurations
config S3C24XX_GPIO_EXTRA
int
default 128 if S3C24XX_GPIO_EXTRA128
default 64 if S3C24XX_GPIO_EXTRA64
default 0
config S3C24XX_GPIO_EXTRA64
bool
help
Add an extra 64 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
config S3C24XX_GPIO_EXTRA128
bool
help
Add an extra 128 gpio numbers to the available GPIO pool. This is
available for boards that need extra gpios for external devices.
config PM_SIMTEC
bool
help
......@@ -49,6 +83,29 @@ config S3C2410_DMA_DEBUG
Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG.
config S3C24XX_ADC
bool "ADC common driver support"
help
Core support for the ADC block found in the S3C24XX SoC systems
for drivers such as the touchscreen and hwmon to use to share
this resource.
# SPI default pin configuration code
config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
bool
help
SPI GPIO configuration code for BUS0 when connected to
GPE11, GPE12 and GPE13.
config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
bool
help
SPI GPIO configuration code for BUS 1 when connected to
GPG5, GPG6 and GPG7.
# common code for s3c24xx based machines, such as the SMDKs.
config MACH_SMDK
bool
help
......
arch/arm/plat-s3c24xx/Makefile
View file @ fdb0a1a6
......@@ -17,9 +17,8 @@ obj-y += irq.o
obj-y += devs.o
obj-y += gpio.o
obj-y += gpiolib.o
obj-y += time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
# Architecture dependant builds
......@@ -30,5 +29,18 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_HAVE_PWM) += pwm.o
obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C24XX_ADC) += adc.o
# device specific setup and/or initialisation
obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
# SPI gpio central GPIO functions
obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o
# machine common support
obj-$(CONFIG_MACH_SMDK) += common-smdk.o
arch/arm/plat-s3c24xx/adc.c 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c24xx/adc.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
*
* S3C24XX ADC device core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <plat/regs-adc.h>
#include <plat/adc.h>
/* This driver is designed to control the usage of the ADC block between
* the touchscreen and any other drivers that may need to use it, such as
* the hwmon driver.
*
* Priority will be given to the touchscreen driver, but as this itself is
* rate limited it should not starve other requests which are processed in
* order that they are received.
*
* Each user registers to get a client block which uniquely identifies it
* and stores information such as the necessary functions to callback when
* action is required.
*/
struct s3c_adc_client {
struct platform_device *pdev;
struct list_head pend;
unsigned int nr_samples;
unsigned char is_ts;
unsigned char channel;
void (*select_cb)(unsigned selected);
void (*convert_cb)(unsigned val1, unsigned val2);
};
struct adc_device {
struct platform_device *pdev;
struct platform_device *owner;
struct clk *clk;
struct s3c_adc_client *cur;
struct s3c_adc_client *ts_pend;
void __iomem *regs;
unsigned int prescale;
int irq;
};
static struct adc_device *adc_dev;
static LIST_HEAD(adc_pending);
#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
static inline void s3c_adc_convert(struct adc_device *adc)
{
unsigned con = readl(adc->regs + S3C2410_ADCCON);
con |= S3C2410_ADCCON_ENABLE_START;
writel(con, adc->regs + S3C2410_ADCCON);
}
static inline void s3c_adc_select(struct adc_device *adc,
struct s3c_adc_client *client)
{
unsigned con = readl(adc->regs + S3C2410_ADCCON);
client->select_cb(1);
con &= ~S3C2410_ADCCON_MUXMASK;
con &= ~S3C2410_ADCCON_STDBM;
con &= ~S3C2410_ADCCON_STARTMASK;
if (!client->is_ts)
con |= S3C2410_ADCCON_SELMUX(client->channel);
writel(con, adc->regs + S3C2410_ADCCON);
}
static void s3c_adc_dbgshow(struct adc_device *adc)
{
adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
readl(adc->regs + S3C2410_ADCCON),
readl(adc->regs + S3C2410_ADCTSC),
readl(adc->regs + S3C2410_ADCDLY));
}
void s3c_adc_try(struct adc_device *adc)
{
struct s3c_adc_client *next = adc->ts_pend;
if (!next && !list_empty(&adc_pending)) {
next = list_first_entry(&adc_pending,
struct s3c_adc_client, pend);
list_del(&next->pend);
} else
adc->ts_pend = NULL;
if (next) {
adc_dbg(adc, "new client is %p\n", next);
adc->cur = next;
s3c_adc_select(adc, next);
s3c_adc_convert(adc);
s3c_adc_dbgshow(adc);
}
}
int s3c_adc_start(struct s3c_adc_client *client,
unsigned int channel, unsigned int nr_samples)
{
struct adc_device *adc = adc_dev;
unsigned long flags;
if (!adc) {
printk(KERN_ERR "%s: failed to find adc\n", __func__);
return -EINVAL;
}
if (client->is_ts && adc->ts_pend)
return -EAGAIN;
local_irq_save(flags);
client->channel = channel;
client->nr_samples = nr_samples;
if (client->is_ts)
adc->ts_pend = client;
else
list_add_tail(&client->pend, &adc_pending);
if (!adc->cur)
s3c_adc_try(adc);
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL_GPL(s3c_adc_start);
static void s3c_adc_default_select(unsigned select)
{
}
struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned int selected),
void (*conv)(unsigned d0, unsigned d1),
unsigned int is_ts)
{
struct s3c_adc_client *client;
WARN_ON(!pdev);
WARN_ON(!conv);
if (!select)
select = s3c_adc_default_select;
if (!conv || !pdev)
return ERR_PTR(-EINVAL);
client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
if (!client) {
dev_err(&pdev->dev, "no memory for adc client\n");
return ERR_PTR(-ENOMEM);
}
client->pdev = pdev;
client->is_ts = is_ts;
client->select_cb = select;
client->convert_cb = conv;
return client;
}
EXPORT_SYMBOL_GPL(s3c_adc_register);
void s3c_adc_release(struct s3c_adc_client *client)
{
/* We should really check that nothing is in progress. */
kfree(client);
}
EXPORT_SYMBOL_GPL(s3c_adc_release);
static irqreturn_t s3c_adc_irq(int irq, void *pw)
{
struct adc_device *adc = pw;
struct s3c_adc_client *client = adc->cur;
unsigned long flags;
unsigned data0, data1;
if (!client) {
dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
return IRQ_HANDLED;
}
data0 = readl(adc->regs + S3C2410_ADCDAT0);
data1 = readl(adc->regs + S3C2410_ADCDAT1);
adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
if (--client->nr_samples > 0) {
/* fire another conversion for this */
client->select_cb(1);
s3c_adc_convert(adc);
} else {
local_irq_save(flags);
(client->select_cb)(0);
adc->cur = NULL;
s3c_adc_try(adc);
local_irq_restore(flags);
}
return IRQ_HANDLED;
}
static int s3c_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct adc_device *adc;
struct resource *regs;
int ret;
adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
if (adc == NULL) {
dev_err(dev, "failed to allocate adc_device\n");
return -ENOMEM;
}
adc->pdev = pdev;
adc->prescale = S3C2410_ADCCON_PRSCVL(49);
adc->irq = platform_get_irq(pdev, 1);
if (adc->irq <= 0) {
dev_err(dev, "failed to get adc irq\n");
ret = -ENOENT;
goto err_alloc;
}
ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
if (ret < 0) {
dev_err(dev, "failed to attach adc irq\n");
goto err_alloc;
}
adc->clk = clk_get(dev, "adc");
if (IS_ERR(adc->clk)) {
dev_err(dev, "failed to get adc clock\n");
ret = PTR_ERR(adc->clk);
goto err_irq;
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(dev, "failed to find registers\n");
ret = -ENXIO;
goto err_clk;
}
adc->regs = ioremap(regs->start, resource_size(regs));
if (!adc->regs) {
dev_err(dev, "failed to map registers\n");
ret = -ENXIO;
goto err_clk;
}
clk_enable(adc->clk);
writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
adc->regs + S3C2410_ADCCON);
dev_info(dev, "attached adc driver\n");
platform_set_drvdata(pdev, adc);
adc_dev = adc;
return 0;
err_clk:
clk_put(adc->clk);
err_irq:
free_irq(adc->irq, adc);
err_alloc:
kfree(adc);
return ret;
}
static int s3c_adc_remove(struct platform_device *pdev)
{
struct adc_device *adc = platform_get_drvdata(pdev);
iounmap(adc->regs);
free_irq(adc->irq, adc);
clk_disable(adc->clk);
clk_put(adc->clk);
kfree(adc);
return 0;
}
#ifdef CONFIG_PM
static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct adc_device *adc = platform_get_drvdata(pdev);
u32 con;
con = readl(adc->regs + S3C2410_ADCCON);
con |= S3C2410_ADCCON_STDBM;
writel(con, adc->regs + S3C2410_ADCCON);
clk_disable(adc->clk);
return 0;
}
static int s3c_adc_resume(struct platform_device *pdev)
{
struct adc_device *adc = platform_get_drvdata(pdev);
clk_enable(adc->clk);
writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
adc->regs + S3C2410_ADCCON);
return 0;
}
#else
#define s3c_adc_suspend NULL
#define s3c_adc_resume NULL
#endif
static struct platform_driver s3c_adc_driver = {
.driver = {
.name = "s3c24xx-adc",
.owner = THIS_MODULE,
},
.probe = s3c_adc_probe,
.remove = __devexit_p(s3c_adc_remove),
.suspend = s3c_adc_suspend,
.resume = s3c_adc_resume,
};
static int __init adc_init(void)
{
int ret;
ret = platform_driver_register(&s3c_adc_driver);
if (ret)
printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
return ret;
}
arch_initcall(adc_init);
arch/arm/plat-s3c24xx/clock-dclk.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
*
* Copyright (c) 2004,2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24XX - definitions for DCLK and CLKOUT registers
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/clock.h>
#include <plat/cpu.h>
/* clocks that could be registered by external code */
static int s3c24xx_dclk_enable(struct clk *clk, int enable)
{
unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
if (enable)
dclkcon |= clk->ctrlbit;
else
dclkcon &= ~clk->ctrlbit;
__raw_writel(dclkcon, S3C24XX_DCLKCON);
return 0;
}
static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
{
unsigned long dclkcon;
unsigned int uclk;
if (parent == &clk_upll)
uclk = 1;
else if (parent == &clk_p)
uclk = 0;
else
return -EINVAL;
clk->parent = parent;
dclkcon = __raw_readl(S3C24XX_DCLKCON);
if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
if (uclk)
dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
else
dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
} else {
if (uclk)
dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
else
dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
}
__raw_writel(dclkcon, S3C24XX_DCLKCON);
return 0;
}
static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
{
unsigned long div;
if ((rate == 0) || !clk->parent)
return 0;
div = clk_get_rate(clk->parent) / rate;
if (div < 2)
div = 2;
else if (div > 16)
div = 16;
return div;
}
static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
unsigned long rate)
{
unsigned long div = s3c24xx_calc_div(clk, rate);
if (div == 0)
return 0;
return clk_get_rate(clk->parent) / div;
}
static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
{
unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
if (div == 0)
return -EINVAL;
if (clk == &s3c24xx_dclk0) {
mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
S3C2410_DCLKCON_DCLK0_CMP_MASK;
data = S3C2410_DCLKCON_DCLK0_DIV(div) |
S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
} else if (clk == &s3c24xx_dclk1) {
mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
S3C2410_DCLKCON_DCLK1_CMP_MASK;
data = S3C2410_DCLKCON_DCLK1_DIV(div) |
S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
} else
return -EINVAL;
clk->rate = clk_get_rate(clk->parent) / div;
__raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
S3C24XX_DCLKCON);
return clk->rate;
}
static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
{
unsigned long mask;
unsigned long source;
/* calculate the MISCCR setting for the clock */
if (parent == &clk_xtal)
source = S3C2410_MISCCR_CLK0_MPLL;
else if (parent == &clk_upll)
source = S3C2410_MISCCR_CLK0_UPLL;
else if (parent == &clk_f)
source = S3C2410_MISCCR_CLK0_FCLK;
else if (parent == &clk_h)
source = S3C2410_MISCCR_CLK0_HCLK;
else if (parent == &clk_p)
source = S3C2410_MISCCR_CLK0_PCLK;
else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
source = S3C2410_MISCCR_CLK0_DCLK0;
else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
source = S3C2410_MISCCR_CLK0_DCLK0;
else
return -EINVAL;
clk->parent = parent;
if (clk == &s3c24xx_clkout0)
mask = S3C2410_MISCCR_CLK0_MASK;
else {
source <<= 4;
mask = S3C2410_MISCCR_CLK1_MASK;
}
s3c2410_modify_misccr(mask, source);
return 0;
}
/* external clock definitions */
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate,
.round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate,
.round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
.id = -1,
.set_parent = s3c24xx_clkout_setparent,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
.id = -1,
.set_parent = s3c24xx_clkout_setparent,
};
arch/arm/plat-s3c24xx/clock.c
View file @ fdb0a1a6
......@@ -27,18 +27,8 @@
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <mach/hardware.h>
......@@ -47,490 +37,23 @@
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
/* clock information */
static LIST_HEAD(clocks);
DEFINE_MUTEX(clocks_mutex);
/* enable and disable calls for use with the clk struct */
static int clk_null_enable(struct clk *clk, int enable)
{
return 0;
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p;
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
mutex_lock(&clocks_mutex);
list_for_each_entry(p, &clocks, list) {
if (p->id == idno &&
strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
/* check for the case where a device was supplied, but the
* clock that was being searched for is not device specific */
if (IS_ERR(clk)) {
list_for_each_entry(p, &clocks, list) {
if (p->id == -1 && strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
}
mutex_unlock(&clocks_mutex);
return clk;
}
void clk_put(struct clk *clk)
{
module_put(clk->owner);
}
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return -EINVAL;
clk_enable(clk->parent);
mutex_lock(&clocks_mutex);
if ((clk->usage++) == 0)
(clk->enable)(clk, 1);
mutex_unlock(&clocks_mutex);
return 0;
}
void clk_disable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return;
mutex_lock(&clocks_mutex);
if ((--clk->usage) == 0)
(clk->enable)(clk, 0);
mutex_unlock(&clocks_mutex);
clk_disable(clk->parent);
}
unsigned long clk_get_rate(struct clk *clk)
{
if (IS_ERR(clk))
return 0;
if (clk->rate != 0)
return clk->rate;
if (clk->get_rate != NULL)
return (clk->get_rate)(clk);
if (clk->parent != NULL)
return clk_get_rate(clk->parent);
return clk->rate;
}
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (!IS_ERR(clk) && clk->round_rate)
return (clk->round_rate)(clk, rate);
return rate;
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (IS_ERR(clk))
return -EINVAL;
/* We do not default just do a clk->rate = rate as
* the clock may have been made this way by choice.
*/
WARN_ON(clk->set_rate == NULL);
if (clk->set_rate == NULL)
return -EINVAL;
mutex_lock(&clocks_mutex);
ret = (clk->set_rate)(clk, rate);
mutex_unlock(&clocks_mutex);
return ret;
}
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = 0;
if (IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
if (clk->set_parent)
ret = (clk->set_parent)(clk, parent);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);
/* base clocks */
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
struct clk clk_xtal = {
.name = "xtal",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_mpll = {
.name = "mpll",
.id = -1,
.set_rate = clk_default_setrate,
};
struct clk clk_upll = {
.name = "upll",
.id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
.id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_h = {
.name = "hclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_p = {
.name = "pclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_usb_bus = {
.name = "usb-bus",
.id = -1,
.rate = 0,
.parent = &clk_upll,
};
/* clocks that could be registered by external code */
static int s3c24xx_dclk_enable(struct clk *clk, int enable)
{
unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
if (enable)
dclkcon |= clk->ctrlbit;
else
dclkcon &= ~clk->ctrlbit;
__raw_writel(dclkcon, S3C24XX_DCLKCON);
return 0;
}
static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
{
unsigned long dclkcon;
unsigned int uclk;
if (parent == &clk_upll)
uclk = 1;
else if (parent == &clk_p)
uclk = 0;
else
return -EINVAL;
clk->parent = parent;
dclkcon = __raw_readl(S3C24XX_DCLKCON);
if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
if (uclk)
dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
else
dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
} else {
if (uclk)
dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
else
dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
}
__raw_writel(dclkcon, S3C24XX_DCLKCON);
return 0;
}
static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
{
unsigned long div;
if ((rate == 0) || !clk->parent)
return 0;
div = clk_get_rate(clk->parent) / rate;
if (div < 2)
div = 2;
else if (div > 16)
div = 16;
return div;
}
static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
unsigned long rate)
{
unsigned long div = s3c24xx_calc_div(clk, rate);
if (div == 0)
return 0;
return clk_get_rate(clk->parent) / div;
}
static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
{
unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
if (div == 0)
return -EINVAL;
if (clk == &s3c24xx_dclk0) {
mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
S3C2410_DCLKCON_DCLK0_CMP_MASK;
data = S3C2410_DCLKCON_DCLK0_DIV(div) |
S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
} else if (clk == &s3c24xx_dclk1) {
mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
S3C2410_DCLKCON_DCLK1_CMP_MASK;
data = S3C2410_DCLKCON_DCLK1_DIV(div) |
S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
} else
return -EINVAL;
clk->rate = clk_get_rate(clk->parent) / div;
__raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
S3C24XX_DCLKCON);
return clk->rate;
}
static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
{
unsigned long mask;
unsigned long source;
/* calculate the MISCCR setting for the clock */
if (parent == &clk_xtal)
source = S3C2410_MISCCR_CLK0_MPLL;
else if (parent == &clk_upll)
source = S3C2410_MISCCR_CLK0_UPLL;
else if (parent == &clk_f)
source = S3C2410_MISCCR_CLK0_FCLK;
else if (parent == &clk_h)
source = S3C2410_MISCCR_CLK0_HCLK;
else if (parent == &clk_p)
source = S3C2410_MISCCR_CLK0_PCLK;
else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
source = S3C2410_MISCCR_CLK0_DCLK0;
else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
source = S3C2410_MISCCR_CLK0_DCLK0;
else
return -EINVAL;
clk->parent = parent;
if (clk == &s3c24xx_clkout0)
mask = S3C2410_MISCCR_CLK0_MASK;
else {
source <<= 4;
mask = S3C2410_MISCCR_CLK1_MASK;
}
s3c2410_modify_misccr(mask, source);
return 0;
}
/* external clock definitions */
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate,
.round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
.set_rate = s3c24xx_set_dclk_rate,
.round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
.id = -1,
.set_parent = s3c24xx_clkout_setparent,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
.id = -1,
.set_parent = s3c24xx_clkout_setparent,
};
struct clk s3c24xx_uclk = {
.name = "uclk",
.id = -1,
};
/* initialise the clock system */
int s3c24xx_register_clock(struct clk *clk)
{
clk->owner = THIS_MODULE;
if (clk->enable == NULL)
clk->enable = clk_null_enable;
/* add to the list of available clocks */
mutex_lock(&clocks_mutex);
list_add(&clk->list, &clocks);
mutex_unlock(&clocks_mutex);
return 0;
}
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
int fails = 0;
for (; nr_clks > 0; nr_clks--, clks++) {
if (s3c24xx_register_clock(*clks) < 0)
fails++;
}
return fails;
}
#include <plat/pll.h>
/* initalise all the clocks */
int __init s3c24xx_setup_clocks(unsigned long xtal,
unsigned long fclk,
unsigned long hclk,
unsigned long pclk)
void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
unsigned long hclk,
unsigned long pclk)
{
printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
/* initialise the main system clocks */
clk_xtal.rate = xtal;
clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
clk_xtal.rate);
clk_mpll.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = fclk;
/* assume uart clocks are correctly setup */
/* register our clocks */
if (s3c24xx_register_clock(&clk_xtal) < 0)
printk(KERN_ERR "failed to register master xtal\n");
if (s3c24xx_register_clock(&clk_mpll) < 0)
printk(KERN_ERR "failed to register mpll clock\n");
if (s3c24xx_register_clock(&clk_upll) < 0)
printk(KERN_ERR "failed to register upll clock\n");
if (s3c24xx_register_clock(&clk_f) < 0)
printk(KERN_ERR "failed to register cpu fclk\n");
if (s3c24xx_register_clock(&clk_h) < 0)
printk(KERN_ERR "failed to register cpu hclk\n");
if (s3c24xx_register_clock(&clk_p) < 0)
printk(KERN_ERR "failed to register cpu pclk\n");
return 0;
}
arch/arm/plat-s3c24xx/cpu.c
View file @ fdb0a1a6
......@@ -30,7 +30,6 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <asm/irq.h>
......@@ -55,16 +54,6 @@
#include <plat/s3c2442.h>
#include <plat/s3c2443.h>
struct cpu_table {
unsigned long idcode;
unsigned long idmask;
void (*map_io)(struct map_desc *mach_desc, int size);
void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
void (*init_clocks)(int xtal);
int (*init)(void);
const char *name;
};
/* table of supported CPUs */
static const char name_s3c2400[] = "S3C2400";
......@@ -169,23 +158,7 @@ static struct map_desc s3c_iodesc[] __initdata = {
IODESC_ENT(UART)
};
static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
{
struct cpu_table *tab;
int count;
tab = cpu_ids;
for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
if ((idcode & tab->idmask) == tab->idcode)
return tab;
}
return NULL;
}
/* cpu information */
static struct cpu_table *cpu;
/* read cpu identificaiton code */
static unsigned long s3c24xx_read_idcode_v5(void)
{
......@@ -231,6 +204,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
unsigned long idcode = 0x0;
/* initialise the io descriptors we need for initialisation */
iotable_init(mach_desc, size);
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
if (cpu_architecture() >= CPU_ARCH_ARMv5) {
......@@ -239,117 +213,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
idcode = s3c24xx_read_idcode_v4();
}
cpu = s3c_lookup_cpu(idcode);
if (cpu == NULL) {
printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
panic("Unknown S3C24XX CPU");
}
printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
if (cpu->map_io == NULL || cpu->init == NULL) {
printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
panic("Unsupported S3C24XX CPU");
}
arm_pm_restart = s3c24xx_pm_restart;
(cpu->map_io)(mach_desc, size);
}
/* s3c24xx_init_clocks
*
* Initialise the clock subsystem and associated information from the
* given master crystal value.
*
* xtal = 0 -> use default PLL crystal value (normally 12MHz)
* != 0 -> PLL crystal value in Hz
*/
void __init s3c24xx_init_clocks(int xtal)
{
if (xtal == 0)
xtal = 12*1000*1000;
if (cpu == NULL)
panic("s3c24xx_init_clocks: no cpu setup?\n");
if (cpu->init_clocks == NULL)
panic("s3c24xx_init_clocks: cpu has no clock init\n");
else
(cpu->init_clocks)(xtal);
s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
}
/* uart management */
static int nr_uarts __initdata = 0;
static struct s3c2410_uartcfg uart_cfgs[3];
/* s3c24xx_init_uartdevs
*
* copy the specified platform data and configuration into our central
* set of devices, before the data is thrown away after the init process.
*
* This also fills in the array passed to the serial driver for the
* early initialisation of the console.
*/
void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
int uart;
memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
platdev = s3c24xx_uart_src[cfgptr->hwport];
resp = res + cfgptr->hwport;
s3c24xx_uart_devs[uart] = platdev;
platdev->name = name;
platdev->resource = resp->resources;
platdev->num_resources = resp->nr_resources;
platdev->dev.platform_data = cfgptr;
}
nr_uarts = no;
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
if (cpu == NULL)
return;
if (cpu->init_uarts == NULL) {
printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
} else
(cpu->init_uarts)(cfg, no);
}
static int __init s3c_arch_init(void)
{
int ret;
// do the correct init for cpu
if (cpu == NULL)
panic("s3c_arch_init: NULL cpu\n");
ret = (cpu->init)();
if (ret != 0)
return ret;
ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
return ret;
}
arch_initcall(s3c_arch_init);
arch/arm/plat-s3c24xx/devs.c
View file @ fdb0a1a6
......@@ -76,6 +76,19 @@ static struct resource s3c2410_uart2_resource[] = {
}
};
static struct resource s3c2410_uart3_resource[] = {
[0] = {
.start = S3C2443_PA_UART3,
.end = S3C2443_PA_UART3 + 0x3fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX3,
.end = IRQ_S3CUART_ERR3,
.flags = IORESOURCE_IRQ,
},
};
struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
[0] = {
.resources = s3c2410_uart0_resource,
......@@ -89,6 +102,10 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
.resources = s3c2410_uart2_resource,
.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
},
[3] = {
.resources = s3c2410_uart3_resource,
.nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
},
};
/* yart devices */
......@@ -105,13 +122,18 @@ static struct platform_device s3c24xx_uart_device2 = {
.id = 2,
};
struct platform_device *s3c24xx_uart_src[3] = {
static struct platform_device s3c24xx_uart_device3 = {
.id = 3,
};
struct platform_device *s3c24xx_uart_src[4] = {
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
&s3c24xx_uart_device3,
};
struct platform_device *s3c24xx_uart_devs[3] = {
struct platform_device *s3c24xx_uart_devs[4] = {
};
/* USB Host Controller */
......@@ -192,8 +214,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
static struct resource s3c_nand_resource[] = {
[0] = {
.start = S3C2410_PA_NAND,
.end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
.start = S3C24XX_PA_NAND,
.end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
.flags = IORESOURCE_MEM,
}
};
......@@ -271,31 +293,6 @@ struct platform_device s3c_device_wdt = {
EXPORT_SYMBOL(s3c_device_wdt);
/* I2C */
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C24XX_PA_IIC,
.end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device s3c_device_i2c = {
.name = "s3c2410-i2c",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
EXPORT_SYMBOL(s3c_device_i2c);
/* IIS */
static struct resource s3c_iis_resource[] = {
......@@ -372,18 +369,26 @@ static struct resource s3c_adc_resource[] = {
};
struct platform_device s3c_device_adc = {
.name = "s3c2410-adc",
.name = "s3c24xx-adc",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_adc_resource),
.resource = s3c_adc_resource,
};
/* HWMON */
struct platform_device s3c_device_hwmon = {
.name = "s3c24xx-hwmon",
.id = -1,
.dev.parent = &s3c_device_adc.dev,
};
/* SDI */
static struct resource s3c_sdi_resource[] = {
[0] = {
.start = S3C2410_PA_SDI,
.end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
.start = S3C24XX_PA_SDI,
.end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -403,36 +408,6 @@ struct platform_device s3c_device_sdi = {
EXPORT_SYMBOL(s3c_device_sdi);
/* High-speed MMC/SD */
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C2443_PA_HSMMC,
.end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3C2443_HSMMC,
.end = IRQ_S3C2443_HSMMC,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct platform_device s3c_device_hsmmc = {
.name = "s3c-sdhci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
/* SPI (0) */
static struct resource s3c_spi0_resource[] = {
......
arch/arm/plat-s3c24xx/dma.c
View file @ fdb0a1a6
......@@ -25,7 +25,6 @@
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/system.h>
......
arch/arm/plat-s3c24xx/gpiolib.c
View file @ fdb0a1a6
......@@ -19,104 +19,12 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/regs-gpio.h>
struct s3c24xx_gpio_chip {
struct gpio_chip chip;
void __iomem *base;
};
static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c24xx_gpio_chip, chip);
}
/* these routines are exported for use by other parts of the platform
* and system support, but are not intended to be used directly by the
* drivers themsevles.
*/
static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
return -EINVAL;
......@@ -125,7 +33,7 @@ static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
......@@ -151,7 +59,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
return 0;
}
static struct s3c24xx_gpio_chip gpios[] = {
struct s3c_gpio_chip s3c24xx_gpios[] = {
[0] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
.chip = {
......@@ -161,8 +69,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.ngpio = 24,
.direction_input = s3c24xx_gpiolib_banka_input,
.direction_output = s3c24xx_gpiolib_banka_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[1] = {
......@@ -172,10 +78,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.owner = THIS_MODULE,
.label = "GPIOB",
.ngpio = 16,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[2] = {
......@@ -185,10 +87,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.owner = THIS_MODULE,
.label = "GPIOC",
.ngpio = 16,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[3] = {
......@@ -198,10 +96,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.owner = THIS_MODULE,
.label = "GPIOD",
.ngpio = 16,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[4] = {
......@@ -211,10 +105,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.label = "GPIOE",
.owner = THIS_MODULE,
.ngpio = 16,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[5] = {
......@@ -224,10 +114,6 @@ static struct s3c24xx_gpio_chip gpios[] = {
.owner = THIS_MODULE,
.label = "GPIOF",
.ngpio = 8,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
[6] = {
......@@ -237,21 +123,17 @@ static struct s3c24xx_gpio_chip gpios[] = {
.owner = THIS_MODULE,
.label = "GPIOG",
.ngpio = 10,
.direction_input = s3c24xx_gpiolib_input,
.direction_output = s3c24xx_gpiolib_output,
.set = s3c24xx_gpiolib_set,
.get = s3c24xx_gpiolib_get,
},
},
};
static __init int s3c24xx_gpiolib_init(void)
{
struct s3c24xx_gpio_chip *chip = gpios;
struct s3c_gpio_chip *chip = s3c24xx_gpios;
int gpn;
for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
gpiochip_add(&chip->chip);
for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
s3c_gpiolib_add(chip);
return 0;
}
......
arch/arm/plat-s3c24xx/include/mach/pwm-clock.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C2410_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 0;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div) - 1;
}
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
arch/arm/plat-s3c24xx/include/plat/map.h 0 → 100644
View file @ fdb0a1a6
/* linux/include/asm-arm/plat-s3c24xx/map.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_S3C24XX_MAP_H
#define __ASM_PLAT_S3C24XX_MAP_H
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define S3C24XX_VA_IRQ S3C_VA_IRQ
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */
#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
/* UARTs */
#define S3C24XX_VA_UART S3C_VA_UART
#define S3C2410_PA_UART (0x50000000)
#define S3C24XX_SZ_UART SZ_1M
#define S3C_UART_OFFSET (0x4000)
/* Timers */
#define S3C24XX_VA_TIMER S3C_VA_TIMER
#define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M
/* Clock and Power management */
#define S3C24XX_VA_CLKPWR S3C_VA_SYS
#define S3C24XX_SZ_CLKPWR SZ_1M
/* USB Device port */
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M
/* Standard size definitions for peripheral blocks. */
#define S3C24XX_SZ_IIS SZ_1M
#define S3C24XX_SZ_ADC SZ_1M
#define S3C24XX_SZ_SPI SZ_1M
#define S3C24XX_SZ_SDI SZ_1M
#define S3C24XX_SZ_NAND SZ_1M
#define S3C24XX_SZ_USBHOST SZ_1M
/* GPIO ports */
/* the calculation for the VA of this must ensure that
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
* is done as a 1:1 maping. This puts it (currently) at
* 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/
#define S3C2410_PA_GPIO (0x56000000)
#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
*/
#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
#ifdef CONFIG_CPU_S3C2412_ONLY
#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
#else
#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
#endif
#else
#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif
#endif /* __ASM_PLAT_S3C24XX_MAP_H */
arch/arm/plat-s3c24xx/include/plat/pll.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24xx - common pll registers and code
*/
#define S3C24XX_PLLCON_MDIVSHIFT 12
#define S3C24XX_PLLCON_PDIVSHIFT 4
#define S3C24XX_PLLCON_SDIVSHIFT 0
#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
#define S3C24XX_PLLCON_SDIVMASK 3
#include <asm/div64.h>
static inline unsigned int
s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
mdiv &= S3C24XX_PLLCON_MDIVMASK;
pdiv &= S3C24XX_PLLCON_PDIVMASK;
sdiv &= S3C24XX_PLLCON_SDIVMASK;
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
arch/arm/plat-s3c24xx/include/plat/s3c2400.h
View file @ fdb0a1a6
......@@ -17,7 +17,7 @@
extern int s3c2400_init(void);
extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
extern void s3c2400_map_io(void);
extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c24xx/include/plat/s3c2410.h
View file @ fdb0a1a6
......@@ -15,7 +15,7 @@
extern int s3c2410_init(void);
extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
extern void s3c2410_map_io(void);
extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c24xx/include/plat/s3c2412.h
View file @ fdb0a1a6
......@@ -14,7 +14,7 @@
extern int s3c2412_init(void);
extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
extern void s3c2412_map_io(void);
extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c24xx/include/plat/s3c2443.h
View file @ fdb0a1a6
......@@ -16,7 +16,7 @@ struct s3c2410_uartcfg;
extern int s3c2443_init(void);
extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
extern void s3c2443_map_io(void);
extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c24xx/irq.c
View file @ fdb0a1a6
......@@ -62,6 +62,7 @@
#include <asm/mach/irq.h>
#include <plat/regs-irqtype.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
......
arch/arm/plat-s3c24xx/pm.c
View file @ fdb0a1a6
......@@ -33,7 +33,6 @@
#include <linux/interrupt.h>
#include <linux/crc32.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/io.h>
......@@ -76,11 +75,13 @@ static struct sleep_save core_save[] = {
SAVE_ITEM(S3C2410_BANKCON4),
SAVE_ITEM(S3C2410_BANKCON5),
#ifndef CONFIG_CPU_FREQ
SAVE_ITEM(S3C2410_CLKDIVN),
SAVE_ITEM(S3C2410_MPLLCON),
SAVE_ITEM(S3C2410_REFRESH),
#endif
SAVE_ITEM(S3C2410_UPLLCON),
SAVE_ITEM(S3C2410_CLKSLOW),
SAVE_ITEM(S3C2410_REFRESH),
};
static struct gpio_sleep {
......
arch/arm/mach-s3c2410/clock.c → arch/arm/plat-s3c24xx/s3c2410-clock.c
View file @ fdb0a1a6
......@@ -272,5 +272,6 @@ int __init s3c2410_baseclk_add(void)
(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
s3c_pwmclk_init();
return 0;
}
arch/arm/plat-s3c24xx/s3c244x-clock.c
View file @ fdb0a1a6
......@@ -31,7 +31,6 @@
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
......@@ -102,13 +101,13 @@ static int s3c244x_clk_add(struct sys_device *sysdev)
if (clk_get_rate(clock_upll) > (94 * MHZ)) {
clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
mutex_lock(&clocks_mutex);
spin_lock(&clocks_lock);
clkdivn = __raw_readl(S3C2410_CLKDIVN);
clkdivn |= S3C2440_CLKDIVN_UCLK;
__raw_writel(clkdivn, S3C2410_CLKDIVN);
mutex_unlock(&clocks_mutex);
spin_unlock(&clocks_lock);
}
return 0;
......
arch/arm/plat-s3c24xx/s3c244x.c
View file @ fdb0a1a6
......@@ -29,6 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
......@@ -42,6 +44,7 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
......@@ -56,32 +59,34 @@ void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}
void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
void __init s3c244x_map_io(void)
{
/* register our io-tables */
iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
iotable_init(mach_desc, size);
/* rename any peripherals used differing from the s3c2410 */
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_i2c.name = "s3c2440-i2c";
s3c_device_i2c0.name = "s3c2440-i2c";
s3c_device_nand.name = "s3c2440-nand";
s3c_device_usbgadget.name = "s3c2440-usbgadget";
}
void __init s3c244x_init_clocks(int xtal)
void __init_or_cpufreq s3c244x_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long clkdiv;
unsigned long camdiv;
unsigned long xtal;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
......@@ -107,18 +112,24 @@ void __init s3c244x_init_clocks(int xtal)
}
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c244x_init_clocks(int xtal)
{
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_register_baseclocks(xtal);
s3c244x_setup_clocks();
s3c2410_baseclk_add();
}
......
arch/arm/plat-s3c24xx/s3c244x.h
View file @ fdb0a1a6
......@@ -12,7 +12,7 @@
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
extern void s3c244x_map_io(void);
extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
......
arch/arm/plat-s3c24xx/setup-i2c.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Base setup for i2c device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
struct platform_device;
#include <plat/iic.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
}
arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/regs-gpio.h>
void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
s3c2410_gpio_pullup(S3C2410_GPE11, 0);
s3c2410_gpio_pullup(S3C2410_GPE13, 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPE11, 1);
s3c2410_gpio_pullup(S3C2410_GPE12, 1);
s3c2410_gpio_pullup(S3C2410_GPE13, 1);
}
}
arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/regs-gpio.h>
void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
s3c2410_gpio_pullup(S3C2410_GPG5, 0);
s3c2410_gpio_pullup(S3C2410_GPG6, 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPG5, 1);
s3c2410_gpio_pullup(S3C2410_GPG6, 1);
s3c2410_gpio_pullup(S3C2410_GPG7, 1);
}
}
arch/arm/plat-s3c64xx/Kconfig 0 → 100644
View file @ fdb0a1a6
# arch/arm/plat-s3c64xx/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
# Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
default y
select CPU_V6
select PLAT_S3C
select ARM_VIC
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
help
Base platform code for any Samsung S3C64XX device
if PLAT_S3C64XX
# Configuration options shared by all S3C64XX implementations
config CPU_S3C6400_INIT
bool
help
Common initialisation code for the S3C6400 that is shared
by other CPUs in the series, such as the S3C6410.
config CPU_S3C6400_CLOCK
bool
help
Common clock support code for the S3C6400 that is shared
by other CPUs in the series, such as the S3C6410.
# platform specific device setup
config S3C64XX_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S3C64XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S3C64XX_SETUP_FB_24BPP
bool
help
Common setup code for S3C64XX with an 24bpp RGB display helper.
endif
arch/arm/plat-s3c64xx/Makefile 0 → 100644
View file @ fdb0a1a6
# arch/arm/plat-s3c64xx/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n := dummy.o
obj- :=
# Core files
obj-y += dev-uart.o
obj-y += cpu.o
obj-y += irq.o
obj-y += irq-eint.o
obj-y += clock.o
obj-y += gpiolib.o
# CPU support
obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
# Device setup
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
arch/arm/plat-s3c64xx/clock.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/clock.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX Base clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-sys.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S3C64XX_OTHERS);
if (enable)
val |= S3C64XX_OTHERS_USBMASK;
else
val &= ~S3C64XX_OTHERS_USBMASK;
__raw_writel(val, S3C64XX_OTHERS);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk,
int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}
static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}
int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "48m",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
.id = 2,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
},
};
static struct clk init_clocks[] = {
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
};
void s3c64xx_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
arch/arm/plat-s3c64xx/cpu.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/cpu.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX CPU Support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* table of supported CPUs */
static const char name_s3c6400[] = "S3C6400";
static const char name_s3c6410[] = "S3C6410";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = 0x36400000,
.idmask = 0xfffff000,
.map_io = s3c6400_map_io,
.init_clocks = s3c6400_init_clocks,
.init_uarts = s3c6400_init_uarts,
.init = s3c6400_init,
.name = name_s3c6400,
}, {
.idcode = 0x36410100,
.idmask = 0xffffff00,
.map_io = s3c6410_map_io,
.init_clocks = s3c6410_init_clocks,
.init_uarts = s3c6410_init_uarts,
.init = s3c6410_init,
.name = name_s3c6410,
},
};
/* minimal IO mapping */
/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xfffff)
static struct map_desc s3c_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_VIC0,
.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_VIC1,
.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(S3C_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C64XX_VA_GPIO,
.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
/* read cpu identification code */
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
unsigned long idcode;
/* initialise the io descriptors we need for initialisation */
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
iotable_init(mach_desc, size);
idcode = __raw_readl(S3C_VA_SYS + 0x118);
s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
}
arch/arm/plat-s3c64xx/dev-uart.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/dev-uart.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX UART resource and device definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/devs.h>
/* Serial port registrations */
/* 64xx uarts are closer together */
static struct resource s3c64xx_uart0_resource[] = {
[0] = {
.start = S3C_PA_UART0,
.end = S3C_PA_UART0 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX0,
.end = IRQ_S3CUART_RX0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX0,
.end = IRQ_S3CUART_TX0,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR0,
.end = IRQ_S3CUART_ERR0,
.flags = IORESOURCE_IRQ,
}
};
static struct resource s3c64xx_uart1_resource[] = {
[0] = {
.start = S3C_PA_UART1,
.end = S3C_PA_UART1 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX1,
.end = IRQ_S3CUART_RX1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX1,
.end = IRQ_S3CUART_TX1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR1,
.end = IRQ_S3CUART_ERR1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource s3c6xx_uart2_resource[] = {
[0] = {
.start = S3C_PA_UART2,
.end = S3C_PA_UART2 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX2,
.end = IRQ_S3CUART_RX2,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX2,
.end = IRQ_S3CUART_TX2,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR2,
.end = IRQ_S3CUART_ERR2,
.flags = IORESOURCE_IRQ,
},
};
static struct resource s3c64xx_uart3_resource[] = {
[0] = {
.start = S3C_PA_UART3,
.end = S3C_PA_UART3 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX3,
.end = IRQ_S3CUART_RX3,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX3,
.end = IRQ_S3CUART_TX3,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR3,
.end = IRQ_S3CUART_ERR3,
.flags = IORESOURCE_IRQ,
},
};
struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
[0] = {
.resources = s3c64xx_uart0_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource),
},
[1] = {
.resources = s3c64xx_uart1_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource),
},
[2] = {
.resources = s3c6xx_uart2_resource,
.nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource),
},
[3] = {
.resources = s3c64xx_uart3_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource),
},
};
/* uart devices */
static struct platform_device s3c24xx_uart_device0 = {
.id = 0,
};
static struct platform_device s3c24xx_uart_device1 = {
.id = 1,
};
static struct platform_device s3c24xx_uart_device2 = {
.id = 2,
};
static struct platform_device s3c24xx_uart_device3 = {
.id = 3,
};
struct platform_device *s3c24xx_uart_src[4] = {
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
&s3c24xx_uart_device3,
};
struct platform_device *s3c24xx_uart_devs[4] = {
};
arch/arm/plat-s3c64xx/gpiolib.c 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/gpiolib.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/gpio.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
/* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 8 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* D 5 4Bit Yes 3
* E 5 4Bit Yes None
* F 16 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* K 16 4Bit[2] No None
* L 15 4Bit[2] No None
* M 6 4Bit No IRQ_EINT
* N 16 2Bit No IRQ_EINT
* O 16 2Bit Yes 7
* P 15 2Bit Yes 8
* Q 9 2Bit Yes 9
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
#define OFF_GPCON (0x00)
#define OFF_GPDAT (0x04)
#define con_4bit_shift(__off) ((__off) * 4)
#if 1
#define gpio_dbg(x...) do { } while(0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
#endif
/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
* the output.
*/
static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + OFF_GPCON);
gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, base + OFF_GPCON);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
/* The next set of routines are for the case where the GPIO configuration
* registers are 4 bits per GPIO but there is more than one register (the
* bank has more than 8 GPIOs.
*
* This case is the similar to the 4 bit case, but the registers are as
* follows:
*
* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x08: Data register, 1 bit per gpio
* bit n: data bit n
*
* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
* store the 'base + 0x4' address so that these routines see the data
* register at ourchip->base + 0x04.
*/
static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
if (offset > 7)
offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, regcon);
gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
return 0;
}
static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
unsigned long dat;
if (offset > 7)
offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, regcon);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
.cfg_eint = 7,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip gpio_4bit[] = {
{
.base = S3C64XX_GPA_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPA(0),
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S3C64XX_GPB_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPG(0),
.ngpio = S3C64XX_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S3C64XX_GPM_BASE,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPM(0),
.ngpio = S3C64XX_GPIO_M_NR,
.label = "GPM",
},
},
};
static struct s3c_gpio_chip gpio_4bit2[] = {
{
.base = S3C64XX_GPH_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPH(0),
.ngpio = S3C64XX_GPIO_H_NR,
.label = "GPH",
},
}, {
.base = S3C64XX_GPK_BASE + 0x4,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPK(0),
.ngpio = S3C64XX_GPIO_K_NR,
.label = "GPK",
},
}, {
.base = S3C64XX_GPL_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPL(0),
.ngpio = S3C64XX_GPIO_L_NR,
.label = "GPL",
},
},
};
static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
.cfg_eint = 2,
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPF(0),
.ngpio = S3C64XX_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S3C64XX_GPI_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPI(0),
.ngpio = S3C64XX_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S3C64XX_GPJ_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPJ(0),
.ngpio = S3C64XX_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S3C64XX_GPN_BASE,
.config = &gpio_2bit_cfg_eint10,
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S3C64XX_GPO_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPO(0),
.ngpio = S3C64XX_GPIO_O_NR,
.label = "GPO",
},
}, {
.base = S3C64XX_GPP_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPP(0),
.ngpio = S3C64XX_GPIO_P_NR,
.label = "GPP",
},
}, {
.base = S3C64XX_GPQ_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPQ(0),
.ngpio = S3C64XX_GPIO_Q_NR,
.label = "GPQ",
},
},
};
static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
}
static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
}
static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
}
static __init int s3c64xx_gpiolib_init(void)
{
s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
s3c64xx_gpiolib_add_4bit);
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
s3c64xx_gpiolib_add_4bit2);
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
return 0;
}
arch_initcall(s3c64xx_gpiolib_init);
arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank A register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank B register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank C register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16)
#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20)
#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28)
#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank D register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank E register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank F register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank G register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank H register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank I register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPI0_VD0 (0x02 << 0)
#define S3C64XX_GPI1_VD1 (0x02 << 2)
#define S3C64XX_GPI2_VD2 (0x02 << 4)
#define S3C64XX_GPI3_VD3 (0x02 << 6)
#define S3C64XX_GPI4_VD4 (0x02 << 8)
#define S3C64XX_GPI5_VD5 (0x02 << 10)
#define S3C64XX_GPI6_VD6 (0x02 << 12)
#define S3C64XX_GPI7_VD7 (0x02 << 14)
#define S3C64XX_GPI8_VD8 (0x02 << 16)
#define S3C64XX_GPI9_VD9 (0x02 << 18)
#define S3C64XX_GPI10_VD10 (0x02 << 20)
#define S3C64XX_GPI11_VD11 (0x02 << 22)
#define S3C64XX_GPI12_VD12 (0x02 << 24)
#define S3C64XX_GPI13_VD13 (0x02 << 26)
#define S3C64XX_GPI14_VD14 (0x02 << 28)
#define S3C64XX_GPI15_VD15 (0x02 << 30)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank J register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPJ0_VD16 (0x02 << 0)
#define S3C64XX_GPJ1_VD17 (0x02 << 2)
#define S3C64XX_GPJ2_VD18 (0x02 << 4)
#define S3C64XX_GPJ3_VD19 (0x02 << 6)
#define S3C64XX_GPJ4_VD20 (0x02 << 8)
#define S3C64XX_GPJ5_VD21 (0x02 << 10)
#define S3C64XX_GPJ6_VD22 (0x02 << 12)
#define S3C64XX_GPJ7_VD23 (0x02 << 14)
#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank N register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPN0_EINT0 (0x02 << 0)
#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
#define S3C64XX_GPN1_EINT1 (0x02 << 2)
#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
#define S3C64XX_GPN2_EINT2 (0x02 << 4)
#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
#define S3C64XX_GPN3_EINT3 (0x02 << 6)
#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
#define S3C64XX_GPN4_EINT4 (0x02 << 8)
#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
#define S3C64XX_GPN5_EINT5 (0x02 << 10)
#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
#define S3C64XX_GPN6_EINT6 (0x02 << 12)
#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
#define S3C64XX_GPN7_EINT7 (0x02 << 14)
#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
#define S3C64XX_GPN8_EINT8 (0x02 << 16)
#define S3C64XX_GPN9_EINT9 (0x02 << 18)
#define S3C64XX_GPN10_EINT10 (0x02 << 20)
#define S3C64XX_GPN11_EINT11 (0x02 << 22)
#define S3C64XX_GPN12_EINT12 (0x02 << 24)
#define S3C64XX_GPN13_EINT13 (0x02 << 26)
#define S3C64XX_GPN14_EINT14 (0x02 << 28)
#define S3C64XX_GPN15_EINT15 (0x02 << 30)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank O register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank P register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank Q register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
arch/arm/plat-s3c64xx/include/plat/irqs.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - Common IRQ support
*/
#ifndef __ASM_PLAT_S3C64XX_IRQS_H
#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*
* note, since we're using the VICs, our start must be a
* mulitple of 32 to allow the common code to work
*/
#define S3C_IRQ_OFFSET (32)
#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
#define S3C_VIC0_BASE S3C_IRQ(0)
#define S3C_VIC1_BASE S3C_IRQ(32)
/* UART interrupts, each UART has 4 intterupts per channel so
* use the space between the ISA and S3C main interrupts. Note, these
* are not in the same order as the S3C24XX series! */
#define IRQ_S3CUART_BASE0 (16)
#define IRQ_S3CUART_BASE1 (20)
#define IRQ_S3CUART_BASE2 (24)
#define IRQ_S3CUART_BASE3 (28)
#define UART_IRQ_RXD (0)
#define UART_IRQ_ERR (1)
#define UART_IRQ_TXD (2)
#define UART_IRQ_MODEM (3)
#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
/* VIC based IRQs */
#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
/* VIC0 */
#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
#define IRQ_2D S3C64XX_IRQ_VIC0(11)
#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
/* VIC1 */
#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
#define IRQ_UHOST S3C64XX_IRQ_VIC1(15)
#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
#define IRQ_TC IRQ_PENDN
#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
/* compatibility for device defines */
#define IRQ_IIC1 IRQ_S3C6410_IIC1
/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
* we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
* which we place after the pair of VICs. */
#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
#define IRQ_EINT(x) S3C_EINT(x)
/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
* that they are sourced from the GPIO pins but with a different scheme for
* priority and source indication.
*
* The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
* interrupts, but for historical reasons they are kept apart from these
* next interrupts.
*
* Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
* machine specific support files.
*/
#define IRQ_EINT_GROUP1_NR (15)
#define IRQ_EINT_GROUP2_NR (8)
#define IRQ_EINT_GROUP3_NR (5)
#define IRQ_EINT_GROUP4_NR (14)
#define IRQ_EINT_GROUP5_NR (7)
#define IRQ_EINT_GROUP6_NR (10)
#define IRQ_EINT_GROUP7_NR (16)
#define IRQ_EINT_GROUP8_NR (15)
#define IRQ_EINT_GROUP9_NR (9)
#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x))
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
arch/arm/plat-s3c64xx/include/plat/pll.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/include/plat/pll.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX PLL code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
#define S3C6400_PLL_MDIV_SHIFT (16)
#define S3C6400_PLL_PDIV_SHIFT (8)
#define S3C6400_PLL_SDIV_SHIFT (0)
#include <asm/div64.h>
static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
u32 pllcon)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
#define S3C6400_EPLL_MDIV_SHIFT (16)
#define S3C6400_EPLL_PDIV_SHIFT (8)
#define S3C6400_EPLL_SDIV_SHIFT (0)
#define S3C6400_EPLL_KDIV_MASK (0xffff)
static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
{
unsigned long result;
u32 epll0 = __raw_readl(S3C_EPLL_CON0);
u32 epll1 = __raw_readl(S3C_EPLL_CON1);
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
/* We need to multiple baseclk by mdiv (the integer part) and kdiv
* which is in 2^16ths, so shift mdiv up (does not overflow) and
* add kdiv before multiplying. The use of tmp is to avoid any
* overflows before shifting bac down into result when multipling
* by the mdiv and kdiv pair.
*/
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
}
arch/arm/plat-s3c64xx/include/plat/regs-clock.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_CLOCK_H
#define __PLAT_REGS_CLOCK_H __FILE__
#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
#define S3C_APLL_LOCK S3C_CLKREG(0x00)
#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
#define S3C_APLL_CON S3C_CLKREG(0x0C)
#define S3C_MPLL_CON S3C_CLKREG(0x10)
#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
#define S3C_CLK_SRC S3C_CLKREG(0x1C)
#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
#define S3C_CLK_OUT S3C_CLKREG(0x2C)
#define S3C_HCLK_GATE S3C_CLKREG(0x30)
#define S3C_PCLK_GATE S3C_CLKREG(0x34)
#define S3C_SCLK_GATE S3C_CLKREG(0x38)
/* CLKDIV0 */
#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
#define S3C6400_CLKDIV0_MFC_SHIFT (28)
#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24)
#define S3C6400_CLKDIV0_JPEG_SHIFT (24)
#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20)
#define S3C6400_CLKDIV0_CAM_SHIFT (20)
#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18)
#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0)
#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0)
#define S3C6400_CLKDIV0_ARM_SHIFT (0)
/* CLKDIV1 */
#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24)
#define S3C6410_CLKDIV1_FIMC_SHIFT (24)
#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20)
#define S3C6400_CLKDIV1_UHOST_SHIFT (20)
#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16)
#define S3C6400_CLKDIV1_SCALER_SHIFT (16)
#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12)
#define S3C6400_CLKDIV1_LCD_SHIFT (12)
#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8)
#define S3C6400_CLKDIV1_MMC2_SHIFT (8)
#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4)
#define S3C6400_CLKDIV1_MMC1_SHIFT (4)
#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0)
#define S3C6400_CLKDIV1_MMC0_SHIFT (0)
/* CLKDIV2 */
#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24)
#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24)
#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20)
#define S3C6400_CLKDIV2_IRDA_SHIFT (20)
#define S3C6400_CLKDIV2_UART_MASK (0xf << 16)
#define S3C6400_CLKDIV2_UART_SHIFT (16)
#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12)
#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12)
#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8)
#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8)
#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4)
#define S3C6400_CLKDIV2_SPI1_SHIFT (4)
#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0)
#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
/* HCLK GATE Registers */
#define S3C_CLKCON_HCLK_BUS (1<<30)
#define S3C_CLKCON_HCLK_SECUR (1<<29)
#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
#define S3C_CLKCON_HCLK_UHOST (1<<26)
#define S3C_CLKCON_HCLK_IROM (1<<25)
#define S3C_CLKCON_HCLK_DDR1 (1<<24)
#define S3C_CLKCON_HCLK_DDR0 (1<<23)
#define S3C_CLKCON_HCLK_MEM1 (1<<22)
#define S3C_CLKCON_HCLK_MEM0 (1<<21)
#define S3C_CLKCON_HCLK_USB (1<<20)
#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
#define S3C_CLKCON_HCLK_MDP (1<<16)
#define S3C_CLKCON_HCLK_DHOST (1<<15)
#define S3C_CLKCON_HCLK_IHOST (1<<14)
#define S3C_CLKCON_HCLK_DMA1 (1<<13)
#define S3C_CLKCON_HCLK_DMA0 (1<<12)
#define S3C_CLKCON_HCLK_JPEG (1<<11)
#define S3C_CLKCON_HCLK_CAMIF (1<<10)
#define S3C_CLKCON_HCLK_SCALER (1<<9)
#define S3C_CLKCON_HCLK_2D (1<<8)
#define S3C_CLKCON_HCLK_TV (1<<7)
#define S3C_CLKCON_HCLK_POST0 (1<<5)
#define S3C_CLKCON_HCLK_ROT (1<<4)
#define S3C_CLKCON_HCLK_LCD (1<<3)
#define S3C_CLKCON_HCLK_TZIC (1<<2)
#define S3C_CLKCON_HCLK_INTC (1<<1)
#define S3C_CLKCON_HCLK_MFC (1<<0)
/* PCLK GATE Registers */
#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
#define S3C_CLKCON_PCLK_SKEY (1<<24)
#define S3C_CLKCON_PCLK_CHIPID (1<<23)
#define S3C_CLKCON_PCLK_SPI1 (1<<22)
#define S3C_CLKCON_PCLK_SPI0 (1<<21)
#define S3C_CLKCON_PCLK_HSIRX (1<<20)
#define S3C_CLKCON_PCLK_HSITX (1<<19)
#define S3C_CLKCON_PCLK_GPIO (1<<18)
#define S3C_CLKCON_PCLK_IIC (1<<17)
#define S3C_CLKCON_PCLK_IIS1 (1<<16)
#define S3C_CLKCON_PCLK_IIS0 (1<<15)
#define S3C_CLKCON_PCLK_AC97 (1<<14)
#define S3C_CLKCON_PCLK_TZPC (1<<13)
#define S3C_CLKCON_PCLK_TSADC (1<<12)
#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
#define S3C_CLKCON_PCLK_IRDA (1<<10)
#define S3C_CLKCON_PCLK_PCM1 (1<<9)
#define S3C_CLKCON_PCLK_PCM0 (1<<8)
#define S3C_CLKCON_PCLK_PWM (1<<7)
#define S3C_CLKCON_PCLK_RTC (1<<6)
#define S3C_CLKCON_PCLK_WDT (1<<5)
#define S3C_CLKCON_PCLK_UART3 (1<<4)
#define S3C_CLKCON_PCLK_UART2 (1<<3)
#define S3C_CLKCON_PCLK_UART1 (1<<2)
#define S3C_CLKCON_PCLK_UART0 (1<<1)
#define S3C_CLKCON_PCLK_MFC (1<<0)
/* SCLK GATE Registers */
#define S3C_CLKCON_SCLK_UHOST (1<<30)
#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
#define S3C_CLKCON_SCLK_MMC2 (1<<26)
#define S3C_CLKCON_SCLK_MMC1 (1<<25)
#define S3C_CLKCON_SCLK_MMC0 (1<<24)
#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
#define S3C_CLKCON_SCLK_SPI1 (1<<21)
#define S3C_CLKCON_SCLK_SPI0 (1<<20)
#define S3C_CLKCON_SCLK_DAC27 (1<<19)
#define S3C_CLKCON_SCLK_TV27 (1<<18)
#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
#define S3C_CLKCON_SCLK_SCALER (1<<16)
#define S3C_CLKCON_SCLK_LCD27 (1<<15)
#define S3C_CLKCON_SCLK_LCD (1<<14)
#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
#define S3C6410_CLKCON_FIMC (1<<13)
#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
#define S3C_CLKCON_SCLK_POST0 (1<<10)
#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
#define S3C_CLKCON_SCLK_SECUR (1<<7)
#define S3C_CLKCON_SCLK_IRDA (1<<6)
#define S3C_CLKCON_SCLK_UART (1<<5)
#define S3C_CLKCON_SCLK_ONENAND (1<<4)
#define S3C_CLKCON_SCLK_MFC (1<<3)
#define S3C_CLKCON_SCLK_CAM (1<<2)
#define S3C_CLKCON_SCLK_JPEG (1<<1)
/* CLKSRC */
#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
#define S3C6400_CLKSRC_MFC (1 << 4)
#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31)
#define S3C6410_CLKSRC_TV27_SHIFT (31)
#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30)
#define S3C6410_CLKSRC_DAC27_SHIFT (30)
#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28)
#define S3C6400_CLKSRC_SCALER_SHIFT (28)
#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26)
#define S3C6400_CLKSRC_LCD_SHIFT (26)
#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24)
#define S3C6400_CLKSRC_IRDA_SHIFT (24)
#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22)
#define S3C6400_CLKSRC_MMC2_SHIFT (22)
#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
#define S3C6400_CLKSRC_MMC1_SHIFT (20)
#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
#define S3C6400_CLKSRC_MMC0_SHIFT (18)
#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
#define S3C6400_CLKSRC_SPI1_SHIFT (16)
#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
#define S3C6400_CLKSRC_SPI0_SHIFT (14)
#define S3C6400_CLKSRC_UART_MASK (0x1 << 13)
#define S3C6400_CLKSRC_UART_SHIFT (13)
#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10)
#define S3C6400_CLKSRC_AUDIO1_SHIFT (10)
#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7)
#define S3C6400_CLKSRC_AUDIO0_SHIFT (7)
#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5)
#define S3C6400_CLKSRC_UHOST_SHIFT (5)
#endif /* _PLAT_REGS_CLOCK_H */
arch/arm/plat-s3c64xx/include/plat/regs-gpio.h 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIO register definitions
*/
#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
/* Base addresses for each of the banks */
#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000)
#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020)
#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040)
#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060)
#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080)
#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0)
#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0)
#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0)
#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100)
#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120)
#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800)
#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810)
#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820)
#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830)
#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140)
#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160)
#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180)
#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
arch/arm/plat-s3c64xx/include/plat/regs-sys.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX system register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_SYS_H
#define __PLAT_REGS_SYS_H __FILE__
#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
#define S3C64XX_OTHERS S3C_SYSREG(0x900)
#define S3C64XX_OTHERS_USBMASK (1 << 16)
#endif /* _PLAT_REGS_SYS_H */
arch/arm/plat-s3c64xx/include/plat/s3c6400.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Header file for s3c6400 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S3C6400 related SoCs */
extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s3c6400_register_clocks(void);
extern void s3c6400_setup_clocks(void);
#ifdef CONFIG_CPU_S3C6400
extern int s3c6400_init(void);
extern void s3c6400_map_io(void);
extern void s3c6400_init_clocks(int xtal);
#define s3c6400_init_uarts s3c6400_common_init_uarts
#else
#define s3c6400_init_clocks NULL
#define s3c6400_init_uarts NULL
#define s3c6400_map_io NULL
#define s3c6400_init NULL
#endif
arch/arm/plat-s3c64xx/include/plat/s3c6410.h 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Header file for s3c6410 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_CPU_S3C6410
extern int s3c6410_init(void);
extern void s3c6410_init_irq(void);
extern void s3c6410_map_io(void);
extern void s3c6410_init_clocks(int xtal);
#define s3c6410_init_uarts s3c6400_common_init_uarts
#else
#define s3c6410_init_clocks NULL
#define s3c6410_init_uarts NULL
#define s3c6410_map_io NULL
#define s3c6410_init NULL
#endif
arch/arm/plat-s3c64xx/irq-eint.c 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/irq-eint.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - Interrupt handling for IRQ_EINT(x)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware/vic.h>
#include <plat/regs-irqtype.h>
#include <mach/map.h>
#include <plat/cpu.h>
/* GPIO is 0x7F008xxx, */
#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
static inline void s3c_irq_eint_mask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S3C64XX_EINT0MASK);
}
static void s3c_irq_eint_unmask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S3C64XX_EINT0MASK);
}
static inline void s3c_irq_eint_ack(unsigned int irq)
{
__raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
}
static void s3c_irq_eint_maskack(unsigned int irq)
{
/* compiler should in-line these */
s3c_irq_eint_mask(irq);
s3c_irq_eint_ack(irq);
}
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
void __iomem *reg;
if (offs > 27)
return -EINVAL;
if (offs <= 15)
reg = S3C64XX_EINT0CON0;
else
reg = S3C64XX_EINT0CON1;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
shift = (offs / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, reg);
return 0;
}
static struct irq_chip s3c_irq_eint = {
.name = "s3c-eint",
.mask = s3c_irq_eint_mask,
.unmask = s3c_irq_eint_unmask,
.mask_ack = s3c_irq_eint_maskack,
.ack = s3c_irq_eint_ack,
.set_type = s3c_irq_eint_set_type,
};
/* s3c_irq_demux_eint
*
* This function demuxes the IRQ from the group0 external interrupts,
* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
* the specific handlers s3c_irq_demux_eintX_Y.
*/
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
u32 status = __raw_readl(S3C64XX_EINT0PEND);
u32 mask = __raw_readl(S3C64XX_EINT0MASK);
unsigned int irq;
status &= ~mask;
status >>= start;
status &= (1 << (end - start + 1)) - 1;
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
if (status & 1)
generic_handle_irq(irq);
status >>= 1;
}
}
static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_eint(0, 3);
}
static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_eint(4, 11);
}
static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_eint(12, 19);
}
static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_eint(20, 27);
}
int __init s3c64xx_init_irq_eint(void)
{
int irq;
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
set_irq_chip(irq, &s3c_irq_eint);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
return 0;
}
arch_initcall(s3c64xx_init_irq_eint);
arch/arm/plat-s3c64xx/irq.c 0 → 100644
View file @ fdb0a1a6
/* arch/arm/plat-s3c64xx/irq.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - Interrupt handling
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <plat/cpu.h>
/* Timer interrupt handling */
static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
{
generic_handle_irq(sub_irq);
}
static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER0);
}
static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER1);
}
static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER2);
}
static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER3);
}
static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER4);
}
/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
static void s3c_irq_timer_mask(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f; /* mask out pending interrupts */
reg &= ~(1 << (irq - IRQ_TIMER0));
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static void s3c_irq_timer_unmask(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f; /* mask out pending interrupts */
reg |= 1 << (irq - IRQ_TIMER0);
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static void s3c_irq_timer_ack(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f;
reg |= (1 << 5) << (irq - IRQ_TIMER0);
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static struct irq_chip s3c_irq_timer = {
.name = "s3c-timer",
.mask = s3c_irq_timer_mask,
.unmask = s3c_irq_timer_unmask,
.ack = s3c_irq_timer_ack,
};
struct uart_irq {
void __iomem *regs;
unsigned int base_irq;
unsigned int parent_irq;
};
/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
* are consecutive when looking up the interrupt in the demux routines.
*/
static struct uart_irq uart_irqs[] = {
[0] = {
.regs = S3C_VA_UART0,
.base_irq = IRQ_S3CUART_BASE0,
.parent_irq = IRQ_UART0,
},
[1] = {
.regs = S3C_VA_UART1,
.base_irq = IRQ_S3CUART_BASE1,
.parent_irq = IRQ_UART1,
},
[2] = {
.regs = S3C_VA_UART2,
.base_irq = IRQ_S3CUART_BASE2,
.parent_irq = IRQ_UART2,
},
[3] = {
.regs = S3C_VA_UART3,
.base_irq = IRQ_S3CUART_BASE3,
.parent_irq = IRQ_UART3,
},
};
static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
{
struct uart_irq *uirq = get_irq_chip_data(irq);
return uirq->regs;
}
static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
{
return irq & 3;
}
/* UART interrupt registers, not worth adding to seperate include header */
#define S3C64XX_UINTP 0x30
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38
static void s3c_irq_uart_mask(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg |= (1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
}
static void s3c_irq_uart_maskack(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg |= (1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
__raw_writel(1 << bit, regs + S3C64XX_UINTP);
}
static void s3c_irq_uart_unmask(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg &= ~(1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
}
static void s3c_irq_uart_ack(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
__raw_writel(1 << bit, regs + S3C64XX_UINTP);
}
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
if (pend & (1 << 0))
generic_handle_irq(base);
if (pend & (1 << 1))
generic_handle_irq(base + 1);
if (pend & (1 << 2))
generic_handle_irq(base + 2);
if (pend & (1 << 3))
generic_handle_irq(base + 3);
}
static struct irq_chip s3c_irq_uart = {
.name = "s3c-uart",
.mask = s3c_irq_uart_mask,
.unmask = s3c_irq_uart_unmask,
.mask_ack = s3c_irq_uart_maskack,
.ack = s3c_irq_uart_ack,
};
static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
{
void *reg_base = uirq->regs;
unsigned int irq;
int offs;
/* mask all interrupts at the start. */
__raw_writel(0xf, reg_base + S3C64XX_UINTM);
for (offs = 0; offs < 3; offs++) {
irq = uirq->base_irq + offs;
set_irq_chip(irq, &s3c_irq_uart);
set_irq_chip_data(irq, uirq);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
}
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
int uart, irq;
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
/* add the timer sub-irqs */
set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
set_irq_chip(irq, &s3c_irq_timer);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
s3c64xx_uart_irq(&uart_irqs[uart]);
}
arch/arm/plat-s3c64xx/s3c6400-clock.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 based common clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <plat/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
*/
struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
.id = -1,
};
#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fout_mpll clk_mpll
struct clk_sources {
unsigned int nr_sources;
struct clk **sources;
};
struct clksrc_clk {
struct clk clk;
unsigned int mask;
unsigned int shift;
struct clk_sources *sources;
unsigned int divider_shift;
void __iomem *reg_divider;
};
struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
};
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
};
static struct clk_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
.mask = S3C6400_CLKSRC_APLL_MOUT,
.sources = &clk_src_apll,
};
struct clk clk_fout_epll = {
.name = "fout_epll",
.id = -1,
};
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
static struct clk_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
.mask = S3C6400_CLKSRC_EPLL_MOUT,
.sources = &clk_src_epll,
};
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
static struct clk_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
.mask = S3C6400_CLKSRC_MPLL_MOUT,
.sources = &clk_src_mpll,
};
static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
rate /= 2;
return rate;
}
struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
.get_rate = s3c64xx_clk_doutmpll_get_rate,
};
static struct clk *clkset_spi_mmc_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_27m,
};
static struct clk_sources clkset_spi_mmc = {
.sources = clkset_spi_mmc_list,
.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
};
static struct clk *clkset_irda_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
&clk_27m,
};
static struct clk_sources clkset_irda = {
.sources = clkset_irda_list,
.nr_sources = ARRAY_SIZE(clkset_irda_list),
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
NULL
};
static struct clk_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_uhost_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_48m,
};
static struct clk_sources clkset_uhost = {
.sources = clkset_uhost_list,
.nr_sources = ARRAY_SIZE(clkset_uhost_list),
};
/* The peripheral clocks are all controlled via clocksource followed
* by an optional divider and gate stage. We currently roll this into
* one clock which hides the intermediate clock from the mux.
*
* Note, the JPEG clock can only be an even divider...
*
* The scaler and LCD clocks depend on the S3C64XX version, and also
* have a common parent divisor so are not included here.
*/
static inline struct clksrc_clk *to_clksrc(struct clk *clk)
{
return container_of(clk, struct clksrc_clk, clk);
}
static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
{
struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv = __raw_readl(sclk->reg_divider);
clkdiv >>= sclk->divider_shift;
clkdiv &= 0xf;
clkdiv++;
rate /= clkdiv;
return rate;
}
static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
{
struct clksrc_clk *sclk = to_clksrc(clk);
void __iomem *reg = sclk->reg_divider;
unsigned int div;
u32 val;
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
val = __raw_readl(reg);
val &= ~sclk->mask;
val |= (rate - 1) << sclk->shift;
__raw_writel(val, reg);
return 0;
}
static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
{
struct clksrc_clk *sclk = to_clksrc(clk);
struct clk_sources *srcs = sclk->sources;
u32 clksrc = __raw_readl(S3C_CLK_SRC);
int src_nr = -1;
int ptr;
for (ptr = 0; ptr < srcs->nr_sources; ptr++)
if (srcs->sources[ptr] == parent) {
src_nr = ptr;
break;
}
if (src_nr >= 0) {
clksrc &= ~sclk->mask;
clksrc |= src_nr << sclk->shift;
__raw_writel(clksrc, S3C_CLK_SRC);
return 0;
}
return -EINVAL;
}
static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
unsigned long rate)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
int div;
if (rate > parent_rate)
rate = parent_rate;
else {
div = rate / parent_rate;
if (div == 0)
div = 1;
if (div > 16)
div = 16;
rate = parent_rate / div;
}
return rate;
}
static struct clksrc_clk clk_mmc0 = {
.clk = {
.name = "mmc_bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC0_SHIFT,
.mask = S3C6400_CLKSRC_MMC0_MASK,
.sources = &clkset_spi_mmc,
.divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
.reg_divider = S3C_CLK_DIV1,
};
static struct clksrc_clk clk_mmc1 = {
.clk = {
.name = "mmc_bus",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.set_parent = s3c64xx_setparent_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC1_SHIFT,
.mask = S3C6400_CLKSRC_MMC1_MASK,
.sources = &clkset_spi_mmc,
.divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
.reg_divider = S3C_CLK_DIV1,
};
static struct clksrc_clk clk_mmc2 = {
.clk = {
.name = "mmc_bus",
.id = 2,
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.set_parent = s3c64xx_setparent_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_MMC2_SHIFT,
.mask = S3C6400_CLKSRC_MMC2_MASK,
.sources = &clkset_spi_mmc,
.divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
.reg_divider = S3C_CLK_DIV1,
};
static struct clksrc_clk clk_usbhost = {
.clk = {
.name = "usb-host-bus",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_UHOST_SHIFT,
.mask = S3C6400_CLKSRC_UHOST_MASK,
.sources = &clkset_uhost,
.divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
.reg_divider = S3C_CLK_DIV1,
};
static struct clksrc_clk clk_uart_uclk1 = {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_UART_SHIFT,
.mask = S3C6400_CLKSRC_UART_MASK,
.sources = &clkset_uart,
.divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
/* Where does UCLK0 come from? */
static struct clksrc_clk clk_spi0 = {
.clk = {
.name = "spi-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_SPI0_SHIFT,
.mask = S3C6400_CLKSRC_SPI0_MASK,
.sources = &clkset_spi_mmc,
.divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
static struct clksrc_clk clk_spi1 = {
.clk = {
.name = "spi-bus",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_SPI1_SHIFT,
.mask = S3C6400_CLKSRC_SPI1_MASK,
.sources = &clkset_spi_mmc,
.divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
.id = -1,
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
};
static struct clk *clkset_audio0_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iis_cd0,
[4] = &clk_pcm_cd,
};
static struct clk_sources clkset_audio0 = {
.sources = clkset_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
};
static struct clksrc_clk clk_audio0 = {
.clk = {
.name = "audio-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
.mask = S3C6400_CLKSRC_AUDIO0_MASK,
.sources = &clkset_audio0,
.divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
static struct clk *clkset_audio1_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iis_cd1,
[4] = &clk_pcm_cd,
};
static struct clk_sources clkset_audio1 = {
.sources = clkset_audio1_list,
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
static struct clksrc_clk clk_audio1 = {
.clk = {
.name = "audio-bus",
.id = 1,
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
.mask = S3C6400_CLKSRC_AUDIO1_MASK,
.sources = &clkset_audio1,
.divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
static struct clksrc_clk clk_irda = {
.clk = {
.name = "irda-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
.set_parent = s3c64xx_setparent_clksrc,
.get_rate = s3c64xx_getrate_clksrc,
.set_rate = s3c64xx_setrate_clksrc,
.round_rate = s3c64xx_roundrate_clksrc,
},
.shift = S3C6400_CLKSRC_IRDA_SHIFT,
.mask = S3C6400_CLKSRC_IRDA_MASK,
.sources = &clkset_irda,
.divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
.reg_divider = S3C_CLK_DIV2,
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_mmc0,
&clk_mmc1,
&clk_mmc2,
&clk_usbhost,
&clk_uart_uclk1,
&clk_spi0,
&clk_spi1,
&clk_audio0,
&clk_audio1,
&clk_irda,
};
static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
{
struct clk_sources *srcs = clk->sources;
u32 clksrc = __raw_readl(S3C_CLK_SRC);
clksrc &= clk->mask;
clksrc >>= clk->shift;
if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
printk(KERN_ERR "%s: bad source %d\n",
clk->clk.name, clksrc);
return;
}
clk->clk.parent = srcs->sources[clksrc];
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
clk->clk.name, clk->clk.parent->name, clksrc,
clk_get_rate(&clk->clk));
}
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
void __init_or_cpufreq s3c6400_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk2;
unsigned long pclk;
unsigned long epll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
u32 clkdiv0;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
epll = s3c6400_get_epll(xtal);
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
fclk = mpll;
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
hclk2, hclk, pclk);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = fclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c6400_set_clksrc(init_parents[ptr]);
}
static struct clk *clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_iis_cd0,
&clk_iis_cd1,
&clk_pcm_cd,
&clk_mout_epll.clk,
&clk_fout_epll,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_mmc0.clk,
&clk_mmc1.clk,
&clk_mmc2.clk,
&clk_usbhost.clk,
&clk_uart_uclk1.clk,
&clk_spi0.clk,
&clk_spi1.clk,
&clk_audio0.clk,
&clk_audio1.clk,
&clk_irda.clk,
};
void __init s3c6400_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clk_mpll.parent = &clk_mout_mpll.clk;
clk_epll.parent = &clk_mout_epll.clk;
}
arch/arm/plat-s3c64xx/s3c6400-init.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - CPU initialisation (common with other S3C64XX chips)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* uart registration process */
void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}
arch/arm/plat-s3c64xx/setup-fb-24bpp.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX setup information for 24bpp LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <mach/regs-fb.h>
#include <mach/gpio.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
extern void s3c64xx_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
arch/arm/plat-s3c64xx/setup-i2c0.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX I2C bus 0 gpio configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
}
arch/arm/plat-s3c64xx/setup-i2c1.c 0 → 100644
View file @ fdb0a1a6
/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX I2C bus 1 gpio configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
}
drivers/serial/Kconfig
View file @ fdb0a1a6
......@@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE
config SERIAL_SAMSUNG
tristate "Samsung SoC serial support"
depends on ARM && PLAT_S3C24XX
depends on ARM && PLAT_S3C
select SERIAL_CORE
help
Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
......@@ -455,6 +455,16 @@ config SERIAL_SAMSUNG
provide all of these ports, depending on how the serial port
pins are configured.
config SERIAL_SAMSUNG_UARTS
int
depends on SERIAL_SAMSUNG
default 2 if ARCH_S3C2400
default 4 if ARCH_S3C64XX || CPU_S3C2443
default 3
help
Select the number of available UART ports for the Samsung S3C
serial driver
config SERIAL_SAMSUNG_DEBUG
bool "Samsung SoC serial debug"
depends on SERIAL_SAMSUNG && DEBUG_LL
......@@ -508,7 +518,20 @@ config SERIAL_S3C2440
help
Serial port support for the Samsung S3C2440 and S3C2442 SoC
config SERIAL_S3C24A0
tristate "Samsung S3C24A0 Serial port support"
depends on SERIAL_SAMSUNG && CPU_S3C24A0
default y if CPU_S3C24A0
help
Serial port support for the Samsung S3C24A0 SoC
config SERIAL_S3C6400
tristate "Samsung S3C6400/S3C6410 Serial port support"
depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410)
default y
help
Serial port support for the Samsung S3C6400 and S3C6410
SoCs
config SERIAL_DZ
bool "DECstation DZ serial driver"
......
drivers/serial/Makefile
View file @ fdb0a1a6
......@@ -41,6 +41,8 @@ obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o
obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_68328) += 68328serial.o
......
drivers/serial/s3c24a0.c 0 → 100644
View file @ fdb0a1a6
/* linux/drivers/serial/s3c24a0.c
*
* Driver for Samsung S3C24A0 SoC onboard UARTs.
*
* Based on drivers/serial/s3c2410.c
*
* Author: Sandeep Patil <sandeep.patil@azingo.com>
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include "samsung.h"
static int s3c24a0_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
if (strcmp(clk->name, "uclk") == 0)
ucon |= S3C2410_UCON_UCLK;
else
ucon &= ~S3C2410_UCON_UCLK;
wr_regl(port, S3C2410_UCON, ucon);
return 0;
}
static int s3c24a0_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
clk->divisor = 1;
clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
return 0;
}
static int s3c24a0_serial_resetport(struct uart_port *port,
struct s3c2410_uartcfg *cfg)
{
dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
port, port->mapbase, cfg);
wr_regl(port, S3C2410_UCON, cfg->ucon);
wr_regl(port, S3C2410_ULCON, cfg->ulcon);
/* reset both fifos */
wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
wr_regl(port, S3C2410_UFCON, cfg->ufcon);
return 0;
}
static struct s3c24xx_uart_info s3c24a0_uart_inf = {
.name = "Samsung S3C24A0 UART",
.type = PORT_S3C2410,
.fifosize = 16,
.rx_fifomask = S3C24A0_UFSTAT_RXMASK,
.rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT,
.rx_fifofull = S3C24A0_UFSTAT_RXFULL,
.tx_fifofull = S3C24A0_UFSTAT_TXFULL,
.tx_fifomask = S3C24A0_UFSTAT_TXMASK,
.tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT,
.get_clksrc = s3c24a0_serial_getsource,
.set_clksrc = s3c24a0_serial_setsource,
.reset_port = s3c24a0_serial_resetport,
};
static int s3c24a0_serial_probe(struct platform_device *dev)
{
return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
}
static struct platform_driver s3c24a0_serial_drv = {
.probe = s3c24a0_serial_probe,
.remove = s3c24xx_serial_remove,
.driver = {
.name = "s3c24a0-uart",
.owner = THIS_MODULE,
},
};
s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
static int __init s3c24a0_serial_init(void)
{
return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
}
static void __exit s3c24a0_serial_exit(void)
{
platform_driver_unregister(&s3c24a0_serial_drv);
}
module_init(s3c24a0_serial_init);
module_exit(s3c24a0_serial_exit);
drivers/serial/s3c6400.c 0 → 100644
View file @ fdb0a1a6
/* linux/drivers/serial/s3c6400.c
*
* Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <plat/regs-serial.h>
#include "samsung.h"
static int s3c6400_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
if (strcmp(clk->name, "uclk0") == 0) {
ucon &= ~S3C6400_UCON_CLKMASK;
ucon |= S3C6400_UCON_UCLK0;
} else if (strcmp(clk->name, "uclk1") == 0)
ucon |= S3C6400_UCON_UCLK1;
else if (strcmp(clk->name, "pclk") == 0) {
/* See notes about transitioning from UCLK to PCLK */
ucon &= ~S3C6400_UCON_UCLK0;
} else {
printk(KERN_ERR "unknown clock source %s\n", clk->name);
return -EINVAL;
}
wr_regl(port, S3C2410_UCON, ucon);
return 0;
}
static int s3c6400_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
u32 ucon = rd_regl(port, S3C2410_UCON);
clk->divisor = 1;
switch (ucon & S3C6400_UCON_CLKMASK) {
case S3C6400_UCON_UCLK0:
clk->name = "uclk0";
break;
case S3C6400_UCON_UCLK1:
clk->name = "uclk1";
break;
case S3C6400_UCON_PCLK:
case S3C6400_UCON_PCLK2:
clk->name = "pclk";
break;
}
return 0;
}
static int s3c6400_serial_resetport(struct uart_port *port,
struct s3c2410_uartcfg *cfg)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
port, port->mapbase, cfg);
/* ensure we don't change the clock settings... */
ucon &= S3C6400_UCON_CLKMASK;
wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
wr_regl(port, S3C2410_ULCON, cfg->ulcon);
/* reset both fifos */
wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
wr_regl(port, S3C2410_UFCON, cfg->ufcon);
return 0;
}
static struct s3c24xx_uart_info s3c6400_uart_inf = {
.name = "Samsung S3C6400 UART",
.type = PORT_S3C6400,
.fifosize = 64,
.rx_fifomask = S3C2440_UFSTAT_RXMASK,
.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
.rx_fifofull = S3C2440_UFSTAT_RXFULL,
.tx_fifofull = S3C2440_UFSTAT_TXFULL,
.tx_fifomask = S3C2440_UFSTAT_TXMASK,
.tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
.get_clksrc = s3c6400_serial_getsource,
.set_clksrc = s3c6400_serial_setsource,
.reset_port = s3c6400_serial_resetport,
};
/* device management */
static int s3c6400_serial_probe(struct platform_device *dev)
{
dbg("s3c6400_serial_probe: dev=%p\n", dev);
return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
}
static struct platform_driver s3c6400_serial_drv = {
.probe = s3c6400_serial_probe,
.remove = s3c24xx_serial_remove,
.driver = {
.name = "s3c6400-uart",
.owner = THIS_MODULE,
},
};
s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
static int __init s3c6400_serial_init(void)
{
return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
}
static void __exit s3c6400_serial_exit(void)
{
platform_driver_unregister(&s3c6400_serial_drv);
}
module_init(s3c6400_serial_init);
module_exit(s3c6400_serial_exit);
MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:s3c6400-uart");
drivers/serial/samsung.c
View file @ fdb0a1a6
......@@ -42,13 +42,14 @@
#include <linux/serial.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include "samsung.h"
......@@ -58,19 +59,6 @@
#define S3C24XX_SERIAL_MAJOR 204
#define S3C24XX_SERIAL_MINOR 64
/* we can support 3 uarts, but not always use them */
#ifdef CONFIG_CPU_S3C2400
#define NR_PORTS (2)
#else
#define NR_PORTS (3)
#endif
/* port irq numbers */
#define TX_IRQ(port) ((port)->irq + 1)
#define RX_IRQ(port) ((port)->irq)
/* macros to change one thing to another */
#define tx_enabled(port) ((port)->unused[0])
......@@ -136,8 +124,10 @@ static void s3c24xx_serial_rx_disable(struct uart_port *port)
static void s3c24xx_serial_stop_tx(struct uart_port *port)
{
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (tx_enabled(port)) {
disable_irq(TX_IRQ(port));
disable_irq(ourport->tx_irq);
tx_enabled(port) = 0;
if (port->flags & UPF_CONS_FLOW)
s3c24xx_serial_rx_enable(port);
......@@ -146,11 +136,13 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
static void s3c24xx_serial_start_tx(struct uart_port *port)
{
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (!tx_enabled(port)) {
if (port->flags & UPF_CONS_FLOW)
s3c24xx_serial_rx_disable(port);
enable_irq(TX_IRQ(port));
enable_irq(ourport->tx_irq);
tx_enabled(port) = 1;
}
}
......@@ -158,9 +150,11 @@ static void s3c24xx_serial_start_tx(struct uart_port *port)
static void s3c24xx_serial_stop_rx(struct uart_port *port)
{
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (rx_enabled(port)) {
dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
disable_irq(RX_IRQ(port));
disable_irq(ourport->rx_irq);
rx_enabled(port) = 0;
}
}
......@@ -384,13 +378,13 @@ static void s3c24xx_serial_shutdown(struct uart_port *port)
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (ourport->tx_claimed) {
free_irq(TX_IRQ(port), ourport);
free_irq(ourport->tx_irq, ourport);
tx_enabled(port) = 0;
ourport->tx_claimed = 0;
}
if (ourport->rx_claimed) {
free_irq(RX_IRQ(port), ourport);
free_irq(ourport->rx_irq, ourport);
ourport->rx_claimed = 0;
rx_enabled(port) = 0;
}
......@@ -407,12 +401,11 @@ static int s3c24xx_serial_startup(struct uart_port *port)
rx_enabled(port) = 1;
ret = request_irq(RX_IRQ(port),
s3c24xx_serial_rx_chars, 0,
ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
s3c24xx_serial_portname(port), ourport);
if (ret != 0) {
printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
return ret;
}
......@@ -422,12 +415,11 @@ static int s3c24xx_serial_startup(struct uart_port *port)
tx_enabled(port) = 1;
ret = request_irq(TX_IRQ(port),
s3c24xx_serial_tx_chars, 0,
ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
s3c24xx_serial_portname(port), ourport);
if (ret) {
printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
goto err;
}
......@@ -452,6 +444,8 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
{
struct s3c24xx_uart_port *ourport = to_ourport(port);
ourport->pm_level = level;
switch (level) {
case 3:
if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
......@@ -661,6 +655,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
ourport->clksrc = clksrc;
ourport->baudclk = clk;
ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
}
switch (termios->c_cflag & CSIZE) {
......@@ -752,6 +747,8 @@ static const char *s3c24xx_serial_type(struct uart_port *port)
return "S3C2440";
case PORT_S3C2412:
return "S3C2412";
case PORT_S3C6400:
return "S3C6400/10";
default:
return NULL;
}
......@@ -827,14 +824,14 @@ static struct uart_ops s3c24xx_serial_ops = {
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.dev_name = "s3c2410_serial",
.nr = 3,
.nr = CONFIG_SERIAL_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.driver_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
[0] = {
.port = {
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
......@@ -859,7 +856,7 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
.line = 1,
}
},
#if NR_PORTS > 2
#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
[2] = {
.port = {
......@@ -872,6 +869,20 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
.flags = UPF_BOOT_AUTOCONF,
.line = 2,
}
},
#endif
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
[3] = {
.port = {
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
.iotype = UPIO_MEM,
.irq = IRQ_S3CUART_RX3,
.uartclk = 0,
.fifosize = 16,
.ops = &s3c24xx_serial_ops,
.flags = UPF_BOOT_AUTOCONF,
.line = 3,
}
}
#endif
};
......@@ -890,6 +901,89 @@ static inline int s3c24xx_serial_resetport(struct uart_port *port,
return (info->reset_port)(port, cfg);
}
#ifdef CONFIG_CPU_FREQ
static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
unsigned long val, void *data)
{
struct s3c24xx_uart_port *port;
struct uart_port *uport;
port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
uport = &port->port;
/* check to see if port is enabled */
if (port->pm_level != 0)
return 0;
/* try and work out if the baudrate is changing, we can detect
* a change in rate, but we do not have support for detecting
* a disturbance in the clock-rate over the change.
*/
if (IS_ERR(port->clk))
goto exit;
if (port->baudclk_rate == clk_get_rate(port->clk))
goto exit;
if (val == CPUFREQ_PRECHANGE) {
/* we should really shut the port down whilst the
* frequency change is in progress. */
} else if (val == CPUFREQ_POSTCHANGE) {
struct ktermios *termios;
struct tty_struct *tty;
if (uport->info == NULL)
goto exit;
tty = uport->info->port.tty;
if (tty == NULL)
goto exit;
termios = tty->termios;
if (termios == NULL) {
printk(KERN_WARNING "%s: no termios?\n", __func__);
goto exit;
}
s3c24xx_serial_set_termios(uport, termios, NULL);
}
exit:
return 0;
}
static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
{
port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
return cpufreq_register_notifier(&port->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
{
cpufreq_unregister_notifier(&port->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
#else
static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
{
return 0;
}
static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
{
}
#endif
/* s3c24xx_serial_init_port
*
* initialise a single serial port from the platform device given
......@@ -914,8 +1008,11 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
if (port->mapbase != 0)
return 0;
if (cfg->hwport > 3)
return -EINVAL;
if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
return -ERANGE;
}
/* setup info for port */
port->dev = &platdev->dev;
......@@ -943,18 +1040,26 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
port->mapbase = res->start;
port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
port->mapbase = res->start;
port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
ret = platform_get_irq(platdev, 0);
if (ret < 0)
port->irq = 0;
else
else {
port->irq = ret;
ourport->rx_irq = ret;
ourport->tx_irq = ret + 1;
}
ret = platform_get_irq(platdev, 1);
if (ret > 0)
ourport->tx_irq = ret;
ourport->clk = clk_get(&platdev->dev, "uart");
dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
port->mapbase, port->membase, port->irq, port->uartclk);
dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
port->mapbase, port->membase, port->irq,
ourport->rx_irq, ourport->tx_irq, port->uartclk);
/* reset the fifos (and setup the uart) */
s3c24xx_serial_resetport(port, cfg);
......@@ -1002,6 +1107,10 @@ int s3c24xx_serial_probe(struct platform_device *dev,
if (ret < 0)
printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
ret = s3c24xx_serial_cpufreq_register(ourport);
if (ret < 0)
dev_err(&dev->dev, "failed to add cpufreq notifier\n");
return 0;
probe_err:
......@@ -1015,6 +1124,7 @@ int s3c24xx_serial_remove(struct platform_device *dev)
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
if (port) {
s3c24xx_serial_cpufreq_deregister(to_ourport(port));
device_remove_file(&dev->dev, &dev_attr_clock_source);
uart_remove_one_port(&s3c24xx_uart_drv, port);
}
......@@ -1219,7 +1329,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
platdev_ptr = s3c24xx_uart_devs;
for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
}
......@@ -1240,7 +1350,7 @@ s3c24xx_serial_console_setup(struct console *co, char *options)
/* is this a valid port */
if (co->index == -1 || co->index >= NR_PORTS)
if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
co->index = 0;
port = &s3c24xx_serial_ports[co->index].port;
......
drivers/serial/samsung.h
View file @ fdb0a1a6
......@@ -33,12 +33,21 @@ struct s3c24xx_uart_info {
struct s3c24xx_uart_port {
unsigned char rx_claimed;
unsigned char tx_claimed;
unsigned int pm_level;
unsigned long baudclk_rate;
unsigned int rx_irq;
unsigned int tx_irq;
struct s3c24xx_uart_info *info;
struct s3c24xx_uart_clksrc *clksrc;
struct clk *clk;
struct clk *baudclk;
struct uart_port port;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
};
/* conversion functions */
......
include/linux/serial_core.h
View file @ fdb0a1a6
......@@ -158,6 +158,8 @@
/* SH-SCI */
#define PORT_SCIFA 83
#define PORT_S3C6400 84
#ifdef __KERNEL__
#include <linux/compiler.h>
......
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