Commit febdfbd2 authored by James Bottomley's avatar James Bottomley

Merge tag '4.4-scsi-mkp' into misc

SCSI queue for 4.4.
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents 0da39687 2c5d16d6
* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
Each UFS PHY node should have its own node.
To bind UFS PHY with UFS host controller, the controller node should
contain a phandle reference to UFS PHY node.
Required properties:
- compatible : compatible list, contains "qcom,ufs-phy-qmp-20nm"
or "qcom,ufs-phy-qmp-14nm" according to the relevant phy in use.
- reg : should contain PHY register address space (mandatory),
- reg-names : indicates various resources passed to driver (via reg proptery) by name.
Required "reg-names" is "phy_mem".
- #phy-cells : This property shall be set to 0
- vdda-phy-supply : phandle to main PHY supply for analog domain
- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
- clocks : List of phandle and clock specifier pairs
- clock-names : List of clock input name strings sorted in the same
order as the clocks property. "ref_clk_src", "ref_clk",
"tx_iface_clk" & "rx_iface_clk" are mandatory but
"ref_clk_parent" is optional
Optional properties:
- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
Example:
ufsphy1: ufsphy@0xfc597000 {
compatible = "qcom,ufs-phy-qmp-20nm";
reg = <0xfc597000 0x800>;
reg-names = "phy_mem";
#phy-cells = <0>;
vdda-phy-supply = <&pma8084_l4>;
vdda-pll-supply = <&pma8084_l12>;
vdda-phy-max-microamp = <50000>;
vdda-pll-max-microamp = <1000>;
clock-names = "ref_clk_src",
"ref_clk_parent",
"ref_clk",
"tx_iface_clk",
"rx_iface_clk";
clocks = <&clock_rpm clk_ln_bb_clk>,
<&clock_gcc clk_pcie_1_phy_ldo >,
<&clock_gcc clk_ufs_phy_ldo>,
<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
};
ufshc@0xfc598000 {
...
phys = <&ufsphy1>;
phy-names = "ufsphy";
};
...@@ -4,11 +4,18 @@ UFSHC nodes are defined to describe on-chip UFS host controllers. ...@@ -4,11 +4,18 @@ UFSHC nodes are defined to describe on-chip UFS host controllers.
Each UFS controller instance should have its own node. Each UFS controller instance should have its own node.
Required properties: Required properties:
- compatible : compatible list, contains "jedec,ufs-1.1" - compatible : must contain "jedec,ufs-1.1", may also list one or more
of the following:
"qcom,msm8994-ufshc"
"qcom,msm8996-ufshc"
"qcom,ufshc"
- interrupts : <interrupt mapping for UFS host controller IRQ> - interrupts : <interrupt mapping for UFS host controller IRQ>
- reg : <registers mapping> - reg : <registers mapping>
Optional properties: Optional properties:
- phys : phandle to UFS PHY node
- phy-names : the string "ufsphy" when is found in a node, along
with "phys" attribute, provides phandle to UFS PHY node
- vdd-hba-supply : phandle to UFS host controller supply regulator node - vdd-hba-supply : phandle to UFS host controller supply regulator node
- vcc-supply : phandle to VCC supply regulator node - vcc-supply : phandle to VCC supply regulator node
- vccq-supply : phandle to VCCQ supply regulator node - vccq-supply : phandle to VCCQ supply regulator node
...@@ -54,4 +61,6 @@ Example: ...@@ -54,4 +61,6 @@ Example:
clocks = <&core 0>, <&ref 0>, <&iface 0>; clocks = <&core 0>, <&ref 0>, <&iface 0>;
clock-names = "core_clk", "ref_clk", "iface_clk"; clock-names = "core_clk", "ref_clk", "iface_clk";
freq-table-hz = <100000000 200000000>, <0 0>, <0 0>; freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
phys = <&ufsphy1>;
phy-names = "ufsphy";
}; };
...@@ -1038,6 +1038,10 @@ kbuf_alloc_2_sgl(int bytes, u32 sgdir, int sge_offset, int *frags, ...@@ -1038,6 +1038,10 @@ kbuf_alloc_2_sgl(int bytes, u32 sgdir, int sge_offset, int *frags,
int i, buflist_ent; int i, buflist_ent;
int sg_spill = MAX_FRAGS_SPILL1; int sg_spill = MAX_FRAGS_SPILL1;
int dir; int dir;
if (bytes < 0)
return NULL;
/* initialization */ /* initialization */
*frags = 0; *frags = 0;
*blp = NULL; *blp = NULL;
......
...@@ -432,6 +432,7 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) ...@@ -432,6 +432,7 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy)
out: out:
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_ref_clk);
static static
int ufs_qcom_phy_disable_vreg(struct phy *phy, int ufs_qcom_phy_disable_vreg(struct phy *phy,
...@@ -474,6 +475,7 @@ void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy) ...@@ -474,6 +475,7 @@ void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy)
phy->is_ref_clk_enabled = false; phy->is_ref_clk_enabled = false;
} }
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk);
#define UFS_REF_CLK_EN (1 << 5) #define UFS_REF_CLK_EN (1 << 5)
...@@ -517,11 +519,13 @@ void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy) ...@@ -517,11 +519,13 @@ void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy)
{ {
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true); ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk);
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy) void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)
{ {
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false); ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk);
/* Turn ON M-PHY RMMI interface clocks */ /* Turn ON M-PHY RMMI interface clocks */
int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy) int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
...@@ -550,6 +554,7 @@ int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy) ...@@ -550,6 +554,7 @@ int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
out: out:
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_iface_clk);
/* Turn OFF M-PHY RMMI interface clocks */ /* Turn OFF M-PHY RMMI interface clocks */
void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy) void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
...@@ -562,6 +567,7 @@ void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy) ...@@ -562,6 +567,7 @@ void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
phy->is_iface_clk_enabled = false; phy->is_iface_clk_enabled = false;
} }
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_iface_clk);
int ufs_qcom_phy_start_serdes(struct phy *generic_phy) int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
{ {
...@@ -578,6 +584,7 @@ int ufs_qcom_phy_start_serdes(struct phy *generic_phy) ...@@ -578,6 +584,7 @@ int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes);
int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes) int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
{ {
...@@ -595,6 +602,7 @@ int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes) ...@@ -595,6 +602,7 @@ int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
u8 major, u16 minor, u16 step) u8 major, u16 minor, u16 step)
...@@ -605,6 +613,7 @@ void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, ...@@ -605,6 +613,7 @@ void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
ufs_qcom_phy->host_ctrl_rev_minor = minor; ufs_qcom_phy->host_ctrl_rev_minor = minor;
ufs_qcom_phy->host_ctrl_rev_step = step; ufs_qcom_phy->host_ctrl_rev_step = step;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
{ {
...@@ -625,6 +634,7 @@ int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) ...@@ -625,6 +634,7 @@ int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy);
int ufs_qcom_phy_remove(struct phy *generic_phy, int ufs_qcom_phy_remove(struct phy *generic_phy,
struct ufs_qcom_phy *ufs_qcom_phy) struct ufs_qcom_phy *ufs_qcom_phy)
...@@ -662,6 +672,7 @@ int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy) ...@@ -662,6 +672,7 @@ int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
return ufs_qcom_phy->phy_spec_ops-> return ufs_qcom_phy->phy_spec_ops->
is_physical_coding_sublayer_ready(ufs_qcom_phy); is_physical_coding_sublayer_ready(ufs_qcom_phy);
} }
EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready);
int ufs_qcom_phy_power_on(struct phy *generic_phy) int ufs_qcom_phy_power_on(struct phy *generic_phy)
{ {
......
...@@ -541,7 +541,6 @@ config SCSI_ARCMSR ...@@ -541,7 +541,6 @@ config SCSI_ARCMSR
source "drivers/scsi/esas2r/Kconfig" source "drivers/scsi/esas2r/Kconfig"
source "drivers/scsi/megaraid/Kconfig.megaraid" source "drivers/scsi/megaraid/Kconfig.megaraid"
source "drivers/scsi/mpt2sas/Kconfig"
source "drivers/scsi/mpt3sas/Kconfig" source "drivers/scsi/mpt3sas/Kconfig"
source "drivers/scsi/ufs/Kconfig" source "drivers/scsi/ufs/Kconfig"
......
...@@ -106,7 +106,6 @@ obj-$(CONFIG_CXLFLASH) += cxlflash/ ...@@ -106,7 +106,6 @@ obj-$(CONFIG_CXLFLASH) += cxlflash/
obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o
obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/ obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/
obj-$(CONFIG_MEGARAID_SAS) += megaraid/ obj-$(CONFIG_MEGARAID_SAS) += megaraid/
obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas/
obj-$(CONFIG_SCSI_MPT3SAS) += mpt3sas/ obj-$(CONFIG_SCSI_MPT3SAS) += mpt3sas/
obj-$(CONFIG_SCSI_UFSHCD) += ufs/ obj-$(CONFIG_SCSI_UFSHCD) += ufs/
obj-$(CONFIG_SCSI_ACARD) += atp870u.o obj-$(CONFIG_SCSI_ACARD) += atp870u.o
......
...@@ -703,10 +703,10 @@ static int asd_unregister_sas_ha(struct asd_ha_struct *asd_ha) ...@@ -703,10 +703,10 @@ static int asd_unregister_sas_ha(struct asd_ha_struct *asd_ha)
{ {
int err; int err;
scsi_remove_host(asd_ha->sas_ha.core.shost);
err = sas_unregister_ha(&asd_ha->sas_ha); err = sas_unregister_ha(&asd_ha->sas_ha);
sas_remove_host(asd_ha->sas_ha.core.shost); sas_remove_host(asd_ha->sas_ha.core.shost);
scsi_remove_host(asd_ha->sas_ha.core.shost);
scsi_host_put(asd_ha->sas_ha.core.shost); scsi_host_put(asd_ha->sas_ha.core.shost);
kfree(asd_ha->sas_ha.sas_phy); kfree(asd_ha->sas_ha.sas_phy);
......
...@@ -3186,7 +3186,7 @@ be_sgl_create_contiguous(void *virtual_address, ...@@ -3186,7 +3186,7 @@ be_sgl_create_contiguous(void *virtual_address,
{ {
WARN_ON(!virtual_address); WARN_ON(!virtual_address);
WARN_ON(!physical_address); WARN_ON(!physical_address);
WARN_ON(!length > 0); WARN_ON(!length);
WARN_ON(!sgl); WARN_ON(!sgl);
sgl->va = virtual_address; sgl->va = virtual_address;
......
This diff is collapsed.
...@@ -33,12 +33,38 @@ struct access_method { ...@@ -33,12 +33,38 @@ struct access_method {
unsigned long (*command_completed)(struct ctlr_info *h, u8 q); unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
}; };
/* for SAS hosts and SAS expanders */
struct hpsa_sas_node {
struct device *parent_dev;
struct list_head port_list_head;
};
struct hpsa_sas_port {
struct list_head port_list_entry;
u64 sas_address;
struct sas_port *port;
int next_phy_index;
struct list_head phy_list_head;
struct hpsa_sas_node *parent_node;
struct sas_rphy *rphy;
};
struct hpsa_sas_phy {
struct list_head phy_list_entry;
struct sas_phy *phy;
struct hpsa_sas_port *parent_port;
bool added_to_port;
};
struct hpsa_scsi_dev_t { struct hpsa_scsi_dev_t {
int devtype; unsigned int devtype;
int bus, target, lun; /* as presented to the OS */ int bus, target, lun; /* as presented to the OS */
unsigned char scsi3addr[8]; /* as presented to the HW */ unsigned char scsi3addr[8]; /* as presented to the HW */
u8 physical_device : 1;
u8 expose_device;
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
unsigned char device_id[16]; /* from inquiry pg. 0x83 */ unsigned char device_id[16]; /* from inquiry pg. 0x83 */
u64 sas_address;
unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
unsigned char model[16]; /* bytes 16-31 of inquiry data */ unsigned char model[16]; /* bytes 16-31 of inquiry data */
unsigned char raid_level; /* from inquiry page 0xC1 */ unsigned char raid_level; /* from inquiry page 0xC1 */
...@@ -75,11 +101,8 @@ struct hpsa_scsi_dev_t { ...@@ -75,11 +101,8 @@ struct hpsa_scsi_dev_t {
struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
int nphysical_disks; int nphysical_disks;
int supports_aborts; int supports_aborts;
#define HPSA_DO_NOT_EXPOSE 0x0 struct hpsa_sas_port *sas_port;
#define HPSA_SG_ATTACH 0x1 int external; /* 1-from external array 0-not <0-unknown */
#define HPSA_ULD_ATTACH 0x2
#define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH)
u8 expose_state;
}; };
struct reply_queue_buffer { struct reply_queue_buffer {
...@@ -136,6 +159,7 @@ struct ctlr_info { ...@@ -136,6 +159,7 @@ struct ctlr_info {
char *product_name; char *product_name;
struct pci_dev *pdev; struct pci_dev *pdev;
u32 board_id; u32 board_id;
u64 sas_address;
void __iomem *vaddr; void __iomem *vaddr;
unsigned long paddr; unsigned long paddr;
int nr_cmds; /* Number of commands allowed on this controller */ int nr_cmds; /* Number of commands allowed on this controller */
...@@ -262,7 +286,10 @@ struct ctlr_info { ...@@ -262,7 +286,10 @@ struct ctlr_info {
spinlock_t offline_device_lock; spinlock_t offline_device_lock;
struct list_head offline_device_list; struct list_head offline_device_list;
int acciopath_status; int acciopath_status;
int drv_req_rescan;
int raid_offload_debug; int raid_offload_debug;
int discovery_polling;
struct ReportLUNdata *lastlogicals;
int needs_abort_tags_swizzled; int needs_abort_tags_swizzled;
struct workqueue_struct *resubmit_wq; struct workqueue_struct *resubmit_wq;
struct workqueue_struct *rescan_ctlr_wq; struct workqueue_struct *rescan_ctlr_wq;
...@@ -270,6 +297,8 @@ struct ctlr_info { ...@@ -270,6 +297,8 @@ struct ctlr_info {
wait_queue_head_t abort_cmd_wait_queue; wait_queue_head_t abort_cmd_wait_queue;
wait_queue_head_t event_sync_wait_queue; wait_queue_head_t event_sync_wait_queue;
struct mutex reset_mutex; struct mutex reset_mutex;
u8 reset_in_progress;
struct hpsa_sas_node *sas_host;
}; };
struct offline_device_entry { struct offline_device_entry {
...@@ -283,6 +312,7 @@ struct offline_device_entry { ...@@ -283,6 +312,7 @@ struct offline_device_entry {
#define HPSA_RESET_TYPE_BUS 0x01 #define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03 #define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04 #define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
#define HPSA_MSG_SEND_RETRY_LIMIT 10 #define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
...@@ -367,6 +397,11 @@ struct offline_device_entry { ...@@ -367,6 +397,11 @@ struct offline_device_entry {
#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
#define HPSA_PHYSICAL_DEVICE_BUS 0
#define HPSA_RAID_VOLUME_BUS 1
#define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
#define HPSA_HBA_BUS 3
/* /*
Send the command to the hardware Send the command to the hardware
*/ */
......
...@@ -260,8 +260,6 @@ struct ext_report_lun_entry { ...@@ -260,8 +260,6 @@ struct ext_report_lun_entry {
u8 wwid[8]; u8 wwid[8];
u8 device_type; u8 device_type;
u8 device_flags; u8 device_flags;
#define NON_DISK_PHYS_DEV(x) ((x)[17] & 0x01)
#define PHYS_IOACCEL(x) ((x)[17] & 0x08)
u8 lun_count; /* multi-lun device, how many luns */ u8 lun_count; /* multi-lun device, how many luns */
u8 redundant_paths; u8 redundant_paths;
u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
...@@ -288,6 +286,11 @@ struct SenseSubsystem_info { ...@@ -288,6 +286,11 @@ struct SenseSubsystem_info {
#define BMIC_FLASH_FIRMWARE 0xF7 #define BMIC_FLASH_FIRMWARE 0xF7
#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
#define BMIC_IDENTIFY_CONTROLLER 0x11
#define BMIC_SET_DIAG_OPTIONS 0xF4
#define BMIC_SENSE_DIAG_OPTIONS 0xF5
#define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x40000000
#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
/* Command List Structure */ /* Command List Structure */
union SCSI3Addr { union SCSI3Addr {
...@@ -684,6 +687,16 @@ struct hpsa_pci_info { ...@@ -684,6 +687,16 @@ struct hpsa_pci_info {
u32 board_id; u32 board_id;
}; };
struct bmic_identify_controller {
u8 configured_logical_drive_count; /* offset 0 */
u8 pad1[153];
__le16 extended_logical_unit_count; /* offset 154 */
u8 pad2[136];
u8 controller_mode; /* offset 292 */
u8 pad3[32];
};
struct bmic_identify_physical_device { struct bmic_identify_physical_device {
u8 scsi_bus; /* SCSI Bus number on controller */ u8 scsi_bus; /* SCSI Bus number on controller */
u8 scsi_id; /* SCSI ID on this bus */ u8 scsi_id; /* SCSI ID on this bus */
...@@ -816,5 +829,18 @@ struct bmic_identify_physical_device { ...@@ -816,5 +829,18 @@ struct bmic_identify_physical_device {
u8 padding[112]; u8 padding[112];
}; };
struct bmic_sense_subsystem_info {
u8 primary_slot_number;
u8 reserved[3];
u8 chasis_serial_number[32];
u8 primary_world_wide_id[8];
u8 primary_array_serial_number[32]; /* NULL terminated */
u8 primary_cache_serial_number[32]; /* NULL terminated */
u8 reserved_2[8];
u8 secondary_array_serial_number[32];
u8 secondary_cache_serial_number[32];
u8 pad[332];
};
#pragma pack() #pragma pack()
#endif /* HPSA_CMD_H */ #endif /* HPSA_CMD_H */
...@@ -106,9 +106,9 @@ MODULE_LICENSE("GPL"); ...@@ -106,9 +106,9 @@ MODULE_LICENSE("GPL");
MODULE_VERSION(IBMVSCSI_VERSION); MODULE_VERSION(IBMVSCSI_VERSION);
module_param_named(max_id, max_id, int, S_IRUGO | S_IWUSR); module_param_named(max_id, max_id, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(max_id, "Largest ID value for each channel"); MODULE_PARM_DESC(max_id, "Largest ID value for each channel [Default=64]");
module_param_named(max_channel, max_channel, int, S_IRUGO | S_IWUSR); module_param_named(max_channel, max_channel, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(max_channel, "Largest channel value"); MODULE_PARM_DESC(max_channel, "Largest channel value [Default=3]");
module_param_named(init_timeout, init_timeout, int, S_IRUGO | S_IWUSR); module_param_named(init_timeout, init_timeout, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(init_timeout, "Initialization timeout in seconds"); MODULE_PARM_DESC(init_timeout, "Initialization timeout in seconds");
module_param_named(max_requests, max_requests, int, S_IRUGO); module_param_named(max_requests, max_requests, int, S_IRUGO);
...@@ -2289,11 +2289,15 @@ static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id) ...@@ -2289,11 +2289,15 @@ static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id)
goto init_pool_failed; goto init_pool_failed;
} }
host->max_lun = 8; host->max_lun = IBMVSCSI_MAX_LUN;
host->max_id = max_id; host->max_id = max_id;
host->max_channel = max_channel; host->max_channel = max_channel;
host->max_cmd_len = 16; host->max_cmd_len = 16;
dev_info(dev,
"Maximum ID: %d Maximum LUN: %llu Maximum Channel: %d\n",
host->max_id, host->max_lun, host->max_channel);
if (scsi_add_host(hostdata->host, hostdata->dev)) if (scsi_add_host(hostdata->host, hostdata->dev))
goto add_host_failed; goto add_host_failed;
......
...@@ -48,6 +48,7 @@ struct Scsi_Host; ...@@ -48,6 +48,7 @@ struct Scsi_Host;
#define IBMVSCSI_CMDS_PER_LUN_DEFAULT 16 #define IBMVSCSI_CMDS_PER_LUN_DEFAULT 16
#define IBMVSCSI_MAX_SECTORS_DEFAULT 256 /* 32 * 8 = default max I/O 32 pages */ #define IBMVSCSI_MAX_SECTORS_DEFAULT 256 /* 32 * 8 = default max I/O 32 pages */
#define IBMVSCSI_MAX_CMDS_PER_LUN 64 #define IBMVSCSI_MAX_CMDS_PER_LUN 64
#define IBMVSCSI_MAX_LUN 32
/* ------------------------------------------------------------ /* ------------------------------------------------------------
* Data Structures * Data Structures
......
...@@ -6363,15 +6363,19 @@ static int ipr_queuecommand(struct Scsi_Host *shost, ...@@ -6363,15 +6363,19 @@ static int ipr_queuecommand(struct Scsi_Host *shost,
ipr_cmd->scsi_cmd = scsi_cmd; ipr_cmd->scsi_cmd = scsi_cmd;
ipr_cmd->done = ipr_scsi_eh_done; ipr_cmd->done = ipr_scsi_eh_done;
if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) { if (ipr_is_gscsi(res)) {
if (scsi_cmd->underflow == 0) if (scsi_cmd->underflow == 0)
ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC; if (res->reset_occurred) {
if (ipr_is_gscsi(res) && res->reset_occurred) {
res->reset_occurred = 0; res->reset_occurred = 0;
ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST; ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
} }
}
if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR; ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
if (scsi_cmd->flags & SCMD_TAGGED) if (scsi_cmd->flags & SCMD_TAGGED)
ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_SIMPLE_TASK; ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_SIMPLE_TASK;
...@@ -7670,6 +7674,63 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd) ...@@ -7670,6 +7674,63 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
return IPR_RC_JOB_RETURN; return IPR_RC_JOB_RETURN;
} }
static int ipr_ioa_service_action_failed(struct ipr_cmnd *ipr_cmd)
{
u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT)
return IPR_RC_JOB_CONTINUE;
return ipr_reset_cmd_failed(ipr_cmd);
}
static void ipr_build_ioa_service_action(struct ipr_cmnd *ipr_cmd,
__be32 res_handle, u8 sa_code)
{
struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
ioarcb->res_handle = res_handle;
ioarcb->cmd_pkt.cdb[0] = IPR_IOA_SERVICE_ACTION;
ioarcb->cmd_pkt.cdb[1] = sa_code;
ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
}
/**
* ipr_ioafp_set_caching_parameters - Issue Set Cache parameters service
* action
*
* Return value:
* none
**/
static int ipr_ioafp_set_caching_parameters(struct ipr_cmnd *ipr_cmd)
{
struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
ENTER;
ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
if (pageC4->cache_cap[0] & IPR_CAP_SYNC_CACHE) {
ipr_build_ioa_service_action(ipr_cmd,
cpu_to_be32(IPR_IOA_RES_HANDLE),
IPR_IOA_SA_CHANGE_CACHE_PARAMS);
ioarcb->cmd_pkt.cdb[2] = 0x40;
ipr_cmd->job_step_failed = ipr_ioa_service_action_failed;
ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
IPR_SET_SUP_DEVICE_TIMEOUT);
LEAVE;
return IPR_RC_JOB_RETURN;
}
LEAVE;
return IPR_RC_JOB_CONTINUE;
}
/** /**
* ipr_ioafp_inquiry - Send an Inquiry to the adapter. * ipr_ioafp_inquiry - Send an Inquiry to the adapter.
* @ipr_cmd: ipr command struct * @ipr_cmd: ipr command struct
...@@ -7720,6 +7781,39 @@ static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page) ...@@ -7720,6 +7781,39 @@ static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
return 0; return 0;
} }
/**
* ipr_ioafp_pageC4_inquiry - Send a Page 0xC4 Inquiry to the adapter.
* @ipr_cmd: ipr command struct
*
* This function sends a Page 0xC4 inquiry to the adapter
* to retrieve software VPD information.
*
* Return value:
* IPR_RC_JOB_CONTINUE / IPR_RC_JOB_RETURN
**/
static int ipr_ioafp_pageC4_inquiry(struct ipr_cmnd *ipr_cmd)
{
struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
ENTER;
ipr_cmd->job_step = ipr_ioafp_set_caching_parameters;
memset(pageC4, 0, sizeof(*pageC4));
if (ipr_inquiry_page_supported(page0, 0xC4)) {
ipr_ioafp_inquiry(ipr_cmd, 1, 0xC4,
(ioa_cfg->vpd_cbs_dma
+ offsetof(struct ipr_misc_cbs,
pageC4_data)),
sizeof(struct ipr_inquiry_pageC4));
return IPR_RC_JOB_RETURN;
}
LEAVE;
return IPR_RC_JOB_CONTINUE;
}
/** /**
* ipr_ioafp_cap_inquiry - Send a Page 0xD0 Inquiry to the adapter. * ipr_ioafp_cap_inquiry - Send a Page 0xD0 Inquiry to the adapter.
* @ipr_cmd: ipr command struct * @ipr_cmd: ipr command struct
...@@ -7737,7 +7831,7 @@ static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd) ...@@ -7737,7 +7831,7 @@ static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap; struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
ENTER; ENTER;
ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg; ipr_cmd->job_step = ipr_ioafp_pageC4_inquiry;
memset(cap, 0, sizeof(*cap)); memset(cap, 0, sizeof(*cap));
if (ipr_inquiry_page_supported(page0, 0xD0)) { if (ipr_inquiry_page_supported(page0, 0xD0)) {
...@@ -8276,6 +8370,42 @@ static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd) ...@@ -8276,6 +8370,42 @@ static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
return IPR_RC_JOB_RETURN; return IPR_RC_JOB_RETURN;
} }
static int ipr_dump_mailbox_wait(struct ipr_cmnd *ipr_cmd)
{
struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
ENTER;
if (ioa_cfg->sdt_state != GET_DUMP)
return IPR_RC_JOB_RETURN;
if (!ioa_cfg->sis64 || !ipr_cmd->u.time_left ||
(readl(ioa_cfg->regs.sense_interrupt_reg) &
IPR_PCII_MAILBOX_STABLE)) {
if (!ipr_cmd->u.time_left)
dev_err(&ioa_cfg->pdev->dev,
"Timed out waiting for Mailbox register.\n");
ioa_cfg->sdt_state = READ_DUMP;
ioa_cfg->dump_timeout = 0;
if (ioa_cfg->sis64)
ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
else
ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
ipr_cmd->job_step = ipr_reset_wait_for_dump;
schedule_work(&ioa_cfg->work_q);
} else {
ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
ipr_reset_start_timer(ipr_cmd,
IPR_CHECK_FOR_RESET_TIMEOUT);
}
LEAVE;
return IPR_RC_JOB_RETURN;
}
/** /**
* ipr_reset_restore_cfg_space - Restore PCI config space. * ipr_reset_restore_cfg_space - Restore PCI config space.
* @ipr_cmd: ipr command struct * @ipr_cmd: ipr command struct
...@@ -8325,20 +8455,11 @@ static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd) ...@@ -8325,20 +8455,11 @@ static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
if (ioa_cfg->in_ioa_bringdown) { if (ioa_cfg->in_ioa_bringdown) {
ipr_cmd->job_step = ipr_ioa_bringdown_done; ipr_cmd->job_step = ipr_ioa_bringdown_done;
} else if (ioa_cfg->sdt_state == GET_DUMP) {
ipr_cmd->job_step = ipr_dump_mailbox_wait;
ipr_cmd->u.time_left = IPR_WAIT_FOR_MAILBOX;
} else { } else {
ipr_cmd->job_step = ipr_reset_enable_ioa; ipr_cmd->job_step = ipr_reset_enable_ioa;
if (GET_DUMP == ioa_cfg->sdt_state) {
ioa_cfg->sdt_state = READ_DUMP;
ioa_cfg->dump_timeout = 0;
if (ioa_cfg->sis64)
ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
else
ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
ipr_cmd->job_step = ipr_reset_wait_for_dump;
schedule_work(&ioa_cfg->work_q);
return IPR_RC_JOB_RETURN;
}
} }
LEAVE; LEAVE;
......
...@@ -39,8 +39,8 @@ ...@@ -39,8 +39,8 @@
/* /*
* Literals * Literals
*/ */
#define IPR_DRIVER_VERSION "2.6.2" #define IPR_DRIVER_VERSION "2.6.3"
#define IPR_DRIVER_DATE "(June 11, 2015)" #define IPR_DRIVER_DATE "(October 17, 2015)"
/* /*
* IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
...@@ -216,6 +216,10 @@ ...@@ -216,6 +216,10 @@
#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
#define IPR_IOA_SHUTDOWN 0xF7 #define IPR_IOA_SHUTDOWN 0xF7
#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
#define IPR_IOA_SERVICE_ACTION 0xD2
/* IOA Service Actions */
#define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14
/* /*
* Timeouts * Timeouts
...@@ -279,6 +283,9 @@ ...@@ -279,6 +283,9 @@
#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
#define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4)
#define IPR_WAIT_FOR_MAILBOX (2 * HZ)
#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
...@@ -846,6 +853,16 @@ struct ipr_inquiry_page0 { ...@@ -846,6 +853,16 @@ struct ipr_inquiry_page0 {
u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
}__attribute__((packed)); }__attribute__((packed));
struct ipr_inquiry_pageC4 {
u8 peri_qual_dev_type;
u8 page_code;
u8 reserved1;
u8 len;
u8 cache_cap[4];
#define IPR_CAP_SYNC_CACHE 0x08
u8 reserved2[20];
} __packed;
struct ipr_hostrcb_device_data_entry { struct ipr_hostrcb_device_data_entry {
struct ipr_vpd vpd; struct ipr_vpd vpd;
struct ipr_res_addr dev_res_addr; struct ipr_res_addr dev_res_addr;
...@@ -1319,6 +1336,7 @@ struct ipr_misc_cbs { ...@@ -1319,6 +1336,7 @@ struct ipr_misc_cbs {
struct ipr_inquiry_page0 page0_data; struct ipr_inquiry_page0 page0_data;
struct ipr_inquiry_page3 page3_data; struct ipr_inquiry_page3 page3_data;
struct ipr_inquiry_cap cap; struct ipr_inquiry_cap cap;
struct ipr_inquiry_pageC4 pageC4_data;
struct ipr_mode_pages mode_pages; struct ipr_mode_pages mode_pages;
struct ipr_supported_device supp_dev; struct ipr_supported_device supp_dev;
}; };
......
...@@ -271,11 +271,11 @@ static void isci_unregister(struct isci_host *isci_host) ...@@ -271,11 +271,11 @@ static void isci_unregister(struct isci_host *isci_host)
if (!isci_host) if (!isci_host)
return; return;
shost = to_shost(isci_host);
scsi_remove_host(shost);
sas_unregister_ha(&isci_host->sas_ha); sas_unregister_ha(&isci_host->sas_ha);
shost = to_shost(isci_host);
sas_remove_host(shost); sas_remove_host(shost);
scsi_remove_host(shost);
scsi_host_put(shost); scsi_host_put(shost);
} }
......
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
/* /*
* MegaRAID SAS Driver meta data * MegaRAID SAS Driver meta data
*/ */
#define MEGASAS_VERSION "06.807.10.00-rc1" #define MEGASAS_VERSION "06.808.16.00-rc1"
#define MEGASAS_RELDATE "March 6, 2015" #define MEGASAS_RELDATE "Oct. 8, 2015"
/* /*
* Device IDs * Device IDs
...@@ -52,6 +52,10 @@ ...@@ -52,6 +52,10 @@
#define PCI_DEVICE_ID_LSI_PLASMA 0x002f #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
#define PCI_DEVICE_ID_LSI_INVADER 0x005d #define PCI_DEVICE_ID_LSI_INVADER 0x005d
#define PCI_DEVICE_ID_LSI_FURY 0x005f #define PCI_DEVICE_ID_LSI_FURY 0x005f
#define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
#define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
#define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
#define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
/* /*
* Intel HBA SSDIDs * Intel HBA SSDIDs
...@@ -62,6 +66,14 @@ ...@@ -62,6 +66,14 @@
#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
#define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
/*
* Intruder HBA SSDIDs
*/
#define MEGARAID_INTRUDER_SSDID1 0x9371
#define MEGARAID_INTRUDER_SSDID2 0x9390
#define MEGARAID_INTRUDER_SSDID3 0x9370
/* /*
* Intel HBA branding * Intel HBA branding
...@@ -78,6 +90,8 @@ ...@@ -78,6 +90,8 @@
"Intel(R) RAID Controller RS3WC080" "Intel(R) RAID Controller RS3WC080"
#define MEGARAID_INTEL_RS3WC040_BRANDING \ #define MEGARAID_INTEL_RS3WC040_BRANDING \
"Intel(R) RAID Controller RS3WC040" "Intel(R) RAID Controller RS3WC040"
#define MEGARAID_INTEL_RMS3BC160_BRANDING \
"Intel(R) Integrated RAID Module RMS3BC160"
/* /*
* ===================================== * =====================================
...@@ -273,6 +287,16 @@ enum MFI_STAT { ...@@ -273,6 +287,16 @@ enum MFI_STAT {
MFI_STAT_INVALID_STATUS = 0xFF MFI_STAT_INVALID_STATUS = 0xFF
}; };
enum mfi_evt_class {
MFI_EVT_CLASS_DEBUG = -2,
MFI_EVT_CLASS_PROGRESS = -1,
MFI_EVT_CLASS_INFO = 0,
MFI_EVT_CLASS_WARNING = 1,
MFI_EVT_CLASS_CRITICAL = 2,
MFI_EVT_CLASS_FATAL = 3,
MFI_EVT_CLASS_DEAD = 4
};
/* /*
* Crash dump related defines * Crash dump related defines
*/ */
...@@ -364,6 +388,8 @@ enum MR_EVT_ARGS { ...@@ -364,6 +388,8 @@ enum MR_EVT_ARGS {
MR_EVT_ARGS_GENERIC, MR_EVT_ARGS_GENERIC,
}; };
#define SGE_BUFFER_SIZE 4096
/* /*
* define constants for device list query options * define constants for device list query options
*/ */
...@@ -394,6 +420,7 @@ enum MR_LD_QUERY_TYPE { ...@@ -394,6 +420,7 @@ enum MR_LD_QUERY_TYPE {
#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
#define MR_EVT_LD_OFFLINE 0x00fc #define MR_EVT_LD_OFFLINE 0x00fc
#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
#define MR_EVT_CTRL_PROP_CHANGED 0x012f
enum MR_PD_STATE { enum MR_PD_STATE {
MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
...@@ -973,7 +1000,12 @@ struct megasas_ctrl_info { ...@@ -973,7 +1000,12 @@ struct megasas_ctrl_info {
struct { struct {
#if defined(__BIG_ENDIAN_BITFIELD) #if defined(__BIG_ENDIAN_BITFIELD)
u32 reserved:12; u32 reserved:7;
u32 useSeqNumJbodFP:1;
u32 supportExtendedSSCSize:1;
u32 supportDiskCacheSettingForSysPDs:1;
u32 supportCPLDUpdate:1;
u32 supportTTYLogCompression:1;
u32 discardCacheDuringLDDelete:1; u32 discardCacheDuringLDDelete:1;
u32 supportSecurityonJBOD:1; u32 supportSecurityonJBOD:1;
u32 supportCacheBypassModes:1; u32 supportCacheBypassModes:1;
...@@ -1013,7 +1045,12 @@ struct megasas_ctrl_info { ...@@ -1013,7 +1045,12 @@ struct megasas_ctrl_info {
u32 supportCacheBypassModes:1; u32 supportCacheBypassModes:1;
u32 supportSecurityonJBOD:1; u32 supportSecurityonJBOD:1;
u32 discardCacheDuringLDDelete:1; u32 discardCacheDuringLDDelete:1;
u32 reserved:12; u32 supportTTYLogCompression:1;
u32 supportCPLDUpdate:1;
u32 supportDiskCacheSettingForSysPDs:1;
u32 supportExtendedSSCSize:1;
u32 useSeqNumJbodFP:1;
u32 reserved:7;
#endif #endif
} adapterOperations3; } adapterOperations3;
...@@ -1229,7 +1266,9 @@ union megasas_sgl_frame { ...@@ -1229,7 +1266,9 @@ union megasas_sgl_frame {
typedef union _MFI_CAPABILITIES { typedef union _MFI_CAPABILITIES {
struct { struct {
#if defined(__BIG_ENDIAN_BITFIELD) #if defined(__BIG_ENDIAN_BITFIELD)
u32 reserved:25; u32 reserved:23;
u32 support_ext_io_size:1;
u32 support_ext_queue_depth:1;
u32 security_protocol_cmds_fw:1; u32 security_protocol_cmds_fw:1;
u32 support_core_affinity:1; u32 support_core_affinity:1;
u32 support_ndrive_r1_lb:1; u32 support_ndrive_r1_lb:1;
...@@ -1245,7 +1284,9 @@ typedef union _MFI_CAPABILITIES { ...@@ -1245,7 +1284,9 @@ typedef union _MFI_CAPABILITIES {
u32 support_ndrive_r1_lb:1; u32 support_ndrive_r1_lb:1;
u32 support_core_affinity:1; u32 support_core_affinity:1;
u32 security_protocol_cmds_fw:1; u32 security_protocol_cmds_fw:1;
u32 reserved:25; u32 support_ext_queue_depth:1;
u32 support_ext_io_size:1;
u32 reserved:23;
#endif #endif
} mfi_capabilities; } mfi_capabilities;
__le32 reg; __le32 reg;
...@@ -1690,6 +1731,7 @@ struct megasas_instance { ...@@ -1690,6 +1731,7 @@ struct megasas_instance {
u32 crash_dump_drv_support; u32 crash_dump_drv_support;
u32 crash_dump_app_support; u32 crash_dump_app_support;
u32 secure_jbod_support; u32 secure_jbod_support;
bool use_seqnum_jbod_fp; /* Added for PD sequence */
spinlock_t crashdump_lock; spinlock_t crashdump_lock;
struct megasas_register_set __iomem *reg_set; struct megasas_register_set __iomem *reg_set;
...@@ -1748,6 +1790,7 @@ struct megasas_instance { ...@@ -1748,6 +1790,7 @@ struct megasas_instance {
u8 UnevenSpanSupport; u8 UnevenSpanSupport;
u8 supportmax256vd; u8 supportmax256vd;
u8 allow_fw_scan;
u16 fw_supported_vd_count; u16 fw_supported_vd_count;
u16 fw_supported_pd_count; u16 fw_supported_pd_count;
...@@ -1769,7 +1812,9 @@ struct megasas_instance { ...@@ -1769,7 +1812,9 @@ struct megasas_instance {
struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
u64 map_id; u64 map_id;
u64 pd_seq_map_id;
struct megasas_cmd *map_update_cmd; struct megasas_cmd *map_update_cmd;
struct megasas_cmd *jbod_seq_cmd;
unsigned long bar; unsigned long bar;
long reset_flags; long reset_flags;
struct mutex reset_mutex; struct mutex reset_mutex;
...@@ -1780,6 +1825,7 @@ struct megasas_instance { ...@@ -1780,6 +1825,7 @@ struct megasas_instance {
char mpio; char mpio;
u16 throttlequeuedepth; u16 throttlequeuedepth;
u8 mask_interrupts; u8 mask_interrupts;
u16 max_chain_frame_sz;
u8 is_imr; u8 is_imr;
bool dev_handle; bool dev_handle;
}; };
...@@ -1985,6 +2031,9 @@ __le16 get_updated_dev_handle(struct megasas_instance *instance, ...@@ -1985,6 +2031,9 @@ __le16 get_updated_dev_handle(struct megasas_instance *instance,
void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
struct LD_LOAD_BALANCE_INFO *lbInfo); struct LD_LOAD_BALANCE_INFO *lbInfo);
int megasas_get_ctrl_info(struct megasas_instance *instance); int megasas_get_ctrl_info(struct megasas_instance *instance);
/* PD sequence */
int
megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
int megasas_set_crash_dump_params(struct megasas_instance *instance, int megasas_set_crash_dump_params(struct megasas_instance *instance,
u8 crash_buf_state); u8 crash_buf_state);
void megasas_free_host_crash_buffer(struct megasas_instance *instance); void megasas_free_host_crash_buffer(struct megasas_instance *instance);
...@@ -2000,5 +2049,6 @@ void __megasas_return_cmd(struct megasas_instance *instance, ...@@ -2000,5 +2049,6 @@ void __megasas_return_cmd(struct megasas_instance *instance,
void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
int megasas_cmd_type(struct scsi_cmnd *cmd); int megasas_cmd_type(struct scsi_cmnd *cmd);
void megasas_setup_jbod_map(struct megasas_instance *instance);
#endif /*LSI_MEGARAID_SAS_H */ #endif /*LSI_MEGARAID_SAS_H */
This diff is collapsed.
...@@ -741,14 +741,12 @@ static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, ...@@ -741,14 +741,12 @@ static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
u8 physArm, span; u8 physArm, span;
u64 row; u64 row;
u8 retval = TRUE; u8 retval = TRUE;
u8 do_invader = 0;
u64 *pdBlock = &io_info->pdBlock; u64 *pdBlock = &io_info->pdBlock;
__le16 *pDevHandle = &io_info->devHandle; __le16 *pDevHandle = &io_info->devHandle;
u32 logArm, rowMod, armQ, arm; u32 logArm, rowMod, armQ, arm;
struct fusion_context *fusion;
if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER || fusion = instance->ctrl_context;
instance->pdev->device == PCI_DEVICE_ID_LSI_FURY))
do_invader = 1;
/*Get row and span from io_info for Uneven Span IO.*/ /*Get row and span from io_info for Uneven Span IO.*/
row = io_info->start_row; row = io_info->start_row;
...@@ -779,7 +777,8 @@ static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, ...@@ -779,7 +777,8 @@ static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
else { else {
*pDevHandle = cpu_to_le16(MR_PD_INVALID); *pDevHandle = cpu_to_le16(MR_PD_INVALID);
if ((raid->level >= 5) && if ((raid->level >= 5) &&
(!do_invader || (do_invader && ((fusion->adapter_type == THUNDERBOLT_SERIES) ||
((fusion->adapter_type == INVADER_SERIES) &&
(raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE;
else if (raid->level == 1) { else if (raid->level == 1) {
...@@ -823,13 +822,12 @@ u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow, ...@@ -823,13 +822,12 @@ u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow,
u8 physArm, span; u8 physArm, span;
u64 row; u64 row;
u8 retval = TRUE; u8 retval = TRUE;
u8 do_invader = 0;
u64 *pdBlock = &io_info->pdBlock; u64 *pdBlock = &io_info->pdBlock;
__le16 *pDevHandle = &io_info->devHandle; __le16 *pDevHandle = &io_info->devHandle;
struct fusion_context *fusion;
fusion = instance->ctrl_context;
if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER ||
instance->pdev->device == PCI_DEVICE_ID_LSI_FURY))
do_invader = 1;
row = mega_div64_32(stripRow, raid->rowDataSize); row = mega_div64_32(stripRow, raid->rowDataSize);
...@@ -875,7 +873,8 @@ u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow, ...@@ -875,7 +873,8 @@ u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow,
/* set dev handle as invalid. */ /* set dev handle as invalid. */
*pDevHandle = cpu_to_le16(MR_PD_INVALID); *pDevHandle = cpu_to_le16(MR_PD_INVALID);
if ((raid->level >= 5) && if ((raid->level >= 5) &&
(!do_invader || (do_invader && ((fusion->adapter_type == THUNDERBOLT_SERIES) ||
((fusion->adapter_type == INVADER_SERIES) &&
(raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE;
else if (raid->level == 1) { else if (raid->level == 1) {
...@@ -909,6 +908,7 @@ MR_BuildRaidContext(struct megasas_instance *instance, ...@@ -909,6 +908,7 @@ MR_BuildRaidContext(struct megasas_instance *instance,
struct RAID_CONTEXT *pRAID_Context, struct RAID_CONTEXT *pRAID_Context,
struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN) struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN)
{ {
struct fusion_context *fusion;
struct MR_LD_RAID *raid; struct MR_LD_RAID *raid;
u32 ld, stripSize, stripe_mask; u32 ld, stripSize, stripe_mask;
u64 endLba, endStrip, endRow, start_row, start_strip; u64 endLba, endStrip, endRow, start_row, start_strip;
...@@ -929,6 +929,7 @@ MR_BuildRaidContext(struct megasas_instance *instance, ...@@ -929,6 +929,7 @@ MR_BuildRaidContext(struct megasas_instance *instance,
isRead = io_info->isRead; isRead = io_info->isRead;
io_info->IoforUnevenSpan = 0; io_info->IoforUnevenSpan = 0;
io_info->start_span = SPAN_INVALID; io_info->start_span = SPAN_INVALID;
fusion = instance->ctrl_context;
ld = MR_TargetIdToLdGet(ldTgtId, map); ld = MR_TargetIdToLdGet(ldTgtId, map);
raid = MR_LdRaidGet(ld, map); raid = MR_LdRaidGet(ld, map);
...@@ -1092,8 +1093,7 @@ MR_BuildRaidContext(struct megasas_instance *instance, ...@@ -1092,8 +1093,7 @@ MR_BuildRaidContext(struct megasas_instance *instance,
cpu_to_le16(raid->fpIoTimeoutForLd ? cpu_to_le16(raid->fpIoTimeoutForLd ?
raid->fpIoTimeoutForLd : raid->fpIoTimeoutForLd :
map->raidMap.fpPdIoTimeoutSec); map->raidMap.fpPdIoTimeoutSec);
if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER) || if (fusion->adapter_type == INVADER_SERIES)
(instance->pdev->device == PCI_DEVICE_ID_LSI_FURY))
pRAID_Context->regLockFlags = (isRead) ? pRAID_Context->regLockFlags = (isRead) ?
raid->regTypeReqOnRead : raid->regTypeReqOnWrite; raid->regTypeReqOnRead : raid->regTypeReqOnWrite;
else else
...@@ -1198,10 +1198,6 @@ void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map, ...@@ -1198,10 +1198,6 @@ void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
span_row_width += span_row_width +=
MR_LdSpanPtrGet MR_LdSpanPtrGet
(ld, count, map)->spanRowDataSize; (ld, count, map)->spanRowDataSize;
printk(KERN_INFO "megasas:"
"span %x rowDataSize %x\n",
count, MR_LdSpanPtrGet
(ld, count, map)->spanRowDataSize);
} }
} }
......
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...@@ -35,8 +35,13 @@ ...@@ -35,8 +35,13 @@
#define _MEGARAID_SAS_FUSION_H_ #define _MEGARAID_SAS_FUSION_H_
/* Fusion defines */ /* Fusion defines */
#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
#define MEGASAS_MAX_CHAIN_SHIFT 5
#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
#define MEGASAS_256K_IO 128
#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
...@@ -89,6 +94,12 @@ enum MR_RAID_FLAGS_IO_SUB_TYPE { ...@@ -89,6 +94,12 @@ enum MR_RAID_FLAGS_IO_SUB_TYPE {
#define MEGASAS_FP_CMD_LEN 16 #define MEGASAS_FP_CMD_LEN 16
#define MEGASAS_FUSION_IN_RESET 0 #define MEGASAS_FUSION_IN_RESET 0
#define THRESHOLD_REPLY_COUNT 50 #define THRESHOLD_REPLY_COUNT 50
#define JBOD_MAPS_COUNT 2
enum MR_FUSION_ADAPTER_TYPE {
THUNDERBOLT_SERIES = 0,
INVADER_SERIES = 1,
};
/* /*
* Raid Context structure which describes MegaRAID specific IO Parameters * Raid Context structure which describes MegaRAID specific IO Parameters
...@@ -117,7 +128,9 @@ struct RAID_CONTEXT { ...@@ -117,7 +128,9 @@ struct RAID_CONTEXT {
u8 numSGE; u8 numSGE;
__le16 configSeqNum; __le16 configSeqNum;
u8 spanArm; u8 spanArm;
u8 resvd2[3]; u8 priority;
u8 numSGEExt;
u8 resvd2;
}; };
#define RAID_CTX_SPANARM_ARM_SHIFT (0) #define RAID_CTX_SPANARM_ARM_SHIFT (0)
...@@ -486,6 +499,7 @@ struct MPI2_IOC_INIT_REQUEST { ...@@ -486,6 +499,7 @@ struct MPI2_IOC_INIT_REQUEST {
#define MAX_PHYSICAL_DEVICES 256 #define MAX_PHYSICAL_DEVICES 256
#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
...@@ -789,6 +803,21 @@ struct MR_FW_RAID_MAP_EXT { ...@@ -789,6 +803,21 @@ struct MR_FW_RAID_MAP_EXT {
struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
}; };
/*
* * define MR_PD_CFG_SEQ structure for system PDs
* */
struct MR_PD_CFG_SEQ {
__le16 seqNum;
__le16 devHandle;
u8 reserved[4];
} __packed;
struct MR_PD_CFG_SEQ_NUM_SYNC {
__le32 size;
__le32 count;
struct MR_PD_CFG_SEQ seq[1];
} __packed;
struct fusion_context { struct fusion_context {
struct megasas_cmd_fusion **cmd_list; struct megasas_cmd_fusion **cmd_list;
dma_addr_t req_frames_desc_phys; dma_addr_t req_frames_desc_phys;
...@@ -828,9 +857,12 @@ struct fusion_context { ...@@ -828,9 +857,12 @@ struct fusion_context {
u32 current_map_sz; u32 current_map_sz;
u32 drv_map_sz; u32 drv_map_sz;
u32 drv_map_pages; u32 drv_map_pages;
struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
u8 fast_path_io; u8 fast_path_io;
struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
u8 adapter_type;
}; };
union desc_value { union desc_value {
......
#
# Kernel configuration file for the MPT2SAS
#
# This code is based on drivers/scsi/mpt2sas/Kconfig
# Copyright (C) 2007-2014 LSI Corporation
# (mailto:DL-MPTFusionLinux@lsi.com)
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; either version 2
# of the License, or (at your option) any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# NO WARRANTY
# THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
# LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
# solely responsible for determining the appropriateness of using and
# distributing the Program and assumes all risks associated with its
# exercise of rights under this Agreement, including but not limited to
# the risks and costs of program errors, damage to or loss of data,
# programs or equipment, and unavailability or interruption of operations.
# DISCLAIMER OF LIABILITY
# NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
# USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
# HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
# USA.
config SCSI_MPT2SAS
tristate "LSI MPT Fusion SAS 2.0 Device Driver"
depends on PCI && SCSI
select SCSI_SAS_ATTRS
select RAID_ATTRS
---help---
This driver supports PCI-Express SAS 6Gb/s Host Adapters.
config SCSI_MPT2SAS_MAX_SGE
int "LSI MPT Fusion Max number of SG Entries (16 - 128)"
depends on PCI && SCSI && SCSI_MPT2SAS
default "128"
range 16 128
---help---
This option allows you to specify the maximum number of scatter-
gather entries per I/O. The driver default is 128, which matches
SAFE_PHYS_SEGMENTS. However, it may decreased down to 16.
Decreasing this parameter will reduce memory requirements
on a per controller instance.
config SCSI_MPT2SAS_LOGGING
bool "LSI MPT Fusion logging facility"
depends on PCI && SCSI && SCSI_MPT2SAS
---help---
This turns on a logging facility.
# mpt2sas makefile
obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas.o
mpt2sas-y += mpt2sas_base.o \
mpt2sas_config.o \
mpt2sas_scsih.o \
mpt2sas_transport.o \
mpt2sas_ctl.o
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/*
* Copyright (c) 2000-2014 LSI Corporation.
*
*
* Name: mpi2_type.h
* Title: MPI basic type definitions
* Creation Date: August 16, 2006
*
* mpi2_type.h Version: 02.00.00
*
* Version History
* ---------------
*
* Date Version Description
* -------- -------- ------------------------------------------------------
* 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
* --------------------------------------------------------------------------
*/
#ifndef MPI2_TYPE_H
#define MPI2_TYPE_H
/*******************************************************************************
* Define MPI2_POINTER if it hasn't already been defined. By default
* MPI2_POINTER is defined to be a near pointer. MPI2_POINTER can be defined as
* a far pointer by defining MPI2_POINTER as "far *" before this header file is
* included.
*/
#ifndef MPI2_POINTER
#define MPI2_POINTER *
#endif
/* the basic types may have already been included by mpi_type.h */
#ifndef MPI_TYPE_H
/*****************************************************************************
*
* Basic Types
*
*****************************************************************************/
typedef u8 U8;
typedef __le16 U16;
typedef __le32 U32;
typedef __le64 U64 __attribute__((aligned(4)));
/*****************************************************************************
*
* Pointer Types
*
*****************************************************************************/
typedef U8 *PU8;
typedef U16 *PU16;
typedef U32 *PU32;
typedef U64 *PU64;
#endif
#endif
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...@@ -41,15 +41,15 @@ ...@@ -41,15 +41,15 @@
# USA. # USA.
config SCSI_MPT3SAS config SCSI_MPT3SAS
tristate "LSI MPT Fusion SAS 3.0 Device Driver" tristate "LSI MPT Fusion SAS 3.0 & SAS 2.0 Device Driver"
depends on PCI && SCSI depends on PCI && SCSI
select SCSI_SAS_ATTRS select SCSI_SAS_ATTRS
select RAID_ATTRS select RAID_ATTRS
---help--- ---help---
This driver supports PCI-Express SAS 12Gb/s Host Adapters. This driver supports PCI-Express SAS 12Gb/s Host Adapters.
config SCSI_MPT3SAS_MAX_SGE config SCSI_MPT2SAS_MAX_SGE
int "LSI MPT Fusion Max number of SG Entries (16 - 256)" int "LSI MPT Fusion SAS 2.0 Max number of SG Entries (16 - 256)"
depends on PCI && SCSI && SCSI_MPT3SAS depends on PCI && SCSI && SCSI_MPT3SAS
default "128" default "128"
range 16 256 range 16 256
...@@ -60,8 +60,14 @@ config SCSI_MPT3SAS_MAX_SGE ...@@ -60,8 +60,14 @@ config SCSI_MPT3SAS_MAX_SGE
can be 256. However, it may decreased down to 16. Decreasing this can be 256. However, it may decreased down to 16. Decreasing this
parameter will reduce memory requirements on a per controller instance. parameter will reduce memory requirements on a per controller instance.
config SCSI_MPT3SAS_LOGGING config SCSI_MPT3SAS_MAX_SGE
bool "LSI MPT Fusion logging facility" int "LSI MPT Fusion SAS 3.0 Max number of SG Entries (16 - 256)"
depends on PCI && SCSI && SCSI_MPT3SAS depends on PCI && SCSI && SCSI_MPT3SAS
default "128"
range 16 256
---help--- ---help---
This turns on a logging facility. This option allows you to specify the maximum number of scatter-
gather entries per I/O. The driver default is 128, which matches
MAX_PHYS_SEGMENTS in most kernels. However in SuSE kernels this
can be 256. However, it may decreased down to 16. Decreasing this
parameter will reduce memory requirements on a per controller instance.
...@@ -5,4 +5,5 @@ mpt3sas-y += mpt3sas_base.o \ ...@@ -5,4 +5,5 @@ mpt3sas-y += mpt3sas_base.o \
mpt3sas_scsih.o \ mpt3sas_scsih.o \
mpt3sas_transport.o \ mpt3sas_transport.o \
mpt3sas_ctl.o \ mpt3sas_ctl.o \
mpt3sas_trigger_diag.o mpt3sas_trigger_diag.o \
mpt3sas_warpdrive.o
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...@@ -50,10 +50,13 @@ ...@@ -50,10 +50,13 @@
#include <linux/miscdevice.h> #include <linux/miscdevice.h>
#endif #endif
#ifndef MPT2SAS_MINOR
#define MPT2SAS_MINOR (MPT_MINOR + 1)
#endif
#ifndef MPT3SAS_MINOR #ifndef MPT3SAS_MINOR
#define MPT3SAS_MINOR (MPT_MINOR + 2) #define MPT3SAS_MINOR (MPT_MINOR + 2)
#endif #endif
#define MPT2SAS_DEV_NAME "mpt2ctl"
#define MPT3SAS_DEV_NAME "mpt3ctl" #define MPT3SAS_DEV_NAME "mpt3ctl"
#define MPT3_MAGIC_NUMBER 'L' #define MPT3_MAGIC_NUMBER 'L'
#define MPT3_IOCTL_DEFAULT_TIMEOUT (10) /* in seconds */ #define MPT3_IOCTL_DEFAULT_TIMEOUT (10) /* in seconds */
...@@ -138,6 +141,7 @@ struct mpt3_ioctl_pci_info { ...@@ -138,6 +141,7 @@ struct mpt3_ioctl_pci_info {
#define MPT2_IOCTL_INTERFACE_FC_IP (0x02) #define MPT2_IOCTL_INTERFACE_FC_IP (0x02)
#define MPT2_IOCTL_INTERFACE_SAS (0x03) #define MPT2_IOCTL_INTERFACE_SAS (0x03)
#define MPT2_IOCTL_INTERFACE_SAS2 (0x04) #define MPT2_IOCTL_INTERFACE_SAS2 (0x04)
#define MPT2_IOCTL_INTERFACE_SAS2_SSS6200 (0x05)
#define MPT3_IOCTL_INTERFACE_SAS3 (0x06) #define MPT3_IOCTL_INTERFACE_SAS3 (0x06)
#define MPT2_IOCTL_VERSION_LENGTH (32) #define MPT2_IOCTL_VERSION_LENGTH (32)
......
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...@@ -640,9 +640,9 @@ static void mvs_pci_remove(struct pci_dev *pdev) ...@@ -640,9 +640,9 @@ static void mvs_pci_remove(struct pci_dev *pdev)
tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
#endif #endif
scsi_remove_host(mvi->shost);
sas_unregister_ha(sha); sas_unregister_ha(sha);
sas_remove_host(mvi->shost); sas_remove_host(mvi->shost);
scsi_remove_host(mvi->shost);
MVS_CHIP_DISP->interrupt_disable(mvi); MVS_CHIP_DISP->interrupt_disable(mvi);
free_irq(mvi->pdev->irq, sha); free_irq(mvi->pdev->irq, sha);
......
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...@@ -51,6 +51,8 @@ enum chip_flavors { ...@@ -51,6 +51,8 @@ enum chip_flavors {
chip_8076, chip_8076,
chip_8077, chip_8077,
chip_8006, chip_8006,
chip_8070,
chip_8072
}; };
enum phy_speed { enum phy_speed {
......
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