Commit fee8ca9f authored by Mark Rutland's avatar Mark Rutland Committed by Ingo Molnar

atomics/arm: Define atomic64_fetch_add_unless()

As a step towards unifying the atomic/atomic64/atomic_long APIs, this
patch converts the arch/arm implementation of atomic64_add_unless() into
an implementation of atomic64_fetch_add_unless().

A wrapper in <linux/atomic.h> will build atomic_add_unless() atop of
this, provided it is given a preprocessor definition.

No functional change is intended as a result of this patch.
Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/lkml/20180621121321.4761-12-mark.rutland@arm.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent ab0b9104
...@@ -486,11 +486,11 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v) ...@@ -486,11 +486,11 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v)
return result; return result;
} }
static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) static inline long long atomic64_fetch_add_unless(atomic64_t *v, long long a,
long long u)
{ {
long long val; long long oldval, newval;
unsigned long tmp; unsigned long tmp;
int ret = 1;
smp_mb(); smp_mb();
prefetchw(&v->counter); prefetchw(&v->counter);
...@@ -499,23 +499,23 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) ...@@ -499,23 +499,23 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
"1: ldrexd %0, %H0, [%4]\n" "1: ldrexd %0, %H0, [%4]\n"
" teq %0, %5\n" " teq %0, %5\n"
" teqeq %H0, %H5\n" " teqeq %H0, %H5\n"
" moveq %1, #0\n"
" beq 2f\n" " beq 2f\n"
" adds %Q0, %Q0, %Q6\n" " adds %Q1, %Q0, %Q6\n"
" adc %R0, %R0, %R6\n" " adc %R1, %R0, %R6\n"
" strexd %2, %0, %H0, [%4]\n" " strexd %2, %1, %H1, [%4]\n"
" teq %2, #0\n" " teq %2, #0\n"
" bne 1b\n" " bne 1b\n"
"2:" "2:"
: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter) : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
: "r" (&v->counter), "r" (u), "r" (a) : "r" (&v->counter), "r" (u), "r" (a)
: "cc"); : "cc");
if (ret) if (oldval != u)
smp_mb(); smp_mb();
return ret; return oldval;
} }
#define atomic64_fetch_add_unless atomic64_fetch_add_unless
#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
#define atomic64_inc(v) atomic64_add(1LL, (v)) #define atomic64_inc(v) atomic64_add(1LL, (v))
......
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