Commit ff3d4578 authored by Finn Thain's avatar Finn Thain Committed by Martin K. Petersen

ncr5380: Implement NCR5380_dma_xfer_len and remove LIMIT_TRANSFERSIZE macro

Follow the example of the atari_NCR5380.c core driver and adopt the
NCR5380_dma_xfer_len() hook. Implement NCR5380_dma_xfer_len() for dtc.c
and g_NCR5380.c to take care of the limitations of these cards. Keep the
default for drivers using PSEUDO_DMA.

Eliminate the unused macro LIMIT_TRANSFERSIZE.
Signed-off-by: default avatarFinn Thain <fthain@telegraphics.com.au>
Reviewed-by: default avatarHannes Reinecke <hare@suse.com>
Tested-by: default avatarOndrej Zary <linux@rainbow-software.org>
Tested-by: default avatarMichael Schmitz <schmitzmic@gmail.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 1d3db59d
...@@ -201,11 +201,6 @@ ...@@ -201,11 +201,6 @@
* DONT_USE_INTR - if defined, never use interrupts, even if we probe or * DONT_USE_INTR - if defined, never use interrupts, even if we probe or
* override-configure an IRQ. * override-configure an IRQ.
* *
* LIMIT_TRANSFERSIZE - if defined, limit the pseudo-dma transfers to 512
* bytes at a time. Since interrupts are disabled by default during
* these transfers, we might need this to give reasonable interrupt
* service time if the transfer size gets too large.
*
* LINKED - if defined, linked commands are supported. * LINKED - if defined, linked commands are supported.
* *
* PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases. * PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases.
...@@ -2000,29 +1995,12 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance) { ...@@ -2000,29 +1995,12 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance) {
*/ */
#if defined(PSEUDO_DMA) || defined(REAL_DMA_POLL) #if defined(PSEUDO_DMA) || defined(REAL_DMA_POLL)
/* KLL transfersize = 0;
* PSEUDO_DMA is defined here. If this is the g_NCR5380 if (!cmd->device->borken &&
* driver then it will always be defined, so the !(hostdata->flags & FLAG_NO_PSEUDO_DMA))
* FLAG_NO_PSEUDO_DMA is used to inhibit PDMA in the base transfersize = NCR5380_dma_xfer_len(instance, cmd, phase);
* NCR5380 case. I think this is a fairly clean solution.
* We supplement these 2 if's with the flag. if (transfersize) {
*/
#ifdef NCR5380_dma_xfer_len
if (!cmd->device->borken && !(hostdata->flags & FLAG_NO_PSEUDO_DMA) && (transfersize = NCR5380_dma_xfer_len(instance, cmd)) != 0) {
#else
transfersize = cmd->transfersize;
#ifdef LIMIT_TRANSFERSIZE /* If we have problems with interrupt service */
if (transfersize > 512)
transfersize = 512;
#endif /* LIMIT_TRANSFERSIZE */
if (!cmd->device->borken && transfersize && !(hostdata->flags & FLAG_NO_PSEUDO_DMA) && cmd->SCp.this_residual && !(cmd->SCp.this_residual % transfersize)) {
/* Limit transfers to 32K, for xx400 & xx406
* pseudoDMA that transfers in 128 bytes blocks. */
if (transfersize > 32 * 1024)
transfersize = 32 * 1024;
#endif
len = transfersize; len = transfersize;
if (NCR5380_transfer_dma(instance, &phase, &len, (unsigned char **) &cmd->SCp.ptr)) { if (NCR5380_transfer_dma(instance, &phase, &len, (unsigned char **) &cmd->SCp.ptr)) {
/* /*
......
...@@ -22,6 +22,9 @@ ...@@ -22,6 +22,9 @@
#define priv(host) ((struct NCR5380_hostdata *)(host)->hostdata) #define priv(host) ((struct NCR5380_hostdata *)(host)->hostdata)
#define NCR5380_read(reg) cumanascsi_read(instance, reg) #define NCR5380_read(reg) cumanascsi_read(instance, reg)
#define NCR5380_write(reg, value) cumanascsi_write(instance, reg, value) #define NCR5380_write(reg, value) cumanascsi_write(instance, reg, value)
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
#define NCR5380_intr cumanascsi_intr #define NCR5380_intr cumanascsi_intr
#define NCR5380_queue_command cumanascsi_queue_command #define NCR5380_queue_command cumanascsi_queue_command
#define NCR5380_info cumanascsi_info #define NCR5380_info cumanascsi_info
......
...@@ -26,6 +26,8 @@ ...@@ -26,6 +26,8 @@
#define NCR5380_write(reg, value) \ #define NCR5380_write(reg, value) \
writeb(value, priv(instance)->base + ((reg) << 2)) writeb(value, priv(instance)->base + ((reg) << 2))
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
#define NCR5380_queue_command oakscsi_queue_command #define NCR5380_queue_command oakscsi_queue_command
#define NCR5380_info oakscsi_info #define NCR5380_info oakscsi_info
#define NCR5380_show_info oakscsi_show_info #define NCR5380_show_info oakscsi_show_info
......
...@@ -2170,11 +2170,13 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance) ...@@ -2170,11 +2170,13 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance)
*/ */
#if defined(REAL_DMA) #if defined(REAL_DMA)
if (
#if !defined(CONFIG_SUN3) #if !defined(CONFIG_SUN3)
!cmd->device->borken && transfersize = 0;
if (!cmd->device->borken)
#endif #endif
(transfersize = NCR5380_dma_xfer_len(instance, cmd, phase)) >= DMA_MIN_SIZE) { transfersize = NCR5380_dma_xfer_len(instance, cmd, phase);
if (transfersize >= DMA_MIN_SIZE) {
len = transfersize; len = transfersize;
cmd->SCp.phase = phase; cmd->SCp.phase = phase;
if (NCR5380_transfer_dma(instance, &phase, if (NCR5380_transfer_dma(instance, &phase,
......
...@@ -419,6 +419,20 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src, ...@@ -419,6 +419,20 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
return (0); return (0);
} }
static int dtc_dma_xfer_len(struct scsi_cmnd *cmd)
{
int transfersize = cmd->transfersize;
/* Limit transfers to 32K, for xx400 & xx406
* pseudoDMA that transfers in 128 bytes blocks.
*/
if (transfersize > 32 * 1024 && cmd->SCp.this_residual &&
!(cmd->SCp.this_residual % transfersize))
transfersize = 32 * 1024;
return transfersize;
}
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
#include "NCR5380.c" #include "NCR5380.c"
......
...@@ -27,6 +27,9 @@ ...@@ -27,6 +27,9 @@
#define NCR5380_read(reg) (readb(DTC_address(reg))) #define NCR5380_read(reg) (readb(DTC_address(reg)))
#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
#define NCR5380_dma_xfer_len(instance, cmd, phase) \
dtc_dma_xfer_len(cmd)
#define NCR5380_intr dtc_intr #define NCR5380_intr dtc_intr
#define NCR5380_queue_command dtc_queue_command #define NCR5380_queue_command dtc_queue_command
#define NCR5380_abort dtc_abort #define NCR5380_abort dtc_abort
......
...@@ -699,6 +699,21 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src, ...@@ -699,6 +699,21 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
; // TIMEOUT ; // TIMEOUT
return 0; return 0;
} }
static int generic_NCR5380_dma_xfer_len(struct scsi_cmnd *cmd)
{
int transfersize = cmd->transfersize;
/* Limit transfers to 32K, for xx400 & xx406
* pseudoDMA that transfers in 128 bytes blocks.
*/
if (transfersize > 32 * 1024 && cmd->SCp.this_residual &&
!(cmd->SCp.this_residual % transfersize))
transfersize = 32 * 1024;
return transfersize;
}
#endif /* PSEUDO_DMA */ #endif /* PSEUDO_DMA */
/* /*
......
...@@ -73,6 +73,9 @@ ...@@ -73,6 +73,9 @@
#endif #endif
#define NCR5380_dma_xfer_len(instance, cmd, phase) \
generic_NCR5380_dma_xfer_len(cmd)
#define NCR5380_intr generic_NCR5380_intr #define NCR5380_intr generic_NCR5380_intr
#define NCR5380_queue_command generic_NCR5380_queue_command #define NCR5380_queue_command generic_NCR5380_queue_command
#define NCR5380_abort generic_NCR5380_abort #define NCR5380_abort generic_NCR5380_abort
......
...@@ -38,6 +38,7 @@ ...@@ -38,6 +38,7 @@
#define NCR5380_pread macscsi_pread #define NCR5380_pread macscsi_pread
#define NCR5380_pwrite macscsi_pwrite #define NCR5380_pwrite macscsi_pwrite
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
#define NCR5380_intr macscsi_intr #define NCR5380_intr macscsi_intr
#define NCR5380_queue_command macscsi_queue_command #define NCR5380_queue_command macscsi_queue_command
......
...@@ -110,6 +110,8 @@ ...@@ -110,6 +110,8 @@
#define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
#define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) ) #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
#define NCR5380_intr pas16_intr #define NCR5380_intr pas16_intr
#define NCR5380_queue_command pas16_queue_command #define NCR5380_queue_command pas16_queue_command
#define NCR5380_abort pas16_abort #define NCR5380_abort pas16_abort
......
...@@ -84,6 +84,8 @@ ...@@ -84,6 +84,8 @@
#define NCR5380_read(reg) readb(T128_address(reg)) #define NCR5380_read(reg) readb(T128_address(reg))
#define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) #define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
#define NCR5380_intr t128_intr #define NCR5380_intr t128_intr
#define NCR5380_queue_command t128_queue_command #define NCR5380_queue_command t128_queue_command
#define NCR5380_abort t128_abort #define NCR5380_abort t128_abort
......
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