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Commit ff61bc81 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "No core changes this time. Just new driver code and improvements!

  New drivers:

   - New driver for the Broadcom BCM4908 SoC.

   - New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative
     of the Samsung Exynos pin control driver.

   - New driver for the Amlogic Meson S4 SoC.

   - New driver for the Sunplus SP7021 SoC.

   - New driver for the Microsemi Ocelot family ServalT SoC.

   - New subdriver for Intel Alder Lake-M SoC.

   - New subdriver for Intel Ice Lake-N SoC, including PCH support.

   - New subdriver for Renesas R8A779F0 SoC.

   - New subdriver for Mediatek MT8186 SoC.

   - New subdriver for NXP Freescale i.MX93 SoC.

   - New driver for Nuvoton WPCM450 SoC.

   - New driver for Qualcomm SC8280XP SoC.

  Improvements:

   - Wakeup support on Samsung Exynos850 and ExynosAutov9.

   - Serious and voluminous maintenance cleanup and refactoring in the
     Renesas drivers. Mainly sharing similar data between the different
     SoC subdrivers.

   - Qualcomm SM8450 EGPIO support.

   - Drive strength support on the Mediatek MT8195.

   - Add some missing groups and functions to the Ralink RT2880"

* tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits)
  pinctrl: mediatek: common-v1: fix semicolon.cocci warnings
  pinctrl: nuvoton: wpcm450: Fix build error without OF
  pinctrl: qcom-pmic-gpio: Add support for pm8450
  dt-bindings: pinctrl: aspeed: Update gfx node in example
  dt-bindings: pinctrl: rt2880: add missing pin groups and functions
  pinctrl: ingenic: Fix regmap on X series SoCs
  pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register()
  pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register()
  pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS
  pinctrl: nuvoton: Fix sparse warning
  pinctrl: mediatek: mt8186: Account for probe refactoring
  pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback
  pinctrl: mediatek: common-v1: Commonize spec_pupd callback
  pinctrl: mediatek: common-v1: Use common probe function
  pinctrl: mediatek: common-v1: Add common probe function
  pinctrl: mediatek: paris: Unify probe function by using OF match data
  pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe
  pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe
  pinctrl: berlin: fix error return code of berlin_pinctrl_build_state()
  pinctrl: qcom: Introduce sc8280xp TLMM driver
  ...
parents 901c7280 4a6d0149
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Showing with 19104 additions and 3941 deletions
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View file @ ff61bc81
......@@ -75,6 +75,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
apb {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -84,6 +85,8 @@ examples:
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
......@@ -104,6 +107,12 @@ examples:
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
interrupts = <0x19>;
syscon = <&syscon>;
memory-region = <&gfx_memory>;
};
};
......@@ -130,3 +139,10 @@ examples:
};
};
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
View file @ ff61bc81
......@@ -85,7 +85,7 @@ Optional Properties (for I2C pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
pull-up resisitors (1.2k, 1.8k, 2.7k) available
pull-up resistors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins, so the valid values
are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
- bias-disable: No arguments. Disable pin bias.
......
Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml 0 → 100644
View file @ ff61bc81
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4908 pin controller
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
description:
Binding for pin controller present on BCM4908 family SoCs.
properties:
compatible:
const: brcm,bcm4908-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
led_25, led_26, led_27, led_28, led_29, led_30, led_31,
hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
usb1_pwr ]
groups:
minItems: 1
maxItems: 2
items:
enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
usb1_pwr_grp ]
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
pinctrl@ff800560 {
compatible = "brcm,bcm4908-pinctrl";
reg = <0xff800560 0x10>;
led_0-a-pins {
function = "led_0";
groups = "led_0_grp_a";
};
};
Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml 0 → 100644
View file @ ff61bc81
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX93 IOMUX Controller
maintainers:
- Peng Fan <peng.fan@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
allOf:
- $ref: "pinctrl.yaml#"
properties:
compatible:
const: fsl,imx93-iomuxc
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@443c0000 {
compatible = "fsl,imx93-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_uart3: uart3grp {
fsl,pins =
<0x48 0x1f8 0x41c 0x1 0x0 0x49>,
<0x4c 0x1fc 0x418 0x1 0x0 0x49>;
};
};
...
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
View file @ ff61bc81
......@@ -16,6 +16,7 @@ Required properties for the root node:
"amlogic,meson-g12a-periphs-pinctrl"
"amlogic,meson-g12a-aobus-pinctrl"
"amlogic,meson-a1-periphs-pinctrl"
"amlogic,meson-s4-periphs-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===
......
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
View file @ ff61bc81
......@@ -145,7 +145,7 @@ examples:
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio2_pins>;
pinctrl-names = "default";
reg = <0x1101059c 0x100>;
reg = <0x1101059c 0x118>;
microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
bus-frequency = <25000000>;
sgpio_in2: gpio@0 {
......
Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
View file @ ff61bc81
......@@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
Required properties:
- compatible : Should be "mscc,ocelot-pinctrl",
"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
"mscc,luton-pinctrl", "mscc,serval-pinctrl" or
"microchip,lan966x-pinctrl"
"mscc,luton-pinctrl", "mscc,serval-pinctrl",
"microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
- reg : Address and length of the register set for the device
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Must be 2.
......
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml 0 → 100644
View file @ ff61bc81
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton WPCM450 pin control and GPIO
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
properties:
compatible:
const: nuvoton,wpcm450-pinctrl
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
# There are three kinds of subnodes:
# 1. a GPIO controller node for each GPIO bank
# 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
# 3. a pinconf node configures properties of a single pin
"^gpio@[0-7]$":
type: object
description:
Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
GPIOs. Some GPIOs support interrupts.
properties:
reg:
minimum: 0
maximum: 7
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 3
description:
The interrupts associated with this GPIO bank
required:
- reg
- gpio-controller
- '#gpio-cells'
"^mux-":
$ref: pinmux-node.yaml#
properties:
groups:
description:
One or more groups of pins to mux to a certain function
items:
enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
function:
description:
The function that a group of pins is muxed to
enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
dependencies:
groups: [ function ]
function: [ groups ]
additionalProperties: false
"^cfg-":
$ref: pincfg-node.yaml#
properties:
pins:
description:
A list of pins to configure in certain ways, such as enabling
debouncing
items:
pattern: "^gpio1?[0-9]{1,2}$"
input-debounce: true
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
pinctrl: pinctrl@b8003000 {
compatible = "nuvoton,wpcm450-pinctrl";
reg = <0xb8003000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
gpio0: gpio@0 {
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<3 IRQ_TYPE_LEVEL_HIGH>,
<4 IRQ_TYPE_LEVEL_HIGH>;
};
mux-rmii2 {
groups = "rmii2";
function = "rmii2";
};
pinmux_uid: mux-uid {
groups = "gspi", "sspi";
function = "gpio";
};
pinctrl_uid: cfg-uid {
pins = "gpio14";
input-debounce = <1>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
uid {
label = "UID";
linux,code = <102>;
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml 0 → 100644
View file @ ff61bc81
This diff is collapsed.
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
View file @ ff61bc81
......@@ -98,7 +98,41 @@ patternProperties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8195 pull down PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8195 pull down RSEL type define value.
- enum: [75000, 5000]
description: mt8195 pull down RSEL type si unit value(ohm).
description: |
For pull down type is normal, it don't need add RSEL & R1R0 define
and resistance value.
......@@ -115,13 +149,6 @@ patternProperties:
& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
define in mt8195. It can also support resistance value(ohm)
"75000" & "5000" in mt8195.
oneOf:
- enum: [100, 101, 102, 103]
- description: mt8195 pull down PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
- description: mt8195 pull down RSEL type define value.
- enum: [75000, 5000]
- description: mt8195 pull down RSEL type si unit value(ohm).
An example of using RSEL define:
pincontroller {
......@@ -146,6 +173,14 @@ patternProperties:
};
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8195 pull up PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8195 pull up RSEL type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
description: mt8195 pull up RSEL type si unit value(ohm).
description: |
For pull up type is normal, it don't need add RSEL & R1R0 define
and resistance value.
......@@ -163,13 +198,6 @@ patternProperties:
define in mt8195. It can also support resistance value(ohm)
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
"75000" in mt8195.
oneOf:
- enum: [100, 101, 102, 103]
- description: mt8195 pull up PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
- description: mt8195 pull up RSEL type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
- description: mt8195 pull up RSEL type si unit value(ohm).
An example of using RSEL define:
pincontroller {
i2c0-pins {
......@@ -268,4 +296,13 @@ examples:
bias-pull-down;
};
};
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-disable;
mediatek,drive-strength-adv = <7>;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
View file @ ff61bc81
......@@ -34,6 +34,8 @@ properties:
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
......
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View file @ ff61bc81
......@@ -36,6 +36,7 @@ properties:
- qcom,pm8350-gpio
- qcom,pm8350b-gpio
- qcom,pm8350c-gpio
- qcom,pm8450-gpio
- qcom,pm8916-gpio
- qcom,pm8917-gpio
- qcom,pm8921-gpio
......
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
View file @ ff61bc81
......@@ -21,6 +21,7 @@ properties:
- qcom,pm8019-mpp
- qcom,pm8038-mpp
- qcom,pm8058-mpp
- qcom,pm8226-mpp
- qcom,pm8821-mpp
- qcom,pm8841-mpp
- qcom,pm8916-mpp
......
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml 0 → 100644
View file @ ff61bc81
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SC8280XP TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
SC8280XP platform.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sc8280xp-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
'$defs':
qcom-sc8280xp-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
vsense_trigger ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sc8280xp-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio4";
function = "qup14";
bias-pull-up;
};
tx {
pins = "gpio5";
function = "qup14";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
View file @ ff61bc81
......@@ -73,7 +73,6 @@ $defs:
properties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
......
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml
View file @ ff61bc81
......@@ -10,7 +10,7 @@ maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description:
The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
is not supported. There is no pinconf support.
properties:
......@@ -29,12 +29,13 @@ patternProperties:
properties:
groups:
description: Name of the pin group to use for the functions.
enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
pcie, sdhci]
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
uart1, uart2, uart3, wdt]
function:
description: The mux function to select
enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
mdio, nand1, nand2, sdhci]
enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
spi, uart1, uart2, uart3, wdt refclk, wdt rst]
required:
- groups
......
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View file @ ff61bc81
......@@ -44,6 +44,7 @@ properties:
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
......
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View file @ ff61bc81
......@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L combined Pin and GPIO controller
title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
......@@ -20,8 +20,15 @@ description:
properties:
compatible:
enum:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
oneOf:
- items:
- enum:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- items:
- enum:
- renesas,r9a07g054-pinctrl # RZ/V2L
- const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
reg:
maxItems: 1
......@@ -76,6 +83,7 @@ additionalProperties:
output-impedance-ohms:
enum: [ 33, 50, 66, 100 ]
power-source:
description: I/O voltage in millivolt.
enum: [ 1800, 2500, 3300 ]
slew-rate: true
gpio-hog: true
......
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View file @ ff61bc81
......@@ -56,6 +56,7 @@ properties:
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
- samsung,exynosautov9-pinctrl
- tesla,fsd-pinctrl
interrupts:
description:
......
MAINTAINERS
View file @ ff61bc81
......@@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki
F: Documentation/devicetree/bindings/*/*wpcm*
F: arch/arm/boot/dts/nuvoton-wpcm450*
F: arch/arm/mach-npcm/wpcm450.c
F: drivers/*/*/*wpcm*
F: drivers/*/*wpcm*
ARM/NXP S32G ARCHITECTURE
......@@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
F: drivers/net/ethernet/broadcom/bcm4908_enet.*
F: drivers/net/ethernet/broadcom/unimac.h
BROADCOM BCM4908 PINMUX DRIVER
M: Rafał Miłecki <rafal@milecki.pl>
M: bcm-kernel-feedback-list@broadcom.com
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
BROADCOM BCM5301X ARM ARCHITECTURE
M: Florian Fainelli <f.fainelli@gmail.com>
M: Hauke Mehrtens <hauke@hauke-m.de>
......@@ -15478,6 +15487,16 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
S: Supported
F: drivers/pinctrl/pinctrl-thunderbay.c
PIN CONTROLLER - SUNPLUS / TIBBO
M: Dvorkin Dmitry <dvorkin@tibbo.com>
M: Wells Lu <wellslutw@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: https://sunplus.atlassian.net/wiki/spaces/doc/overview
F: Documentation/devicetree/bindings/pinctrl/sunplus,*
F: drivers/pinctrl/sunplus/
F: include/dt-bindings/pinctrl/sppctl*.h
PKTCDVD DRIVER
M: linux-block@vger.kernel.org
S: Orphan
......
drivers/pinctrl/Kconfig
View file @ ff61bc81
......@@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunplus/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/tegra/Kconfig"
source "drivers/pinctrl/ti/Kconfig"
......
drivers/pinctrl/Makefile
View file @ ff61bc81
......@@ -62,7 +62,7 @@ obj-y += mediatek/
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-y += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
obj-y += nuvoton/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_RALINK) += ralink/
......@@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-y += sunplus/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
......
drivers/pinctrl/bcm/Kconfig
View file @ ff61bc81
......@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
help
Say Y here to enable the Broadcom BCM2835 GPIO driver.
config PINCTRL_BCM4908
tristate "Broadcom BCM4908 pinmux driver"
depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
default ARCH_BCM4908
help
Driver for BCM4908 family SoCs with integrated pin controller.
If compiled as module it will be called pinctrl-bcm4908.
config PINCTRL_BCM63XX
bool
select PINMUX
......
drivers/pinctrl/bcm/Makefile
View file @ ff61bc81
......@@ -3,6 +3,7 @@
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
......
drivers/pinctrl/bcm/pinctrl-bcm4908.c 0 → 100644
View file @ ff61bc81
This diff is collapsed.
drivers/pinctrl/berlin/berlin.c
View file @ ff61bc81
......@@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
pctrl->functions = krealloc(pctrl->functions,
pctrl->nfunctions * sizeof(*pctrl->functions),
GFP_KERNEL);
if (!pctrl->functions)
return -ENOMEM;
/* map functions to theirs groups */
for (i = 0; i < pctrl->desc->ngroups; i++) {
......
drivers/pinctrl/freescale/Kconfig
View file @ ff61bc81
......@@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050
help
Say Y here to enable the imxrt1050 pinctrl driver
config PINCTRL_IMX93
tristate "IMX93 pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx93 pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
......
drivers/pinctrl/freescale/Makefile
View file @ ff61bc81
......@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
......
drivers/pinctrl/freescale/pinctrl-imx.c
View file @ ff61bc81
......@@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
func->name = np->name;
func->num_group_names = of_get_child_count(np);
if (func->num_group_names == 0) {
dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
......
drivers/pinctrl/freescale/pinctrl-imx93.c 0 → 100644
View file @ ff61bc81
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx93_pads {
IMX93_IOMUXC_DAP_TDI = 0,
IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
IMX93_IOMUXC_GPIO_IO00 = 4,
IMX93_IOMUXC_GPIO_IO01 = 5,
IMX93_IOMUXC_GPIO_IO02 = 6,
IMX93_IOMUXC_GPIO_IO03 = 7,
IMX93_IOMUXC_GPIO_IO04 = 8,
IMX93_IOMUXC_GPIO_IO05 = 9,
IMX93_IOMUXC_GPIO_IO06 = 10,
IMX93_IOMUXC_GPIO_IO07 = 11,
IMX93_IOMUXC_GPIO_IO08 = 12,
IMX93_IOMUXC_GPIO_IO09 = 13,
IMX93_IOMUXC_GPIO_IO10 = 14,
IMX93_IOMUXC_GPIO_IO11 = 15,
IMX93_IOMUXC_GPIO_IO12 = 16,
IMX93_IOMUXC_GPIO_IO13 = 17,
IMX93_IOMUXC_GPIO_IO14 = 18,
IMX93_IOMUXC_GPIO_IO15 = 19,
IMX93_IOMUXC_GPIO_IO16 = 20,
IMX93_IOMUXC_GPIO_IO17 = 21,
IMX93_IOMUXC_GPIO_IO18 = 22,
IMX93_IOMUXC_GPIO_IO19 = 23,
IMX93_IOMUXC_GPIO_IO20 = 24,
IMX93_IOMUXC_GPIO_IO21 = 25,
IMX93_IOMUXC_GPIO_IO22 = 26,
IMX93_IOMUXC_GPIO_IO23 = 27,
IMX93_IOMUXC_GPIO_IO24 = 28,
IMX93_IOMUXC_GPIO_IO25 = 29,
IMX93_IOMUXC_GPIO_IO26 = 30,
IMX93_IOMUXC_GPIO_IO27 = 31,
IMX93_IOMUXC_GPIO_IO28 = 32,
IMX93_IOMUXC_GPIO_IO29 = 33,
IMX93_IOMUXC_CCM_CLKO1 = 34,
IMX93_IOMUXC_CCM_CLKO2 = 35,
IMX93_IOMUXC_CCM_CLKO3 = 36,
IMX93_IOMUXC_CCM_CLKO4 = 37,
IMX93_IOMUXC_ENET1_MDC = 38,
IMX93_IOMUXC_ENET1_MDIO = 39,
IMX93_IOMUXC_ENET1_TD3 = 40,
IMX93_IOMUXC_ENET1_TD2 = 41,
IMX93_IOMUXC_ENET1_TD1 = 42,
IMX93_IOMUXC_ENET1_TD0 = 43,
IMX93_IOMUXC_ENET1_TX_CTL = 44,
IMX93_IOMUXC_ENET1_TXC = 45,
IMX93_IOMUXC_ENET1_RX_CTL = 46,
IMX93_IOMUXC_ENET1_RXC = 47,
IMX93_IOMUXC_ENET1_RD0 = 48,
IMX93_IOMUXC_ENET1_RD1 = 49,
IMX93_IOMUXC_ENET1_RD2 = 50,
IMX93_IOMUXC_ENET1_RD3 = 51,
IMX93_IOMUXC_ENET2_MDC = 52,
IMX93_IOMUXC_ENET2_MDIO = 53,
IMX93_IOMUXC_ENET2_TD3 = 54,
IMX93_IOMUXC_ENET2_TD2 = 55,
IMX93_IOMUXC_ENET2_TD1 = 56,
IMX93_IOMUXC_ENET2_TD0 = 57,
IMX93_IOMUXC_ENET2_TX_CTL = 58,
IMX93_IOMUXC_ENET2_TXC = 59,
IMX93_IOMUXC_ENET2_RX_CTL = 60,
IMX93_IOMUXC_ENET2_RXC = 61,
IMX93_IOMUXC_ENET2_RD0 = 62,
IMX93_IOMUXC_ENET2_RD1 = 63,
IMX93_IOMUXC_ENET2_RD2 = 64,
IMX93_IOMUXC_ENET2_RD3 = 65,
IMX93_IOMUXC_SD1_CLK = 66,
IMX93_IOMUXC_SD1_CMD = 67,
IMX93_IOMUXC_SD1_DATA0 = 68,
IMX93_IOMUXC_SD1_DATA1 = 69,
IMX93_IOMUXC_SD1_DATA2 = 70,
IMX93_IOMUXC_SD1_DATA3 = 71,
IMX93_IOMUXC_SD1_DATA4 = 72,
IMX93_IOMUXC_SD1_DATA5 = 73,
IMX93_IOMUXC_SD1_DATA6 = 74,
IMX93_IOMUXC_SD1_DATA7 = 75,
IMX93_IOMUXC_SD1_STROBE = 76,
IMX93_IOMUXC_SD2_VSELECT = 77,
IMX93_IOMUXC_SD3_CLK = 78,
IMX93_IOMUXC_SD3_CMD = 79,
IMX93_IOMUXC_SD3_DATA0 = 80,
IMX93_IOMUXC_SD3_DATA1 = 81,
IMX93_IOMUXC_SD3_DATA2 = 82,
IMX93_IOMUXC_SD3_DATA3 = 83,
IMX93_IOMUXC_SD2_CD_B = 84,
IMX93_IOMUXC_SD2_CLK = 85,
IMX93_IOMUXC_SD2_CMD = 86,
IMX93_IOMUXC_SD2_DATA0 = 87,
IMX93_IOMUXC_SD2_DATA1 = 88,
IMX93_IOMUXC_SD2_DATA2 = 89,
IMX93_IOMUXC_SD2_DATA3 = 90,
IMX93_IOMUXC_SD2_RESET_B = 91,
IMX93_IOMUXC_I2C1_SCL = 92,
IMX93_IOMUXC_I2C1_SDA = 93,
IMX93_IOMUXC_I2C2_SCL = 94,
IMX93_IOMUXC_I2C2_SDA = 95,
IMX93_IOMUXC_UART1_RXD = 96,
IMX93_IOMUXC_UART1_TXD = 97,
IMX93_IOMUXC_UART2_RXD = 98,
IMX93_IOMUXC_UART2_TXD = 99,
IMX93_IOMUXC_PDM_CLK = 100,
IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
IMX93_IOMUXC_SAI1_TXFS = 103,
IMX93_IOMUXC_SAI1_TXC = 104,
IMX93_IOMUXC_SAI1_TXD0 = 105,
IMX93_IOMUXC_SAI1_RXD0 = 106,
IMX93_IOMUXC_WDOG_ANY = 107,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
};
static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
.pins = imx93_pinctrl_pads,
.npins = ARRAY_SIZE(imx93_pinctrl_pads),
.gpr_compatible = "fsl,imx93-iomuxc-gpr",
};
static const struct of_device_id imx93_pinctrl_of_match[] = {
{ .compatible = "fsl,imx93-iomuxc", },
{ /* sentinel */ }
};
static int imx93_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
}
static struct platform_driver imx93_pinctrl_driver = {
.driver = {
.name = "imx93-pinctrl",
.of_match_table = imx93_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx93_pinctrl_probe,
};
static int __init imx93_pinctrl_init(void)
{
return platform_driver_register(&imx93_pinctrl_driver);
}
arch_initcall(imx93_pinctrl_init);
MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
MODULE_LICENSE("GPL v2");
drivers/pinctrl/intel/pinctrl-alderlake.c
View file @ ff61bc81
This diff is collapsed.
drivers/pinctrl/intel/pinctrl-baytrail.c
View file @ ff61bc81
......@@ -32,6 +32,7 @@
#define BYT_VAL_REG 0x008
#define BYT_DFT_REG 0x00c
#define BYT_INT_STAT_REG 0x800
#define BYT_DIRECT_IRQ_REG 0x980
#define BYT_DEBOUNCE_REG 0x9d0
/* BYT_CONF0_REG register bits */
......@@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
chip->irq_eoi(data);
}
static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
{
int direct_irq, ioapic_direct_irq_base;
u8 *match, direct_irq_mux[16];
u32 trig;
memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
sizeof(direct_irq_mux));
match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
if (!match) {
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
return false;
}
direct_irq = match - direct_irq_mux;
/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
direct_irq, direct_irq + ioapic_direct_irq_base);
/*
* Testing has shown that the way direct IRQs work is that the combination of the
* direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
* trigger block, which normally sets the status flag in the IRQ status reg at
* 0x800, to one of the IO-APIC pins according to the mux registers.
*
* This means that:
* 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
* 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
* passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
* selecting edge mode operation then on the first edge the IO-APIC pin goes
* high, but since no write-to-clear write will be done to the IRQ status reg
* at 0x800, the detected edge condition will never get cleared.
*/
trig = conf0 & BYT_TRIG_MASK;
if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
pin, conf0);
return false;
}
return true;
}
static void byt_init_irq_valid_mask(struct gpio_chip *chip,
unsigned long *valid_mask,
unsigned int ngpios)
......@@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
value = readl(reg);
if (value & BYT_DIRECT_IRQ_EN) {
clear_bit(i, valid_mask);
dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
if (byt_direct_irq_sanity_check(vg, i, value)) {
clear_bit(i, valid_mask);
} else {
value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
}
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
byt_gpio_clear_triggering(vg, i);
dev_dbg(vg->dev, "disabling GPIO %d\n", i);
......
drivers/pinctrl/intel/pinctrl-icelake.c
View file @ ff61bc81
This diff is collapsed.
drivers/pinctrl/mediatek/Kconfig
View file @ ff61bc81
......@@ -147,6 +147,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8186
bool "Mediatek MT8186 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
......
drivers/pinctrl/mediatek/Makefile
View file @ ff61bc81
......@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
......
drivers/pinctrl/mediatek/pinctrl-moore.c
View file @ ff61bc81
......@@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw)
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
int err, i;
......@@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
hw->soc = soc;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names) {
dev_err(&pdev->dev,
if (!hw->soc->nbase_names)
return dev_err_probe(dev, -EINVAL,
"SoC should be assigned at least one register base\n");
return -EINVAL;
}
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
......@@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
/* Setup groups descriptions per SoC types */
err = mtk_build_groups(hw);
if (err) {
dev_err(&pdev->dev, "Failed to build groups\n");
return err;
}
if (err)
return dev_err_probe(dev, err, "Failed to build groups\n");
/* Setup functions descriptions per SoC types */
err = mtk_build_functions(hw);
if (err) {
dev_err(&pdev->dev, "Failed to build functions\n");
return err;
}
if (err)
return dev_err_probe(dev, err, "Failed to build functions\n");
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
* until all groups and functions are being added one.
......@@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw);
if (err) {
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
return err;
}
if (err)
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
platform_set_drvdata(pdev, hw);
......
drivers/pinctrl/mediatek/pinctrl-mt2701.c
View file @ ff61bc81
......@@ -270,13 +270,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
};
static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
......@@ -436,18 +429,6 @@ static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
};
static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
ARRAY_SIZE(mt2701_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
ARRAY_SIZE(mt2701_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
MTK_PINMUX_SPEC(22, 0xb10, 3),
MTK_PINMUX_SPEC(23, 0xb10, 4),
......@@ -508,8 +489,14 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
.pin_drv_grp = mt2701_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
.spec_pull_set = mt2701_spec_pull_set,
.spec_ies_smt_set = mt2701_ies_smt_set,
.spec_ies = mt2701_ies_set,
.n_spec_ies = ARRAY_SIZE(mt2701_ies_set),
.spec_pupd = mt2701_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd),
.spec_smt = mt2701_smt_set,
.n_spec_smt = ARRAY_SIZE(mt2701_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.spec_pinmux_set = mt2701_spec_pinmux_set,
.spec_dir_set = mt2701_spec_dir_set,
.dir_offset = 0x0000,
......@@ -534,20 +521,15 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
},
};
static int mt2701_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
}
static const struct of_device_id mt2701_pctrl_match[] = {
{ .compatible = "mediatek,mt2701-pinctrl", },
{ .compatible = "mediatek,mt7623-pinctrl", },
{ .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data },
{ .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt2701_pinctrl_probe,
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt2701-pinctrl",
.of_match_table = mt2701_pctrl_match,
......
drivers/pinctrl/mediatek/pinctrl-mt2712.c
View file @ ff61bc81
......@@ -81,16 +81,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
};
static int mt2712_spec_pull_set(struct regmap *regmap,
unsigned int pin,
unsigned char align,
bool isup,
unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
......@@ -285,19 +275,6 @@ static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
};
static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align,
int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
ARRAY_SIZE(mt2712_ies_set), pin, align, value);
if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
ARRAY_SIZE(mt2712_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
......@@ -563,8 +540,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
.pin_drv_grp = mt2712_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
.spec_pull_set = mt2712_spec_pull_set,
.spec_ies_smt_set = mt2712_ies_smt_set,
.spec_ies = mt2712_ies_set,
.n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
.spec_pupd = mt2712_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
.spec_smt = mt2712_smt_set,
.n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
......@@ -587,21 +570,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
},
};
static int mt2712_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
}
static const struct of_device_id mt2712_pctrl_match[] = {
{
.compatible = "mediatek,mt2712-pinctrl",
},
{ .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
{ }
};
MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt2712_pinctrl_probe,
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt2712-pinctrl",
.of_match_table = mt2712_pctrl_match,
......
drivers/pinctrl/mediatek/pinctrl-mt6765.c
View file @ ff61bc81
......@@ -1082,21 +1082,16 @@ static const struct mtk_pin_soc mt6765_data = {
};
static const struct of_device_id mt6765_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6765-pinctrl", },
{ .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data },
{ }
};
static int mt6765_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
}
static struct platform_driver mt6765_pinctrl_driver = {
.driver = {
.name = "mt6765-pinctrl",
.of_match_table = mt6765_pinctrl_of_match,
},
.probe = mt6765_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt6765_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt6779.c
View file @ ff61bc81
......@@ -758,21 +758,16 @@ static const struct mtk_pin_soc mt6779_data = {
};
static const struct of_device_id mt6779_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6779-pinctrl", },
{ .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data },
{ }
};
static int mt6779_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt6779_data);
}
static struct platform_driver mt6779_pinctrl_driver = {
.driver = {
.name = "mt6779-pinctrl",
.of_match_table = mt6779_pinctrl_of_match,
},
.probe = mt6779_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt6779_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt6797.c
View file @ ff61bc81
......@@ -58,21 +58,16 @@ static const struct mtk_pin_soc mt6797_data = {
};
static const struct of_device_id mt6797_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6797-pinctrl", },
{ .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data },
{ }
};
static int mt6797_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
}
static struct platform_driver mt6797_pinctrl_driver = {
.driver = {
.name = "mt6797-pinctrl",
.of_match_table = mt6797_pinctrl_of_match,
},
.probe = mt6797_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt6797_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt8127.c
View file @ ff61bc81
......@@ -172,13 +172,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
};
static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
......@@ -259,19 +252,6 @@ static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
};
static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
ARRAY_SIZE(mt8127_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
ARRAY_SIZE(mt8127_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
.pins = mtk_pins_mt8127,
.npins = ARRAY_SIZE(mtk_pins_mt8127),
......@@ -279,8 +259,14 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
.pin_drv_grp = mt8127_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
.spec_pull_set = mt8127_spec_pull_set,
.spec_ies_smt_set = mt8127_ies_smt_set,
.spec_ies = mt8127_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
.spec_pupd = mt8127_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
.spec_smt = mt8127_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
......@@ -303,18 +289,13 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
},
};
static int mt8127_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
}
static const struct of_device_id mt8127_pctrl_match[] = {
{ .compatible = "mediatek,mt8127-pinctrl", },
{ .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
{ }
};
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8127_pinctrl_probe,
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8127-pinctrl",
.of_match_table = mt8127_pctrl_match,
......
drivers/pinctrl/mediatek/pinctrl-mt8135.c
View file @ ff61bc81
......@@ -230,12 +230,14 @@ static const struct mtk_spec_pull_set spec_pupd[] = {
SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
};
static int spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
static int spec_pull_set(struct regmap *regmap,
const struct mtk_pinctrl_devdata *devdata,
unsigned int pin, bool isup, unsigned int r1r0)
{
unsigned int i;
unsigned int reg_pupd, reg_set_r0, reg_set_r1;
unsigned int reg_rst_r0, reg_rst_r1;
unsigned char align = devdata->port_align;
bool find = false;
for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
......@@ -316,20 +318,13 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
},
};
static int mt8135_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
}
static const struct of_device_id mt8135_pctrl_match[] = {
{
.compatible = "mediatek,mt8135-pinctrl",
},
{ .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
{ }
};
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8135_pinctrl_probe,
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8135-pinctrl",
.of_match_table = mt8135_pctrl_match,
......
drivers/pinctrl/mediatek/pinctrl-mt8167.c
View file @ ff61bc81
......@@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
};
static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
......@@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
};
static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
ARRAY_SIZE(mt8167_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
ARRAY_SIZE(mt8167_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
.pins = mtk_pins_mt8167,
.npins = ARRAY_SIZE(mtk_pins_mt8167),
......@@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
.pin_drv_grp = mt8167_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
.spec_pull_set = mt8167_spec_pull_set,
.spec_ies_smt_set = mt8167_ies_smt_set,
.spec_ies = mt8167_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
.spec_pupd = mt8167_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
.spec_smt = mt8167_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0500,
.pullsel_offset = 0x0600,
......@@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
},
};
static int mt8167_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
}
static const struct of_device_id mt8167_pctrl_match[] = {
{
.compatible = "mediatek,mt8167-pinctrl",
},
{ .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8167_pinctrl_probe,
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8167-pinctrl",
.of_match_table = mt8167_pctrl_match,
......
drivers/pinctrl/mediatek/pinctrl-mt8173.c
View file @ ff61bc81
......@@ -61,13 +61,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
};
static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
......@@ -174,18 +167,6 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
};
static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
ARRAY_SIZE(mt8173_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
ARRAY_SIZE(mt8173_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
......@@ -319,8 +300,14 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
.pin_drv_grp = mt8173_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
.spec_pull_set = mt8173_spec_pull_set,
.spec_ies_smt_set = mt8173_ies_smt_set,
.spec_ies = mt8173_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
.spec_pupd = mt8173_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
.spec_smt = mt8173_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
......
drivers/pinctrl/mediatek/pinctrl-mt8183.c
View file @ ff61bc81
......@@ -567,22 +567,17 @@ static const struct mtk_pin_soc mt8183_data = {
};
static const struct of_device_id mt8183_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8183-pinctrl", },
{ .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data },
{ }
};
static int mt8183_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
}
static struct platform_driver mt8183_pinctrl_driver = {
.driver = {
.name = "mt8183-pinctrl",
.of_match_table = mt8183_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mt8183_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8183_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt8186.c 0 → 100644
View file @ ff61bc81
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drivers/pinctrl/mediatek/pinctrl-mt8192.c
View file @ ff61bc81
......@@ -1381,22 +1381,17 @@ static const struct mtk_pin_soc mt8192_data = {
};
static const struct of_device_id mt8192_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8192-pinctrl", },
{ .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data },
{ }
};
static int mt8192_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt8192_data);
}
static struct platform_driver mt8192_pinctrl_driver = {
.driver = {
.name = "mt8192-pinctrl",
.of_match_table = mt8192_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mt8192_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8192_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt8195.c
View file @ ff61bc81
......@@ -959,22 +959,17 @@ static const struct mtk_pin_soc mt8195_data = {
};
static const struct of_device_id mt8195_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8195-pinctrl", },
{ .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data },
{ }
};
static int mt8195_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt8195_data);
}
static struct platform_driver mt8195_pinctrl_driver = {
.driver = {
.name = "mt8195-pinctrl",
.of_match_table = mt8195_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mt8195_pinctrl_probe,
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8195_pinctrl_init(void)
......
drivers/pinctrl/mediatek/pinctrl-mt8365.c
View file @ ff61bc81
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drivers/pinctrl/mediatek/pinctrl-mt8516.c
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drivers/pinctrl/mediatek/pinctrl-paris.c
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drivers/pinctrl/mediatek/pinctrl-paris.h
View file @ ff61bc81
......@@ -57,8 +57,7 @@
id##_funcs, \
}
int mtk_paris_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc);
int mtk_paris_pinctrl_probe(struct platform_device *pdev);
ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
unsigned int gpio, char *buf, unsigned int bufLen);
......
drivers/pinctrl/meson/Kconfig
View file @ ff61bc81
......@@ -61,4 +61,10 @@ config PINCTRL_MESON_A1
select PINCTRL_MESON_AXG_PMX
default y
config PINCTRL_MESON_S4
tristate "Meson s4 Soc pinctrl driver"
depends on ARM64
select PINCTRL_MESON_AXG_PMX
default y
endif
drivers/pinctrl/meson/Makefile
View file @ ff61bc81
......@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o
drivers/pinctrl/meson/pinctrl-meson-g12a.c
View file @ ff61bc81
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drivers/pinctrl/nomadik/pinctrl-nomadik.c
View file @ ff61bc81
......@@ -1883,8 +1883,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
}
prcm_np = of_parse_phandle(np, "prcm", 0);
if (prcm_np)
if (prcm_np) {
npct->prcm_base = of_iomap(prcm_np, 0);
of_node_put(prcm_np);
}
if (!npct->prcm_base) {
if (version == PINCTRL_NMK_STN8815) {
dev_info(&pdev->dev,
......
drivers/pinctrl/nuvoton/Kconfig
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drivers/pinctrl/sunplus/Makefile 0 → 100644
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drivers/pinctrl/sunplus/sppctl.c 0 → 100644
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drivers/pinctrl/sunplus/sppctl.h 0 → 100644
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drivers/pinctrl/sunplus/sppctl_sp7021.c 0 → 100644
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drivers/pinctrl/sunxi/pinctrl-sunxi.c
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include/dt-bindings/gpio/meson-s4-gpio.h 0 → 100644
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include/dt-bindings/pinctrl/mt8186-pinfunc.h 0 → 100644
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include/dt-bindings/pinctrl/sppctl-sp7021.h 0 → 100644
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include/dt-bindings/pinctrl/sppctl.h 0 → 100644
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