Commit ff945afb authored by Linus Torvalds's avatar Linus Torvalds

Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6:
  Staging: comedi: fix build on arches that don't want comedi drivers
  Staging: comedi: pcmcia irq fixes
  Staging: comedi: ni_pcimio: Added device id for pxi-6225.
  Staging: comedi: ni_65xx.c: fix output inversion problem.
  Staging: comedi: ni_65xx.c: fix insn_bits shift calculation.
  Staging: comedi: s526: fixes for pulse generator
  Staging: comedi: s526: Take account of arch's byte order.
  Staging: comedi: s526: Get rid of global variable 'cmReg'.
  Staging: comedi: s526: Fix number of channels on DIO subdevice
  Staging: comedi: cb_pcidio: fix "section mismatch" error
  Staging: comedi: jr3_pci: Initialize transf variable fully in jr3_pci_poll_subdevice().
  Staging: comedi: Corrected type of a printk argument in resize_async_buffer().
  Staging: p9auth: a few fixes
  Staging: rtl8192e: Add #include <linux/vmalloc.h>
  Staging: iio: Don't build on s390
  Staging: winbond: implement prepare_multicast and fix API usage
  Staging: w35und: Fix ->beacon_int breakage
  Staging: remove cowloop driver
  Staging: remove agnx driver
  Staging: comedi: serial2002: fix include build issue
parents 4c274fff cad9e3c7
...@@ -59,8 +59,6 @@ source "drivers/staging/echo/Kconfig" ...@@ -59,8 +59,6 @@ source "drivers/staging/echo/Kconfig"
source "drivers/staging/poch/Kconfig" source "drivers/staging/poch/Kconfig"
source "drivers/staging/agnx/Kconfig"
source "drivers/staging/otus/Kconfig" source "drivers/staging/otus/Kconfig"
source "drivers/staging/rt2860/Kconfig" source "drivers/staging/rt2860/Kconfig"
...@@ -129,7 +127,5 @@ source "drivers/staging/sep/Kconfig" ...@@ -129,7 +127,5 @@ source "drivers/staging/sep/Kconfig"
source "drivers/staging/iio/Kconfig" source "drivers/staging/iio/Kconfig"
source "drivers/staging/cowloop/Kconfig"
endif # !STAGING_EXCLUDE_BUILD endif # !STAGING_EXCLUDE_BUILD
endif # STAGING endif # STAGING
...@@ -12,7 +12,6 @@ obj-$(CONFIG_W35UND) += winbond/ ...@@ -12,7 +12,6 @@ obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/ obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/ obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_POCH) += poch/ obj-$(CONFIG_POCH) += poch/
obj-$(CONFIG_AGNX) += agnx/
obj-$(CONFIG_OTUS) += otus/ obj-$(CONFIG_OTUS) += otus/
obj-$(CONFIG_RT2860) += rt2860/ obj-$(CONFIG_RT2860) += rt2860/
obj-$(CONFIG_RT2870) += rt2870/ obj-$(CONFIG_RT2870) += rt2870/
...@@ -46,4 +45,3 @@ obj-$(CONFIG_VME_BUS) += vme/ ...@@ -46,4 +45,3 @@ obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_RAR_REGISTER) += rar/ obj-$(CONFIG_RAR_REGISTER) += rar/
obj-$(CONFIG_DX_SEP) += sep/ obj-$(CONFIG_DX_SEP) += sep/
obj-$(CONFIG_IIO) += iio/ obj-$(CONFIG_IIO) += iio/
obj-$(CONFIG_COWLOOP) += cowloop/
config AGNX
tristate "Wireless Airgo AGNX support"
depends on WLAN_80211 && MAC80211
---help---
This is an experimental driver for Airgo AGNX00 wireless chip.
obj-$(CONFIG_AGNX) += agnx.o
agnx-objs := rf.o \
pci.o \
xmit.o \
table.o \
sta.o \
phy.o
2008 7/18
The RX has can't receive OFDM packet correctly,
Guess it need be do RX calibrate.
before 2008 3/1
1: The RX get too much "CRC failed" pakets, it make the card work very unstable,
2: After running a while, the card will get infinity "RX Frame" and "Error"
interrupt, not know the root reason so far, try to fix it
3: Using two tx queue txd and txm but not only txm.
4: Set the hdr correctly.
5: Try to do recalibrate correvtly
6: To support G mode in future
7: Fix the mac address can't be readed and set correctly in BE machine.
8: Fix include and exclude FCS in promisous mode and manage mode
9: Using sta_notify to notice sta change
10: Turn on frame reception at the end of start
11: Guess the card support HW_MULTICAST_FILTER
12: The tx process should be implment atomic?
13: Using mac80211 function to control the TX&RX LED.
#ifndef AGNX_H_
#define AGNX_H_
#include <linux/io.h>
#include "xmit.h"
#define PFX KBUILD_MODNAME ": "
static inline u32 agnx_read32(void __iomem *mem_region, u32 offset)
{
return ioread32(mem_region + offset);
}
static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val)
{
iowrite32(val, mem_region + offset);
}
/* static const struct ieee80211_rate agnx_rates_80211b[] = { */
/* { .rate = 10, */
/* .val = 0xa, */
/* .flags = IEEE80211_RATE_CCK }, */
/* { .rate = 20, */
/* .val = 0x14, */
/* .hw_value = -0x14, */
/* .flags = IEEE80211_RATE_CCK_2 }, */
/* { .rate = 55, */
/* .val = 0x37, */
/* .val2 = -0x37, */
/* .flags = IEEE80211_RATE_CCK_2 }, */
/* { .rate = 110, */
/* .val = 0x6e, */
/* .val2 = -0x6e, */
/* .flags = IEEE80211_RATE_CCK_2 } */
/* }; */
static const struct ieee80211_rate agnx_rates_80211g[] = {
/* { .bitrate = 10, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
{ .bitrate = 10, .hw_value = 1, },
{ .bitrate = 20, .hw_value = 2, },
{ .bitrate = 55, .hw_value = 3, },
{ .bitrate = 110, .hw_value = 4,},
{ .bitrate = 60, .hw_value = 0xB, },
{ .bitrate = 90, .hw_value = 0xF, },
{ .bitrate = 120, .hw_value = 0xA },
{ .bitrate = 180, .hw_value = 0xE, },
/* { .bitrate = 240, .hw_value = 0xd, }, */
{ .bitrate = 360, .hw_value = 0xD, },
{ .bitrate = 480, .hw_value = 0x8, },
{ .bitrate = 540, .hw_value = 0xC, },
};
static const struct ieee80211_channel agnx_channels[] = {
{ .center_freq = 2412, .hw_value = 1, },
{ .center_freq = 2417, .hw_value = 2, },
{ .center_freq = 2422, .hw_value = 3, },
{ .center_freq = 2427, .hw_value = 4, },
{ .center_freq = 2432, .hw_value = 5, },
{ .center_freq = 2437, .hw_value = 6, },
{ .center_freq = 2442, .hw_value = 7, },
{ .center_freq = 2447, .hw_value = 8, },
{ .center_freq = 2452, .hw_value = 9, },
{ .center_freq = 2457, .hw_value = 10, },
{ .center_freq = 2462, .hw_value = 11, },
{ .center_freq = 2467, .hw_value = 12, },
{ .center_freq = 2472, .hw_value = 13, },
{ .center_freq = 2484, .hw_value = 14, },
};
#define NUM_DRIVE_MODES 2
/* Agnx operate mode */
enum {
AGNX_MODE_80211A,
AGNX_MODE_80211A_OOB,
AGNX_MODE_80211A_MIMO,
AGNX_MODE_80211B_SHORT,
AGNX_MODE_80211B_LONG,
AGNX_MODE_80211G,
AGNX_MODE_80211G_OOB,
AGNX_MODE_80211G_MIMO,
};
enum {
AGNX_UNINIT,
AGNX_START,
AGNX_STOP,
};
struct agnx_priv {
struct pci_dev *pdev;
struct ieee80211_hw *hw;
spinlock_t lock;
struct mutex mutex;
unsigned int init_status;
void __iomem *ctl; /* pointer to base ram address */
void __iomem *data; /* pointer to mem region #2 */
struct agnx_ring rx;
struct agnx_ring txm;
struct agnx_ring txd;
/* Need volatile? */
u32 irq_status;
struct delayed_work periodic_work; /* Periodic tasks like recalibrate */
struct ieee80211_low_level_stats stats;
/* unsigned int phymode; */
int mode;
int channel;
u8 bssid[ETH_ALEN];
u8 mac_addr[ETH_ALEN];
u8 revid;
struct ieee80211_supported_band band;
};
#define AGNX_CHAINS_MAX 6
#define AGNX_PERIODIC_DELAY 60000 /* unit: ms */
#define LOCAL_STAID 0 /* the station entry for the card itself */
#define BSSID_STAID 1 /* the station entry for the bsssid AP */
#define spi_delay() udelay(40)
#define eeprom_delay() udelay(40)
#define routing_table_delay() udelay(50)
/* PDU pool MEM region #2 */
#define AGNX_PDUPOOL 0x40000 /* PDU pool */
#define AGNX_PDUPOOL_SIZE 0x8000 /* PDU pool size*/
#define AGNX_PDU_TX_WQ 0x41000 /* PDU list TX workqueue */
#define AGNX_PDU_FREE 0x41800 /* Free Pool */
#define PDU_SIZE 0x80 /* Free Pool node size */
#define PDU_FREE_CNT 0xd0 /* Free pool node count */
/* RF stuffs */
extern void rf_chips_init(struct agnx_priv *priv);
extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw);
extern void calibrate_oscillator(struct agnx_priv *priv);
extern void do_calibration(struct agnx_priv *priv);
extern void antenna_calibrate(struct agnx_priv *priv);
extern void __antenna_calibrate(struct agnx_priv *priv);
extern void print_offsets(struct agnx_priv *priv);
extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel);
#endif /* AGNX_H_ */
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#include <linux/delay.h>
#include <linux/etherdevice.h>
#include "phy.h"
#include "sta.h"
#include "debug.h"
void hash_read(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id)
{
void __iomem *ctl = priv->ctl;
reglo &= 0xFFFF;
reglo |= 0x30000000;
reglo |= 0x40000000; /* Set status busy */
reglo |= sta_id << 16;
iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo);
}
void hash_write(struct agnx_priv *priv, const u8 *mac_addr, u8 sta_id)
{
void __iomem *ctl = priv->ctl;
u32 reghi, reglo;
if (!is_valid_ether_addr(mac_addr))
printk(KERN_WARNING PFX "Update hash table: Invalid hwaddr!\n");
reghi = mac_addr[0] << 24 | mac_addr[1] << 16 | mac_addr[2] << 8 | mac_addr[3];
reglo = mac_addr[4] << 8 | mac_addr[5];
reglo |= 0x10000000; /* Set hash commmand */
reglo |= 0x40000000; /* Set status busy */
reglo |= sta_id << 16;
iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
if (!(reglo & 0x80000000))
printk(KERN_WARNING PFX "Update hash table failed\n");
}
void hash_delete(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id)
{
void __iomem *ctl = priv->ctl;
reglo &= 0xFFFF;
reglo |= 0x20000000;
reglo |= 0x40000000; /* Set status busy */
reglo |= sta_id << 16;
iowrite32(0, ctl + AGNX_RXM_HASH_CMD_FLAG);
iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH);
iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo);
}
void hash_dump(struct agnx_priv *priv, u8 sta_id)
{
void __iomem *ctl = priv->ctl;
u32 reghi, reglo;
reglo = 0x40000000; /* status bit */
iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW);
iowrite32(sta_id << 16, ctl + AGNX_RXM_HASH_DUMP_DATA);
udelay(80);
reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH);
reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW);
printk(PFX "hash cmd are : %.8x%.8x\n", reghi, reglo);
reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_FLAG);
printk(PFX "hash flag is : %.8x\n", reghi);
reghi = ioread32(ctl + AGNX_RXM_HASH_DUMP_MST);
reglo = ioread32(ctl + AGNX_RXM_HASH_DUMP_LST);
printk(PFX "hash dump mst lst: %.8x%.8x\n", reghi, reglo);
reghi = ioread32(ctl + AGNX_RXM_HASH_DUMP_DATA);
printk(PFX "hash dump data: %.8x\n", reghi);
}
void get_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx)
{
void __iomem *ctl = priv->ctl;
memcpy_fromio(power, ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx,
sizeof(*power));
}
inline void
set_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx)
{
void __iomem *ctl = priv->ctl;
/* FIXME 2. Write Template to offset + station number */
memcpy_toio(ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx,
power, sizeof(*power));
}
void get_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
unsigned int sta_idx, unsigned int wq_idx)
{
void __iomem *data = priv->data;
memcpy_fromio(tx_wq, data + AGNX_PDU_TX_WQ + sizeof(*tx_wq) * STA_TX_WQ_NUM * sta_idx +
sizeof(*tx_wq) * wq_idx, sizeof(*tx_wq));
}
inline void set_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
unsigned int sta_idx, unsigned int wq_idx)
{
void __iomem *data = priv->data;
memcpy_toio(data + AGNX_PDU_TX_WQ + sizeof(*tx_wq) * STA_TX_WQ_NUM * sta_idx +
sizeof(*tx_wq) * wq_idx, tx_wq, sizeof(*tx_wq));
}
void get_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx)
{
void __iomem *data = priv->data;
memcpy_fromio(sta, data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx,
sizeof(*sta));
}
inline void set_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx)
{
void __iomem *data = priv->data;
memcpy_toio(data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx,
sta, sizeof(*sta));
}
/* FIXME */
void sta_power_init(struct agnx_priv *priv, unsigned int sta_idx)
{
struct agnx_sta_power power;
u32 reg;
AGNX_TRACE;
memset(&power, 0, sizeof(power));
reg = agnx_set_bits(EDCF, EDCF_SHIFT, 0x1);
power.reg = cpu_to_le32(reg);
set_sta_power(priv, &power, sta_idx);
udelay(40);
} /* add_power_template */
/* @num: The #number of station that is visible to the card */
static void sta_tx_workqueue_init(struct agnx_priv *priv, unsigned int sta_idx)
{
struct agnx_sta_tx_wq tx_wq;
u32 reg;
unsigned int i;
memset(&tx_wq, 0, sizeof(tx_wq));
reg = agnx_set_bits(WORK_QUEUE_VALID, WORK_QUEUE_VALID_SHIFT, 1);
reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 1);
/* reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 0); */
tx_wq.reg2 |= cpu_to_le32(reg);
/* Suppose all 8 traffic class are used */
for (i = 0; i < STA_TX_WQ_NUM; i++)
set_sta_tx_wq(priv, &tx_wq, sta_idx, i);
} /* sta_tx_workqueue_init */
static void sta_traffic_init(struct agnx_sta_traffic *traffic)
{
u32 reg;
memset(traffic, 0, sizeof(*traffic));
reg = agnx_set_bits(NEW_PACKET, NEW_PACKET_SHIFT, 1);
reg |= agnx_set_bits(TRAFFIC_VALID, TRAFFIC_VALID_SHIFT, 1);
/* reg |= agnx_set_bits(TRAFFIC_ACK_TYPE, TRAFFIC_ACK_TYPE_SHIFT, 1); */
traffic->reg0 = cpu_to_le32(reg);
/* 3. setting RX Sequence Number to 4095 */
reg = agnx_set_bits(RX_SEQUENCE_NUM, RX_SEQUENCE_NUM_SHIFT, 4095);
traffic->reg1 = cpu_to_le32(reg);
}
/* @num: The #number of station that is visible to the card */
void sta_init(struct agnx_priv *priv, unsigned int sta_idx)
{
/* FIXME the length of sta is 256 bytes Is that
* dangerous to stack overflow? */
struct agnx_sta sta;
u32 reg;
int i;
memset(&sta, 0, sizeof(sta));
/* Set valid to 1 */
reg = agnx_set_bits(STATION_VALID, STATION_VALID_SHIFT, 1);
/* Set Enable Concatenation to 0 (?) */
reg |= agnx_set_bits(ENABLE_CONCATENATION, ENABLE_CONCATENATION_SHIFT, 0);
/* Set Enable Decompression to 0 (?) */
reg |= agnx_set_bits(ENABLE_DECOMPRESSION, ENABLE_DECOMPRESSION_SHIFT, 0);
sta.reg = cpu_to_le32(reg);
/* Initialize each of the Traffic Class Structures by: */
for (i = 0; i < 8; i++)
sta_traffic_init(sta.traffic + i);
set_sta(priv, &sta, sta_idx);
sta_tx_workqueue_init(priv, sta_idx);
} /* sta_descriptor_init */
#ifndef AGNX_STA_H_
#define AGNX_STA_H_
#define STA_TX_WQ_NUM 8 /* The number of TX workqueue one STA has */
struct agnx_hash_cmd {
__be32 cmdhi;
#define MACLO 0xFFFF0000
#define MACLO_SHIFT 16
#define STA_ID 0x0000FFF0
#define STA_ID_SHIFT 4
#define CMD 0x0000000C
#define CMD_SHIFT 2
#define STATUS 0x00000002
#define STATUS_SHIFT 1
#define PASS 0x00000001
#define PASS_SHIFT 1
__be32 cmdlo;
} __attribute__((__packed__));
/*
* Station Power Template
* FIXME Just for agn100 yet
*/
struct agnx_sta_power {
__le32 reg;
#define SIGNAL 0x000000FF /* signal */
#define SIGNAL_SHIFT 0
#define RATE 0x00000F00
#define RATE_SHIFT 8
#define TIFS 0x00001000
#define TIFS_SHIFT 12
#define EDCF 0x00002000
#define EDCF_SHIFT 13
#define CHANNEL_BOND 0x00004000
#define CHANNEL_BOND_SHIFT 14
#define PHY_MODE 0x00038000
#define PHY_MODE_SHIFT 15
#define POWER_LEVEL 0x007C0000
#define POWER_LEVEL_SHIFT 18
#define NUM_TRANSMITTERS 0x00800000
#define NUM_TRANSMITTERS_SHIFT 23
} __attribute__((__packed__));
/*
* TX Workqueue Descriptor
*/
struct agnx_sta_tx_wq {
__le32 reg0;
#define HEAD_POINTER_LOW 0xFF000000 /* Head pointer low */
#define HEAD_POINTER_LOW_SHIFT 24
#define TAIL_POINTER 0x00FFFFFF /* Tail pointer */
#define TAIL_POINTER_SHIFT 0
__le32 reg3;
#define ACK_POINTER_LOW 0xFFFF0000 /* ACK pointer low */
#define ACK_POINTER_LOW_SHIFT 16
#define HEAD_POINTER_HIGH 0x0000FFFF /* Head pointer high */
#define HEAD_POINTER_HIGH_SHIFT 0
__le32 reg1;
/* ACK timeout tail packet count */
#define ACK_TIMOUT_TAIL_PACK_CNT 0xFFF00000
#define ACK_TIMOUT_TAIL_PACK_CNT_SHIFT 20
/* Head timeout tail packet count */
#define HEAD_TIMOUT_TAIL_PACK_CNT 0x000FFF00
#define HEAD_TIMOUT_TAIL_PACK_CNT_SHIFT 8
#define ACK_POINTER_HIGH 0x000000FF /* ACK pointer high */
#define ACK_POINTER_HIGH_SHIFT 0
__le32 reg2;
#define WORK_QUEUE_VALID 0x80000000 /* valid */
#define WORK_QUEUE_VALID_SHIFT 31
#define WORK_QUEUE_ACK_TYPE 0x40000000 /* ACK type */
#define WORK_QUEUE_ACK_TYPE_SHIFT 30
/* Head timeout window limit fragmentation count */
#define HEAD_TIMOUT_WIN_LIM_FRAG_CNT 0x3FFF0000
#define HEAD_TIMOUT_WIN_LIM_FRAG_CNT_SHIFT 16
/* Head timeout window limit byte count */
#define HEAD_TIMOUT_WIN_LIM_BYTE_CNT 0x0000FFFF
#define HEAD_TIMOUT_WIN_LIM_BYTE_CNT_SHIFT 0
} __attribute__((__packed__));
/*
* Traffic Class Structure
*/
struct agnx_sta_traffic {
__le32 reg0;
#define ACK_TIMOUT_CNT 0xFF800000 /* ACK Timeout Counts */
#define ACK_TIMOUT_CNT_SHIFT 23
#define TRAFFIC_ACK_TYPE 0x00600000 /* ACK Type */
#define TRAFFIC_ACK_TYPE_SHIFT 21
#define NEW_PACKET 0x00100000 /* New Packet */
#define NEW_PACKET_SHIFT 20
#define TRAFFIC_VALID 0x00080000 /* Valid */
#define TRAFFIC_VALID_SHIFT 19
#define RX_HDR_DESC_POINTER 0x0007FFFF /* RX Header Descripter pointer */
#define RX_HDR_DESC_POINTER_SHIFT 0
__le32 reg1;
#define RX_PACKET_TIMESTAMP 0xFFFF0000 /* RX Packet Timestamp */
#define RX_PACKET_TIMESTAMP_SHIFT 16
#define TRAFFIC_RESERVED 0x0000E000 /* Reserved */
#define TRAFFIC_RESERVED_SHIFT 13
#define SV 0x00001000 /* sv */
#define SV_SHIFT 12
#define RX_SEQUENCE_NUM 0x00000FFF /* RX Sequence Number */
#define RX_SEQUENCE_NUM_SHIFT 0
__le32 tx_replay_cnt_low; /* TX Replay Counter Low */
__le16 tx_replay_cnt_high; /* TX Replay Counter High */
__le16 rx_replay_cnt_high; /* RX Replay Counter High */
__be32 rx_replay_cnt_low; /* RX Replay Counter Low */
} __attribute__((__packed__));
/*
* Station Descriptors
*/
struct agnx_sta {
__le32 tx_session_keys[4]; /* Transmit Session Key (0-3) */
__le32 rx_session_keys[4]; /* Receive Session Key (0-3) */
__le32 reg;
#define ID_1 0xC0000000 /* id 1 */
#define ID_1_SHIFT 30
#define ID_0 0x30000000 /* id 0 */
#define ID_0_SHIFT 28
#define ENABLE_CONCATENATION 0x0FF00000 /* Enable concatenation */
#define ENABLE_CONCATENATION_SHIFT 20
#define ENABLE_DECOMPRESSION 0x000FF000 /* Enable decompression */
#define ENABLE_DECOMPRESSION_SHIFT 12
#define STA_RESERVED 0x00000C00 /* Reserved */
#define STA_RESERVED_SHIFT 10
#define EAP 0x00000200 /* EAP */
#define EAP_SHIFT 9
#define ED_NULL 0x00000100 /* ED NULL */
#define ED_NULL_SHIFT 8
#define ENCRYPTION_POLICY 0x000000E0 /* Encryption Policy */
#define ENCRYPTION_POLICY_SHIFT 5
#define DEFINED_KEY_ID 0x00000018 /* Defined Key ID */
#define DEFINED_KEY_ID_SHIFT 3
#define FIXED_KEY 0x00000004 /* Fixed Key */
#define FIXED_KEY_SHIFT 2
#define KEY_VALID 0x00000002 /* Key Valid */
#define KEY_VALID_SHIFT 1
#define STATION_VALID 0x00000001 /* Station Valid */
#define STATION_VALID_SHIFT 0
__le32 tx_aes_blks_unicast; /* TX AES Blks Unicast */
__le32 rx_aes_blks_unicast; /* RX AES Blks Unicast */
__le16 aes_format_err_unicast_cnt; /* AES Format Error Unicast Counts */
__le16 aes_replay_unicast; /* AES Replay Unicast */
__le16 aes_decrypt_err_unicast; /* AES Decrypt Error Unicast */
__le16 aes_decrypt_err_default; /* AES Decrypt Error default */
__le16 single_retry_packets; /* Single Retry Packets */
__le16 failed_tx_packets; /* Failed Tx Packets */
__le16 muti_retry_packets; /* Multiple Retry Packets */
__le16 ack_timeouts; /* ACK Timeouts */
__le16 frag_tx_cnt; /* Fragment TX Counts */
__le16 rts_brq_sent; /* RTS Brq Sent */
__le16 tx_packets; /* TX Packets */
__le16 cts_back_timeout; /* CTS Back Timeout */
__le32 phy_stats_high; /* PHY Stats High */
__le32 phy_stats_low; /* PHY Stats Low */
struct agnx_sta_traffic traffic[8]; /* Traffic Class Structure (8) */
__le16 traffic_class0_frag_success; /* Traffic Class 0 Fragment Success */
__le16 traffic_class1_frag_success; /* Traffic Class 1 Fragment Success */
__le16 traffic_class2_frag_success; /* Traffic Class 2 Fragment Success */
__le16 traffic_class3_frag_success; /* Traffic Class 3 Fragment Success */
__le16 traffic_class4_frag_success; /* Traffic Class 4 Fragment Success */
__le16 traffic_class5_frag_success; /* Traffic Class 5 Fragment Success */
__le16 traffic_class6_frag_success; /* Traffic Class 6 Fragment Success */
__le16 traffic_class7_frag_success; /* Traffic Class 7 Fragment Success */
__le16 num_frag_non_prime_rates; /* number of Fragments for non-prime rates */
__le16 ack_timeout_non_prime_rates; /* ACK Timeout for non-prime rates */
} __attribute__((__packed__));
struct agnx_beacon_hdr {
struct agnx_sta_power power; /* Tx Station Power Template */
u8 phy_hdr[6]; /* PHY Hdr */
u8 frame_len_lo; /* Frame Length Lo */
u8 frame_len_hi; /* Frame Length Hi */
u8 mac_hdr[24]; /* MAC Header */
/* FIXME */
/* 802.11(abg) beacon */
} __attribute__((__packed__));
void hash_write(struct agnx_priv *priv, const u8 *mac_addr, u8 sta_id);
void hash_dump(struct agnx_priv *priv, u8 sta_id);
void hash_read(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id);
void hash_delete(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id);
void get_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx);
void set_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power,
unsigned int sta_idx);
void get_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
unsigned int sta_idx, unsigned int wq_idx);
void set_sta_tx_wq(struct agnx_priv *priv, struct agnx_sta_tx_wq *tx_wq,
unsigned int sta_idx, unsigned int wq_idx);
void get_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx);
void set_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int sta_idx);
void sta_power_init(struct agnx_priv *priv, unsigned int num);
void sta_init(struct agnx_priv *priv, unsigned int num);
#endif /* AGNX_STA_H_ */
#include <linux/pci.h>
#include <linux/delay.h>
#include "agnx.h"
#include "debug.h"
#include "phy.h"
static const u32
tx_fir_table[] = { 0x19, 0x5d, 0xce, 0x151, 0x1c3, 0x1ff, 0x1ea, 0x17c, 0xcf,
0x19, 0x38e, 0x350, 0x362, 0x3ad, 0x5, 0x44, 0x59, 0x49,
0x21, 0x3f7, 0x3e0, 0x3e3, 0x3f3, 0x0 };
void tx_fir_table_init(struct agnx_priv *priv)
{
void __iomem *ctl = priv->ctl;
int i;
for (i = 0; i < ARRAY_SIZE(tx_fir_table); i++)
iowrite32(tx_fir_table[i], ctl + AGNX_FIR_BASE + i*4);
} /* fir_table_setup */
static const u32
gain_table[] = { 0x8, 0x8, 0xf, 0x13, 0x17, 0x1b, 0x1f, 0x23, 0x27, 0x2b,
0x2f, 0x33, 0x37, 0x3b, 0x3f, 0x43, 0x47, 0x4b, 0x4f,
0x53, 0x57, 0x5b, 0x5f, 0x5f, 0x5f, 0x5f, 0x5f, 0x5f,
0x5f, 0x5f, 0x5f, 0x5f };
void gain_table_init(struct agnx_priv *priv)
{
void __iomem *ctl = priv->ctl;
int i;
for (i = 0; i < ARRAY_SIZE(gain_table); i++) {
iowrite32(gain_table[i], ctl + AGNX_GAIN_TABLE + i*4);
iowrite32(gain_table[i], ctl + AGNX_GAIN_TABLE + i*4 + 0x80);
}
} /* gain_table_init */
void monitor_gain_table_init(struct agnx_priv *priv)
{
void __iomem *ctl = priv->ctl;
unsigned int i;
for (i = 0; i < 0x44; i += 4) {
iowrite32(0x61, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0x61, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0x44; i < 0x64; i += 4) {
iowrite32(0x6e, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0x6e, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0x64; i < 0x94; i += 4) {
iowrite32(0x7a, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0x7a, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0x94; i < 0xdc; i += 4) {
iowrite32(0x87, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0x87, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0xdc; i < 0x148; i += 4) {
iowrite32(0x95, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0x95, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0x148; i < 0x1e8; i += 4) {
iowrite32(0xa2, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0xa2, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
for (i = 0x1e8; i <= 0x1fc; i += 4) {
iowrite32(0xb0, ctl + AGNX_MONGCR_BASE + i);
iowrite32(0xb0, ctl + AGNX_MONGCR_BASE + 0x200 + i);
}
} /* monitor_gain_table_init */
void routing_table_init(struct agnx_priv *priv)
{
void __iomem *ctl = priv->ctl;
unsigned int type, subtype;
u32 reg;
disable_receiver(priv);
for (type = 0; type < 0x3; type++) {
for (subtype = 0; subtype < 0x10; subtype++) {
/* 1. Set Routing table to R/W and to Return status on Read */
reg = (type << ROUTAB_TYPE_SHIFT) |
(subtype << ROUTAB_SUBTYPE_SHIFT);
reg |= (1 << ROUTAB_RW_SHIFT) | (1 << ROUTAB_STATUS_SHIFT);
if (type == ROUTAB_TYPE_DATA) {
/* NULL goes to RFP */
if (subtype == ROUTAB_SUBTYPE_NULL)
/* reg |= ROUTAB_ROUTE_RFP; */
reg |= ROUTAB_ROUTE_CPU;
/* QOS NULL goes to CPU */
else if (subtype == ROUTAB_SUBTYPE_QOSNULL)
reg |= ROUTAB_ROUTE_CPU;
/* All Data and QOS data subtypes go to Encryption */
else if ((subtype == ROUTAB_SUBTYPE_DATA) ||
(subtype == ROUTAB_SUBTYPE_DATAACK) ||
(subtype == ROUTAB_SUBTYPE_DATAPOLL) ||
(subtype == ROUTAB_SUBTYPE_DATAPOLLACK) ||
(subtype == ROUTAB_SUBTYPE_QOSDATA) ||
(subtype == ROUTAB_SUBTYPE_QOSDATAACK) ||
(subtype == ROUTAB_SUBTYPE_QOSDATAPOLL) ||
(subtype == ROUTAB_SUBTYPE_QOSDATAACKPOLL))
reg |= ROUTAB_ROUTE_ENCRY;
/* reg |= ROUTAB_ROUTE_CPU; */
/*Drop NULL and QOS NULL ack, poll and poll ack*/
else if ((subtype == ROUTAB_SUBTYPE_NULLACK) ||
(subtype == ROUTAB_SUBTYPE_QOSNULLACK) ||
(subtype == ROUTAB_SUBTYPE_NULLPOLL) ||
(subtype == ROUTAB_SUBTYPE_QOSNULLPOLL) ||
(subtype == ROUTAB_SUBTYPE_NULLPOLLACK) ||
(subtype == ROUTAB_SUBTYPE_QOSNULLPOLLACK))
/* reg |= ROUTAB_ROUTE_DROP; */
reg |= ROUTAB_ROUTE_CPU;
} else {
reg |= (ROUTAB_ROUTE_CPU);
}
iowrite32(reg, ctl + AGNX_RXM_ROUTAB);
/* Check to verify that the status bit cleared */
routing_table_delay();
}
}
enable_receiver(priv);
} /* routing_table_init */
void tx_engine_lookup_tbl_init(struct agnx_priv *priv)
{
void __iomem *data = priv->data;
unsigned int i;
for (i = 0; i <= 28; i += 4)
iowrite32(0xb00c, data + AGNX_ENGINE_LOOKUP_TBL + i);
for (i = 32; i <= 120; i += 8) {
iowrite32(0x1e58, data + AGNX_ENGINE_LOOKUP_TBL + i);
iowrite32(0xb00c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
}
for (i = 128; i <= 156; i += 4)
iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i);
for (i = 160; i <= 248; i += 8) {
iowrite32(0x1858, data + AGNX_ENGINE_LOOKUP_TBL + i);
iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
}
for (i = 256; i <= 284; i += 4)
iowrite32(0x980c, data + AGNX_ENGINE_LOOKUP_TBL + i);
for (i = 288; i <= 376; i += 8) {
iowrite32(0x1a58, data + AGNX_ENGINE_LOOKUP_TBL + i);
iowrite32(0x1858, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
}
for (i = 512; i <= 540; i += 4)
iowrite32(0xc00c, data + AGNX_ENGINE_LOOKUP_TBL + i);
for (i = 544; i <= 632; i += 8) {
iowrite32(0x2058, data + AGNX_ENGINE_LOOKUP_TBL + i);
iowrite32(0xc00c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
}
for (i = 640; i <= 668; i += 4)
iowrite32(0xc80c, data + AGNX_ENGINE_LOOKUP_TBL + i);
for (i = 672; i <= 764; i += 8) {
iowrite32(0x2258, data + AGNX_ENGINE_LOOKUP_TBL + i);
iowrite32(0xc80c, data + AGNX_ENGINE_LOOKUP_TBL + i + 4);
}
}
#ifndef AGNX_TABLE_H_
#define AGNX_TABLE_H_
void tx_fir_table_init(struct agnx_priv *priv);
void gain_table_init(struct agnx_priv *priv);
void monitor_gain_table_init(struct agnx_priv *priv);
void routing_table_init(struct agnx_priv *priv);
void tx_engine_lookup_tbl_init(struct agnx_priv *priv);
#endif /* AGNX_TABLE_H_ */
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config COMEDI config COMEDI
tristate "Data acquisition support (comedi)" tristate "Data acquisition support (comedi)"
default N default N
depends on m depends on m && (PCI || PCMCIA || PCCARD || USB)
---help--- ---help---
Enable support a wide range of data acquisition devices Enable support a wide range of data acquisition devices
for Linux. for Linux.
......
...@@ -2337,7 +2337,7 @@ static int resize_async_buffer(struct comedi_device *dev, ...@@ -2337,7 +2337,7 @@ static int resize_async_buffer(struct comedi_device *dev,
} }
DPRINTK("comedi%i subd %d buffer resized to %i bytes\n", DPRINTK("comedi%i subd %d buffer resized to %i bytes\n",
dev->minor, s - dev->subdevices, async->prealloc_bufsz); dev->minor, (int)(s - dev->subdevices), async->prealloc_bufsz);
return 0; return 0;
} }
......
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