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Commit ffa09d93 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
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drm/amd/display: Query VCO frequency from register for DCN3.1 

[Why]
Hardcoding the VCO frequency isn't correct since we don't own or control
the value.

In the case where the hardcode is also missing we can't lightup display.

[How]
Query from the CLK register instead. Update the DFS frequency to be able
to compute the VCO frequency.
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f891ae71
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Inline Side-by-side
Showing with 42 additions and 55 deletions
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View file @ ffa09d93
...@@ -48,6 +48,21 @@ ...@@ -48,6 +48,21 @@
#include "dc_dmub_srv.h" #include "dc_dmub_srv.h"
#include "yellow_carp_offset.h"
#define regCLK1_CLK_PLL_REQ 0x0237
#define regCLK1_CLK_PLL_REQ_BASE_IDX 0
#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
#define REG(reg_name) \
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
#define TO_CLK_MGR_DCN31(clk_mgr)\ #define TO_CLK_MGR_DCN31(clk_mgr)\
container_of(clk_mgr, struct clk_mgr_dcn31, base) container_of(clk_mgr, struct clk_mgr_dcn31, base)
...@@ -229,7 +244,32 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, ...@@ -229,7 +244,32 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
{ {
return 0; /* get FbMult value */
struct fixed31_32 pll_req;
unsigned int fbmult_frac_val = 0;
unsigned int fbmult_int_val = 0;
/*
* Register value of fbmult is in 8.16 format, we are converting to 31.32
* to leverage the fix point operations available in driver
*/
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
pll_req = dc_fixpt_from_int(fbmult_int_val);
/*
* since fractional part is only 16 bit in register definition but is 32 bit
* in our fix point definiton, need to shift left by 16 to obtain correct value
*/
pll_req.value |= fbmult_frac_val << 16;
/* multiply by REFCLK period */
pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
/* integer part is now VCO frequency in kHz */
return dc_fixpt_floor(pll_req);
} }
static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base) static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
...@@ -592,6 +632,7 @@ void dcn31_clk_mgr_construct( ...@@ -592,6 +632,7 @@ void dcn31_clk_mgr_construct(
clk_mgr->base.dprefclk_ss_percentage = 0; clk_mgr->base.dprefclk_ss_percentage = 0;
clk_mgr->base.dprefclk_ss_divider = 1000; clk_mgr->base.dprefclk_ss_divider = 1000;
clk_mgr->base.ss_on_dprefclk = false; clk_mgr->base.ss_on_dprefclk = false;
clk_mgr->base.dfs_ref_freq_khz = 48000;
clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
clk_mgr->base.base.ctx, clk_mgr->base.base.ctx,
......
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
View file @ ffa09d93
...@@ -27,60 +27,6 @@ ...@@ -27,60 +27,6 @@
#define __DCN31_CLK_MGR_H__ #define __DCN31_CLK_MGR_H__
#include "clk_mgr_internal.h" #include "clk_mgr_internal.h"
//CLK1_CLK_PLL_REQ
#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
//CLK1_CLK0_DFS_CNTL
#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
/*DPREF clock related*/
#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
//CLK3_0_CLK3_CLK_PLL_REQ
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
#define mmCLK0_CLK3_DFS_CNTL 0x16C60
#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
#define mmCLK0_CLK_PLL_REQ 0x16C10
#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
#define mmCLK1_CLK_PLL_REQ 0x1B00D
#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
#define mmCLK2_CLK_PLL_REQ 0x17E0D
/*AMCLK*/
#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
#endif
struct dcn31_watermarks; struct dcn31_watermarks;
struct dcn31_smu_watermark_set { struct dcn31_smu_watermark_set {
......
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