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Commit ffe91cb2 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}() 

All clocks in this driver are supported by the common simple probe
mechanism and it's now possible to migrate to it.

While at it, also switch to using the module_platform_driver() macro.
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-15-angelogioacchino.delregno@collabora.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent ff962100
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Showing with 37 additions and 204 deletions
drivers/clk/mediatek/clk-mt8365.c
View file @ ffe91cb2
...@@ -752,220 +752,53 @@ static const struct mtk_gate peri_clks[] = { ...@@ -752,220 +752,53 @@ static const struct mtk_gate peri_clks[] = {
&mtk_clk_gate_ops_no_setclr), &mtk_clk_gate_ops_no_setclr),
}; };
static int clk_mt8365_top_probe(struct platform_device *pdev) static const struct mtk_clk_desc topck_desc = {
{ .clks = top_clk_gates,
void __iomem *base; .num_clks = ARRAY_SIZE(top_clk_gates),
struct clk_hw_onecell_data *clk_data; .fixed_clks = top_fixed_clks,
struct device_node *node = pdev->dev.of_node; .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
struct device *dev = &pdev->dev; .factor_clks = top_divs,
int ret; .num_factor_clks = ARRAY_SIZE(top_divs),
int i; .mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
base = devm_platform_ioremap_resource(pdev, 0); .composite_clks = top_misc_muxes,
if (IS_ERR(base)) .num_composite_clks = ARRAY_SIZE(top_misc_muxes),
return PTR_ERR(base); .divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); .clk_lock = &mt8365_clk_lock,
if (!clk_data) };
return -ENOMEM;
ret = mtk_clk_register_fixed_clks(top_fixed_clks,
ARRAY_SIZE(top_fixed_clks), clk_data);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
clk_data);
if (ret)
goto unregister_fixed_clks;
ret = mtk_clk_register_muxes(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), node,
&mt8365_clk_lock, clk_data);
if (ret)
goto unregister_factors;
ret = mtk_clk_register_composites(&pdev->dev, top_misc_muxes,
ARRAY_SIZE(top_misc_muxes), base,
&mt8365_clk_lock, clk_data);
if (ret)
goto unregister_muxes;
ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt8365_clk_lock, clk_data);
if (ret)
goto unregister_composites;
ret = mtk_clk_register_gates(&pdev->dev, node, top_clk_gates,
ARRAY_SIZE(top_clk_gates), clk_data);
if (ret)
goto unregister_dividers;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_gates;
return 0;
unregister_gates:
mtk_clk_unregister_gates(top_clk_gates, ARRAY_SIZE(top_clk_gates), clk_data);
unregister_dividers:
mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
clk_data);
unregister_composites:
mtk_clk_unregister_composites(top_misc_muxes,
ARRAY_SIZE(top_misc_muxes), clk_data);
unregister_muxes:
mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
unregister_factors:
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
unregister_fixed_clks:
mtk_clk_unregister_fixed_clks(top_fixed_clks,
ARRAY_SIZE(top_fixed_clks), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static int clk_mt8365_infra_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int ret;
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_gates(&pdev->dev, node, ifr_clks,
ARRAY_SIZE(ifr_clks), clk_data);
if (ret)
goto free_clk_data;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_gates;
return 0;
unregister_gates:
mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static int clk_mt8365_peri_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
if (ret)
return ret;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
return ret;
}
static int clk_mt8365_mcu_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
ARRAY_SIZE(mcu_muxes), base,
&mt8365_clk_lock, clk_data);
if (ret)
goto free_clk_data;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_composites;
return 0; static const struct mtk_clk_desc infra_desc = {
.clks = ifr_clks,
.num_clks = ARRAY_SIZE(ifr_clks),
};
unregister_composites: static const struct mtk_clk_desc peri_desc = {
mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), .clks = peri_clks,
clk_data); .num_clks = ARRAY_SIZE(peri_clks),
free_clk_data: };
mtk_free_clk_data(clk_data);
return ret; static const struct mtk_clk_desc mcu_desc = {
} .composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
.clk_lock = &mt8365_clk_lock,
};
static const struct of_device_id of_match_clk_mt8365[] = { static const struct of_device_id of_match_clk_mt8365[] = {
{ { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc },
.compatible = "mediatek,mt8365-topckgen", { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc },
.data = clk_mt8365_top_probe, { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc },
}, { { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc },
.compatible = "mediatek,mt8365-infracfg", { /* sentinel */ }
.data = clk_mt8365_infra_probe, };
}, {
.compatible = "mediatek,mt8365-pericfg",
.data = clk_mt8365_peri_probe,
}, {
.compatible = "mediatek,mt8365-mcucfg",
.data = clk_mt8365_mcu_probe,
}, {
/* sentinel */
}
};
static int clk_mt8365_probe(struct platform_device *pdev)
{
int (*clk_probe)(struct platform_device *pdev);
int ret;
clk_probe = of_device_get_match_data(&pdev->dev);
if (!clk_probe)
return -EINVAL;
ret = clk_probe(pdev);
if (ret)
dev_err(&pdev->dev,
"%s: could not register clock provider: %d\n",
pdev->name, ret);
return ret;
}
static struct platform_driver clk_mt8365_drv = { static struct platform_driver clk_mt8365_drv = {
.probe = clk_mt8365_probe,
.driver = { .driver = {
.name = "clk-mt8365", .name = "clk-mt8365",
.of_match_table = of_match_clk_mt8365, .of_match_table = of_match_clk_mt8365,
}, },
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
}; };
module_platform_driver(clk_mt8365_drv);
static int __init clk_mt8365_init(void)
{
return platform_driver_register(&clk_mt8365_drv);
}
arch_initcall(clk_mt8365_init);
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
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