- 13 Jan, 2021 4 commits
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Daniele Ceraolo Spurio authored
Initialize all required entries from guc_set_default_submission, instead of calling the execlists function. The previously inherited setup has been copied over from the execlist code and simplified by removing the execlists submission-specific parts. v2: move setting of relative_mmio flag to engine_setup_common (Chris) Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: John Harrison <john.c.harrison@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1 Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210113021236.8164-5-daniele.ceraolospurio@intel.com
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Daniele Ceraolo Spurio authored
Instead of starting the engine in execlists submission mode and then switching to GuC, start directly in GuC submission mode. The initial setup functions have been copied over from the execlists code and simplified by removing the execlists submission-specific parts. v2: remove unneeded unexpected starting state check (Chris) Signed-off-by:
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Daniele Ceraolo Spurio authored
GuC owns the execlists state and the context IDs used for submission, so the status of the ports and the CSB entries are not something we control or can decode from the i915 side, therefore we can avoid dumping it. A follow-up patch will also stop setting the csb pointers when using GuC submission. GuC dumps all the required events in the GuC logs when verbosity is set high enough. Signed-off-by:
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Matthew Brost authored
Delete GuC code unused in future patches that rewrite the GuC interface to work with the new firmware. Most of the code deleted relates to workqueues or execlist port. The code is safe to remove because we still don't allow GuC submission to be enabled, even when overriding the modparam, so it currently can't be reached. The defines + structs for the process descriptor and workqueue remain. Although the new GuC interface does not require either of these for the normal submission path multi-lrc submission does. The usage of the process descriptor and workqueue for multi-lrc will be quite different from the code that is deleted in this patch. A future patch will implement multi-lrc submission. v2: add a code in the commit message about the code being safe to remove (Chris) Signed-off-by:
Matthew Brost <matthew.brost@intel.com> Signed-off-by:
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- 12 Jan, 2021 10 commits
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Matthew Auld authored
Device local-memory should be thought of as part the GT, which means it should also sit under gt/. Suggested-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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Jani Nikula authored
There are no users outside of intel_region_lmem.c. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Jani Nikula authored
There are no users outside of intel_memory_region.c. Signed-off-by:
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Chris Wilson authored
During igt_reset_nop_engine, it was observed that an unexpected failed engine reset lead to us busywaiting on the stop-ring semaphore (set during the reset preparations) on the first request afterwards. There was no explicit MI_ARB_CHECK in this sequence as the presumption was that the failed MI_SEMAPHORE_WAIT would itself act as an arbitration point. It did not in this circumstance, so force it. This patch is based on the assumption that the MI_SEMAPHORE_WAIT failure to arbitrate is a rare Tigerlake bug, similar to the lite-restore vs semaphore issues previously seen in the CS. The explicit MI_ARB_CHECK should always ensure that there is at least one arbitration point in the request before the MI_SEMAPHORE_WAIT to trigger the IDLE->ACTIVE event. Upon processing that event, we will clear the stop-ring flag and release the semaphore from its busywait. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210112100759.32698-2-chris@chris-wilson.co.uk
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Chris Wilson authored
On the off chance that we need to arbitrate before launching the payload, perform the check after we signal the request is ready to start. Assuming instantaneous processing of the CS event, the request will then be treated as having started when we make the decisions as to how to process that CS event. v2: More commentary about the users of i915_request_started() as a reminder about why we are marking the initial breadcrumb. Signed-off-by:
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Chris Wilson authored
A new fi-cml-dallium CI machine has 8G and apparently plenty free, yet fails some selftests with ENOMEM. The failures all seem to be from huge_gem_object which does not try very hard to allocate memory, skipping reclaim entirely. Let's try a bit harder and direct reclaim before failing. Signed-off-by:
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Chris Wilson authored
If this stolen object holds the last reference to the region, we need to remove our drm_mm_node before freeing the region's drm_mm. <4> [431.679591] Memory manager not clean during takedown. <4> [431.679633] WARNING: CPU: 0 PID: 110 at drivers/gpu/drm/drm_mm.c:999 drm_mm_takedown+0x51/0x100 <4> [431.679655] Modules linked in: i915 vgem btusb snd_hda_codec_hdmi btrtl btbcm btintel snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio bluetooth coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel ecdh_generic ecc r8169 realtek lpc_ich snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm pinctrl_cherryview prime_numbers [last unloaded: i915] <4> [431.679883] CPU: 0 PID: 110 Comm: kworker/u4:3 Tainted: G U 5.11.0-rc3-CI-CI_DRM_9583+ #1 <4> [431.679895] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0058.2016.1102.1842 11/02/2016 <4> [431.679905] Workqueue: i915 __i915_gem_free_work [i915] <4> [431.680831] RIP: 0010:drm_mm_takedown+0x51/0x100 <4> [431.680850] Code: 44 24 08 65 48 33 04 25 28 00 00 00 0f 85 b6 00 00 00 48 83 c4 10 5b 5d 41 5c c3 48 89 fb 48 c7 c7 c8 b7 38 82 e8 00 d6 37 00 <0f> 0b 48 8b 3d 96 d5 d1 00 ba 00 10 00 00 be c0 0c 00 00 e8 d7 64 <4> [431.680862] RSP: 0018:ffffc90000ad7dc0 EFLAGS: 00010282 <4> [431.680879] RAX: 0000000000000000 RBX: ffff8881109aa140 RCX: 0000000000000001 <4> [431.680888] RDX: 0000000080000001 RSI: ffffffff8235a70f RDI: 00000000ffffffff <4> [431.680897] RBP: ffff8881109aa178 R08: 0000000000000001 R09: 0000000000000001 <4> [431.680906] R10: 0000000025eaec48 R11: 00000000f5b271a7 R12: ffff88810a38ddc0 <4> [431.680916] R13: 00000000ffffffff R14: ffffffff82861b70 R15: ffff88810b715538 <4> [431.680925] FS: 0000000000000000(0000) GS:ffff88817b800000(0000) knlGS:0000000000000000 <4> [431.680935] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [431.680945] CR2: 000056377cfd7c48 CR3: 00000001045de000 CR4: 00000000001006f0 <4> [431.680954] Call Trace: <4> [431.680977] __intel_memory_region_destroy+0x24/0x50 [i915] <4> [431.681340] i915_gem_object_release_stolen+0x26/0x40 [i915] <4> [431.681637] __i915_gem_free_objects.isra.21+0x1ef/0x3b0 [i915] <4> [431.681935] process_one_work+0x270/0x5c0 <4> [431.682022] worker_thread+0x37/0x380 <4> [431.682047] ? process_one_work+0x5c0/0x5c0 <4> [431.682062] kthread+0x146/0x170 <4> [431.682077] ? kthread_park+0x80/0x80 <4> [431.682098] ret_from_fork+0x22/0x30 <4> [431.682153] irq event stamp: 1872905 <4> [431.682162] hardirqs last enabled at (1872911): [<ffffffff8112bd9a>] console_unlock+0x49a/0x580 <4> [431.682176] hardirqs last disabled at (1872916): [<ffffffff8112bd06>] console_unlock+0x406/0x580 <4> [431.682187] softirqs last enabled at (1872850): [<ffffffff81e00342>] __do_softirq+0x342/0x48e <4> [431.682201] softirqs last disabled at (1872845): [<ffffffff81c00f52>] asm_call_irq_on_stack+0x12/0x20 <4> [431.682214] ---[ end trace 5d3bcd818e2e3816 ]--- <3> [431.686188] [drm:drm_mm_takedown] *ERROR* node [0002d000 + 00004000]: inserted at drm_mm_insert_node_in_range+0x34a/0x5b0 i915_gem_stolen_insert_node_in_range+0x7b/0xa0 [i915] _i915_gem_object_create_stolen+0x83/0xd0 [i915] i915_gem_object_create_region+0x61/0x140 [i915] intel_engine_create_ring+0x176/0x230 [i915] Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2927Signed-off-by:
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Chris Wilson authored
The clear-residuals mitigation is a relatively heavy hammer and under some circumstances the user may wish to forgo the context isolation in order to meet some performance requirement. Introduce a generic module parameter to allow selectively enabling/disabling different mitigations. To disable just the clear-residuals mitigation (on Ivybridge, Baytrail, or Haswell) use the module parameter: i915.mitigations=auto,!residuals Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1858 Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111225220.3483-3-chris@chris-wilson.co.uk
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Chris Wilson authored
The mitigation is required for all gen7 platforms, now that it does not cause GPU hangs, restore it for Ivybridge and Baytrail. Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Reviewed-by:
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Chris Wilson authored
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the range [0, n-1] where n is #EU * (#threads/EU) with the number of threads based on plaform and the number of EU based on the number of slices and subslices. This is a fixed number per platform/gt, so appropriately limit the number of threads we spawn to match the device. v2: Oversaturate the system with tasks to force execution on every HW thread; if the thread idles it is returned to the pool and may be reused again before an unused thread. v3: Fix more state commands, which was causing Baytrail to barf. v4: STATE_CACHE_INVALIDATE requires a stall on Ivybridge Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024 Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
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- 11 Jan, 2021 3 commits
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Chris Wilson authored
During igt_reset_nop_engine, an engine reset unexpectedly failed. For the next time this happens, mention which engine that was. Signed-off-by:
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Chris Wilson authored
Braswell's pdp workaround is full of dragons, that may be being angered when they are interrupted. Let's not take that risk and disable arbitration during the update. Signed-off-by:
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Dan Carpenter authored
These error paths return success instead of negative error codes as intended. Fixes: c92724de ("drm/i915/selftests: Try to detect rollback during batchbuffer preemption") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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- 09 Jan, 2021 4 commits
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Chris Wilson authored
When wedging the device, we cancel all outstanding requests and mark them as EIO. Rather than duplicate the small function to do so between each submission backend, export one. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210109163455.28466-3-chris@chris-wilson.co.uk
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Chris Wilson authored
drivers/gpu/drm/i915//gt/intel_workarounds.c:1394:20: error: function 'is_nonpriv_flags_valid' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] static inline bool is_nonpriv_flags_valid(u32 flags) This is only used by debug build, so mark it as maybe-unused to keep the compiler from complaining. Signed-off-by:
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Chris Wilson authored
>> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function 'dword_in_page' [-Werror,-Wunused-function] static inline unsigned int dword_in_page(void *addr) Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Chris Wilson authored
Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a failure to construct the workarounds. v2: Avoid mentioning an error for fault-injection, other CI will complain about the dmesg spam. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210109114453.27798-1-chris@chris-wilson.co.uk
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- 08 Jan, 2021 7 commits
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Chris Wilson authored
If a request is submitted and known to require no preemption, disable arbitration around the batch which prevents the HW from handling a preemption request during the payload. Signed-off-by:
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Chris Wilson authored
The reason why we did not enable preemption on Broadwater was due to missing GPGPU workarounds. Since this only applies to rcs0, only restrict rcs0 (and our global capabilities). While this does not affect exposing a preemption capability to userspace, it does affect our internal decisions on whether to use timeslicing and semaphores between individual engines. Signed-off-by:
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Chris Wilson authored
We use the completion of the last active breadcrumb to retire the requests along a timeline. This is purely opportunistic as nothing guarantees that any particular timeline is terminated by a breadcrumb; except for parking the engine where we explicitly add a breadcrumb so that we park quickly and do an explicit retire upon signaling to reduce the latency dramatically (avoiding a retire worker roundtrip). With scheduling, we anticipate retiring completed timelines as a matter of course. Performing the same action from inside the breadcrumbs is intended to provide similar functionality for legacy ringbuffer submission. Signed-off-by:
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Chris Wilson authored
Before we mark the virtual engine as no longer inflight, flush any ongoing signaling that may be using the ce->signal_link along the previous breadcrumbs. On switch to a new physical engine, that link will be inserted into the new set of breadcrumbs, causing confusion to an ongoing iterator. This patch undoes a last minute mistake introduced into commit bab0557c ("drm/i915/gt: Remove virtual breadcrumb before transfer"), whereby instead of unconditionally applying the flush, it was only applied if the request itself was going to be reused. v2: Generalise and cancel all remaining ce->signals Fixes: bab0557c ("drm/i915/gt: Remove virtual breadcrumb before transfer") Signed-off-by:
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Chris Wilson authored
In our tests where we measure the elapsed time on both the CPU and CS using a udelay, our CS results match the udelay much more accurately than the ktime (even when using ktime_get_fast_ns). With preemption disabled, we can go one step lower than ktime and use local_clock. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2919Signed-off-by:
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Chris Wilson authored
If any of the perf tests run into 0 time, not only are we liable to divide by zero, but the result would be highly questionable. Nevertheless, let's not have a div-by-zero error. Signed-off-by:
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Chris Wilson authored
On error we unpin and free the wa_ctx.vma, but do not clear any of the derived flags. During lrc_init, we look at the flags and attempt to dereference the wa_ctx.vma if they are set. To protect the error path where we try to limp along without the wa_ctx, make sure we clear those flags! Reported-by:
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- 07 Jan, 2021 2 commits
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Chris Wilson authored
In the next^W future patch, we remove the strict priority system and continuously re-evaluate the relative priority of tasks. As such we need to enable the timeslice whenever there is more than one context in the pipeline. This simplifies the decision and removes some of the tweaks to suppress timeslicing, allowing us to lift the timeslice enabling to a common spot at the end of running the submission tasklet. One consequence of the suppression is that it was reducing fairness between virtual engines on an over saturated system; undermining the principle for timeslicing. v2: Commentary v3: Commentary for the right cancel_timer() v4: Add tracing for why we need a timeslice Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2802 Testcase: igt/gem_exec_balancer/fairslice Signed-off-by:
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Chris Wilson authored
Refactor our timer_list.expires checking into its own timer_active() helper. Signed-off-by:
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- 06 Jan, 2021 2 commits
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Chris Wilson authored
Use memset_io() on the iomem, and silence sparse as we copy from the iomem to normal system pages. Signed-off-by:
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Chris Wilson authored
AFter detecting a register mismatch between the protocontext and the image generated by HW, immediately break out of the double loop. Otherwise we end up with a second confusing error message. Signed-off-by:
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- 05 Jan, 2021 5 commits
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Chris Wilson authored
In generating the reference LRC, we want a page-aligned address for simplicity in computing the offsets within. This then shares the computation for the HW LRC which is mapped and so page aligned, making the comparison straightforward. It seems that kmalloc(4k) is not always returning from a 4k-aligned slab cache (which would give us a page aligned address) so force alignment by explicitly allocating a page. Reported-by:
"Gote, Nitin R" <nitin.r.gote@intel.com> Signed-off-by:
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Chris Wilson authored
If another sibling is able to claim the virtual request, by the time we inspect the request under the lock it may no longer match the local engine. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2877Signed-off-by:
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Chris Wilson authored
If the engine reset fails, we will attempt to resume with the current inflight submissions. When that happens, we cannot assert that the engine reset cleared the pending submission, so do not. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2878 Fixes: 16f2941a ("drm/i915/gt: Replace direct submit with direct call to tasklet") Signed-off-by:
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Chris Wilson authored
Older platforms use rawclk to derive the CS clock. rawclk is being determined during intel_device_info_init(), and so that needs to be pushed slightly earlier. Fixes: f170523a ("drm/i915/gt: Consolidate the CS timestamp clocks") Signed-off-by:
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Chris Wilson authored
A few missed PTR_ERR() upon create_gang() errors. Signed-off-by:
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- 04 Jan, 2021 3 commits
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Chris Wilson authored
In the near future, upstream will introduce a SZ_8G macro that is slightly different to our own. Employ a temporary ifndef to avoid compilation failure until we have backmerged. References: 8b0fac44 ("sizes.h: add SZ_8G/SZ_16G/SZ_32G macros") Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210104171511.32684-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Some rcs0 workarounds were being incorrectly applied to the GT, and so we failed to restore the expected register settings after a reset. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210104114914.30165-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Some rcs0 workarounds were being incorrectly applied to the GT, and so we failed to restore the expected register settings after a reset. Signed-off-by:
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