- 28 Jul, 2015 40 commits
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Rob Herring authored
set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Mike Turquette <mturquette@baylibre.com> Acked-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by:
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Jun Nie authored
The array of parent names can be made as array of const pointers to const strings. Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
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Jun Nie authored
Add SPDIF/I2S and GPIO clock for zx296702 Signed-off-by:
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Jun Nie authored
Add SPDIF/I2S divider clock method for zx296702 Signed-off-by:
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Vaibhav Hiremath authored
This patch cleans up the driver for, - Use devm_kcalloc() variant instead of devm_kzalloc() for array allocation. - clk_prepare()/unprepare(), remove "ret" variable as it is not required - use __exit for cleanup function As I am referring this driver as a reference for my 88pm800 clk driver, applying same changes here as well. Signed-off-by:Vaibhav Hiremath <vaibhav.hiremath@linaro.org> Tested-by:
Anand Moon <linux.amoon@gmail.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
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Stephen Boyd authored
The recursive spinlock implementation trips up sparse and it complains that these functions have lock imbalances. That isn't really true though, so add some __acquires() and __releases() information so that sparse is quiet. drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock Signed-off-by: -
Stephen Boyd authored
The basic clock types use conditional locking for the register accessor spinlocks. Add __acquire() and __release() markings in the right locations so that sparse isn't tripped up on the conditional locking. drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: -
Stephen Boyd authored
The missing license causes the clk-qcom.ko module to taint the kernel. Add the appropriate license to avoid taint. Signed-off-by: -
Stephen Boyd authored
Let's encourage const arrays of parent names like other basic clock types. Cc: Sergej Sawazki <ce3a@gmx.de> Signed-off-by: -
Michael Turquette authored
Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
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Jim Quinlan authored
This commit allows certain Broadcom STB clock dividers to be used with clk-divider.c. It allows for a clock whose field value is the equal to the divisor, execpt when the field value is zero, in which case the divisor is 2^width. For example, consider a divisor clock with a two bit field: value divisor 0 4 1 1 2 2 3 3 Signed-off-by:
Jim Quinlan <jim2101024@gmail.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Andy Shevchenko authored
Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
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Robert Jarzmik authored
Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency. This reporting was broken because the expected unit is kHz and not Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx. Fixes: fe7710fa ("clk: add pxa25x clock drivers") Fixes: d40670dc ("clk: add pxa27x clock drivers") Fixes: 9bbb8a33 ("clk: pxa: add pxa3xx clock driver") Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Douglas Anderson authored
In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by:Douglas Anderson <dianders@chromium.org> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Stephen Boyd authored
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by:
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Signed-off-by:
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by:
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by:
Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by:
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by:
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James Liao authored
MT8173 MMPLL frequency settings are different from common PLLs. It needs different post divider settings for some ranges of frequency. This patch add support for MT8173 MMPLL frequency setting by adding div-rate table to lookup suitable post divider setting under a specified frequency. Signed-off-by:
James Liao <jamesjj.liao@mediatek.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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James Liao authored
Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by:
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James Liao authored
Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by:
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Stephen Boyd authored
clk providers are using the consumer APIs to set min/max rates on the clock they're providing. To encourage clk providers to move away from the consumer APIs, add a provider API to set the min/max rate of a clock. The assumption is that this is done before the clock can be requested via clk_get() and that the clock rate is already within the boundaries of the min/max that's configured. Tested-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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Axel Lin authored
Use devm_clk_register() to simplify the code by removing twl6040_clk_remove(). Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Axel Lin authored
The devm_clk_unregister() in .probe error case is not necessary as it will be automatically called when probe fails. Signed-off-by:
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Geert Uytterhoeven authored
The CCF implementations for the various shmobile SoCs don't use clkdev functionality, hence drop the inclusion of <linux/clkdev.h>. Add the missing #include <linux/slab.h>, which was included implicitly through <asm/clkdev.h> before. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Stephen Boyd authored
Add __force here so that sparse doesn't complain about us playing tricks with __iomem. Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Stephen Boyd authored
Sparse complains about these structures missing static, but they also don't look to be used. Remove them. drivers/clk/ti/clk-3xxx.c:74:30: warning: symbol 'clkhwops_omap3430es2_ssi_wait' was not declared. Should it be static? drivers/clk/ti/clk-3xxx.c:157:30: warning: symbol 'clkhwops_omap3430es2_hsotgusb_wait' was not declared. Should it be static? Acked-by:
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Stephen Boyd authored
This variable isn't exported outside of this file so mark it static. Silences the following sparse warning: drivers/clk/ti/clk.c:36:24: warning: symbol 'ti_clk_features' was not declared. Should it be static? Acked-by:
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Stephen Boyd authored
smatch reports a failure to check kzalloc() here: drivers/clk/ti/clk.c:232 omap2_clk_provider_init() error: potential null dereference 'io'. (kzalloc returns null) Check for an allocation failure and return -ENOMEM. Acked-by:
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https://github.com/t-kristo/linux-pmStephen Boyd authored
From Tero Kristo: "This pull request contains the TI clock driver set to move the clock implementations under clock driver. Some small portions of the clock driver code still remain under mach-omap2 after this, it should be decided whether this code is now obsolete and should be deleted or should someone try to fix it." Slight merge conflicts with determine_rate prototype changes.
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Axel Lin authored
of_clk_get_parent_count() may return negative error code, so num_parents needs to be int rather than unsigned int. Signed-off-by:
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Stephen Boyd authored
The other ce clocks have the flag set, but ce1 doesn't, so clk_set_rate() doesn't propagate up the tree to the ce1_src_clk. Set the flag as this is supported. Reported-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Tested-by:
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Stephen Boyd authored
We don't unlock the mutex if we fail to allocate the parent names array. Unlock it and return an error in this case as well. Reported-by:
kbuild test robot <fengguang.wu@intel.com> Acked-by:
Julia Lawall <julia.lawall@lip6.fr> Cc: Sergej Sawazki <ce3a@gmx.de> Signed-off-by:
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Stephen Boyd authored
There doesn't seem to be any reason why we can't use the standard readb()/writeb() accessors here because ctrl_inb() and ctrl_outb() match the generic implementation of readb() and writeb() that the h8300 architecture uses. This allows us to test compile this driver on other architectures besides h8300. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
We don't need to print an error on allocation failures, drop it. While we're here, change the sizeof() to be sizeof(*<ptr>) to make code more future proof. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
* clk-determine-rate-struct: clk: fix some determine_rate implementations clk: change clk_ops' ->determine_rate() prototype
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Boris Brezillon authored
Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by:
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Boris Brezillon authored
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by:
Romain Perier <romain.perier@gmail.com> Signed-off-by:
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