- 02 Mar, 2021 20 commits
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Alex Deucher authored
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Xiaogang Chen authored
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT interrupt(hpd, hpd_rx) by using work queue and uses single work_struct. If new interrupt is recevied before the previous handler finished, new interrupts(same type) will be discarded and driver just sends "amdgpu_dm_irq_schedule_work FAILED" message out. If some important hpd, hpd_rx related interrupts are missed by driver the hot (un)plug devices may cause system hang or instability, such as issues with system resume from S3 sleep with mst device connected. This patch dynamically allocates new amdgpu_dm_irq_handler_data for new interrupts if previous INTERRUPT_LOW_IRQ_CONTEXT interrupt work has not been handled. So the new interrupt works can be queued to the same workqueue_struct, instead of discard the new interrupts. All allocated amdgpu_dm_irq_handler_data are put into a single linked list and will be reused after. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses reminder of 64 bit division (modulus operator) , which is not supported by 32 bit platforms [how] Use div64 API for 64 bit modulus Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Bindu Ramamurthy<bindu.r@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses division operator for 64 bit division, which is not supported by 32 bit platforms [how] Use div64 API for 64 bit division Signed-off-by:
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Jonathan Kim authored
Request to stop DF performance counters is missing the actual write to the controller register. Reported-by:
Chris Freehill <chris.freehill@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Acked-by:
Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by:
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Dillon Varone authored
[Why?] HSplit should not affect DSC slice count. Can cause improper timings to be applied for certain modes. [How?] No longer change DSC Slice count based on HSplit. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Hugo Hu authored
[Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Tested-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Aric Cyr authored
DC version 3.2.125 brings improvements in multiple areas. In summary, we highlight: - DSC fixes - Enable ASSR - Firmware relase 0.0.54 - eDP interface refactor for multiple eDP Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] DMUB FW send trace event via outbox0 interrupt. Driver will handle it. Tested-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] GPINT timeout is causing PSR_STATE_0 to be returned when it shouldn't. We must guarantee that PSR is fully disabled before doing hw programming on driver-side. [How] Return invalid state if GPINT command times out. Let existing retry logic send the GPINT until successful. Tested-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Jake Wang authored
[Why & How] Some existing DC interfaces are optimized to return a single eDP link/stream. Refactored those DC interfaces to support multiple eDP. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Eryk Brol authored
[Why] Useful for testing when setting a max bpc value higher than the default is required [How] Allow for reading/writing of the max_requested_bpc property of the connector Tested-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Max.Tseng authored
[why] Add flag to build infopacket in SDP v1.3 format Tested-by:
Max.Tseng <Max.Tseng@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why] Currently the creation of link encoder objects is tightly coupled to the creation of link objects. Decoupling link encoder object creation is a preliminary step in the process of allowing link encoders to be dynamically assigned to links. [How] Add "minimal" link encoder objects which are not associated with any link until required. Tested-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
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Evan Quan authored
By using the information provided by PMFW when available. V2: put those structures shared around SMU V11 ASICs in smu_v11_0.h Signed-off-by: -
Evan Quan authored
New changes were involved for the SmuMetrics structure. Signed-off-by:
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Kevin Wang authored
miss RAP TA in loop. (when i == 4) Fix: drm/amdgpu: add RAP TA version print in amdgpu_firmware_info Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reported-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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- 26 Feb, 2021 20 commits
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c:273:16-21: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:924:47-52: WARNING: conversion to bool not needed here. Reported-by:
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Dennis Li authored
If the number of badpage records exceed the threshold, driver has updated both epprom header and control->tbl_hdr.header before gpu reset, therefore GPU recovery thread no need to read epprom header directly. v2: merge amdgpu_ras_check_err_threshold into amdgpu_ras_eeprom_check_err_threshold Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Shirish S authored
report -ENOTSUPP instead of -EINVAL, so that if userspace fails to read sensor data can figure it out the failure correctly. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Evan Quan authored
Arcturus has a different register address from other SMU V11 ASICs. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Kevin Wang authored
add RAP TA version print in amdgpu_firmware_info. Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:243:67-72: WARNING: conversion to bool not needed here. Reported-by:
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Yang Li authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1589:0-23: WARNING: fops_ib_preempt should be defined with DEFINE_DEBUGFS_ATTRIBUTE ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1592:0-23: WARNING: fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Per discussions with PMFW team, the driver only needs to notify the PMFW when the RLC is disabled. The RLC FW will notify the PMFW directly when it's enabled. Acked-by:
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Alex Deucher authored
Making them an error confuses users and the errors are harmless as not all asics support all profiles. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1488Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Alex Deucher authored
And just use the ioctl index. They are the same. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
So mesa can check when to query the kernel vs use hardcoded codec bandwidth data. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
We currently hardcode these in mesa, but querying them from the kernel makes more sense since there may be board specific limitations that the kernel driver is better suited to determining. Userpace patches that use this interface: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case, squash in memory leak fix v4: drop extra break Reviewed-by:
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Alex Deucher authored
For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by:
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Alex Deucher authored
This will be used by a new INFO ioctl query to fetch the decode and encode capabilities from the kernel driver rather than hardcoding them in mesa. This gives us more fine grained control of capabilities using information that is only availabl in the kernel (e.g., platform limitations or bandwidth restrictions). v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case Reviewed-by:
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Aurabindo Pillai authored
[Why] A seamless transition between modes can be performed if the new incoming mode has the same timing parameters as the optimized mode on a display with a variable vtotal min/max. Smooth video playback usecases can be enabled with this seamless transition by switching to a new mode which has a refresh rate matching the video. [How] Skip full modeset if userspace requested a compatible freesync mode which only differs in the front porch timing from the current mode. Signed-off-by:
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Aurabindo Pillai authored
[Why] While possible for userspace to create and add custom mode based off the optimized mode for the connected display which differs only in front porch timing, this patch set adds a list of common video modes in advance. The list of common video refresh rates is small, well known and the optimized mode has specific requirements to be able to enable HW frame doubling and tripling so it makes most sense to create the modes that video players will need in advance. The optimized mode matches the preferred mode resolution but has the highest refresh rate available to enable the largest front porch extension. [How] Find the optimized mode and store it on the connector so we can check it later during our optimized modeset. Prepopulate the mode list with a list of common video mades based on the optimized mode (but with a longer front porch) if the panel doesn't support a variant of the mode natively. Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why] This option shall be opt-in by default since it is a temporary solution until long term solution is agreed upon which may require userspace interface changes. This feature give the user a seamless experience when freesync aware programs (media players for instance) switches to a compatible freesync mode when playing videos. Enabling this feature also have the potential side effect of causing higher power consumption due to running a mode with lower resolution and base clock frequency with the highest base clock supported on the monitor as per its advertised modes. There has been precedent of manufacturing modes in the kernel. In AMDGPU, the existing usage are for common modes and scaling modes. Other driver have a similar approach as well. [How] Adds a module parameter to enable freesync video mode modeset optimization. Enabling this mode allows the driver to skip a full modeset when a freesync compatible mode is requested by the userspace. This parameter will also add some additional modes that are within the connected monitor's VRR range corresponding to common video modes, which media players can use for a seamless experience while making use of freesync. Signed-off-by:
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Ramesh Errabolu authored
Currently callers have to provide handle of amdgpu_device, which is not used by the implementation. It is unlikely this parameter will become useful in future, thus removing it v2: squash in unused variable fix Reviewed-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Jingwen Chen authored
Move gpu_reset_counter after drm_sched_stop to avoid race condition caused by job submitted between reset_count +1 and drm_sched_stop. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
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