- 14 Jan, 2019 40 commits
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Leo Li authored
[Why] This fixes an regression introduced by: drm/amd/display: add stream ID and otg instance in dc_stream_state During driver initialization, a null pointer deref is raised. This is caused by searching for a stream status in the dc->current_state before the dc_state swap happens at the end of dc_commit_state_no_check(). Since the swap has not happened, the dc_state to be swapped in should be searched, and not dc->current_state. [How] Add a function that searches for the stream status within the given dc_state, instead of dc->current_state. Use that before the state swap happens in dc_commit_state_no_check(). Also remove duplicate occurrences of this function in amdgpu_dm.c. Signed-off-by:Leo Li <sunpeng.li@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo Li authored
[Why] context->bw.dce.dispclk_khz is being cached into unpatched_clock, then restored at end of function call. This is needlessly complex [How] Instead, use a local patched_clock variable. Leave context->bw.dce.dispclk_khz alone. No functional change is intended. Signed-off-by:
David Francis <david.francis@amd.com> Signed-off-by:
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Eric Bernstein authored
[Why] There are different reasons for Validation failure error during atomic_check [How] Add better logging of the reason for validation failure Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Ken Chalmers authored
[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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SivapiriyanKumarasamy authored
[WHY] There is an extra null check for fs_params in the build_freesync_hdr function detected by Smatch. [HOW] 1) Remove the extra null check since it is checked in the caller. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Leo Li authored
[Why] It's not being used anywhere. [How] Remove it. Signed-off-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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David Francis authored
[Why] ABM enablement testing can be automated if a way of reading target and current hardware backlight is available [How] Expand debugfs interface with two new entries. Hook directly into dc interface. Units are as a fraction of 0x1000 = 100% Use the built-in amdgpu function for creating read-only debugfs files Signed-off-by:
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Jun Lei authored
[why] stream ID allows DMs to avoid memory address comparisons to compare stream equality. otg_instance allows DC to more rigorously define when otg_instance can change. specifically, it is now defined to be only mutable when dc_stream_state changes. This is better than a "get status" function which prevents efficient caching of otherwise very stable information. [how] stream ID follows similar pattern to sink ID, which is already implemented otg_instance is an output which occurs on all dc_stream modification functions Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
DV have made updates to DCN dml which we need to pull in Signed-off-by:
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David Francis authored
[Why] Backlight is conceptually a property of links, not streams. All backlight programming is done on links, but there is a stream property bl_pwm_level that is used to restore backlight on dpms on and s3 resume. This is unnecessary, as backlight is already restored by hardware with no driver intervention. [How] Remove bl_pwm_level, and the stream argument to set_backlight Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Imad Syed authored
They're not being used, so remove them. Signed-off-by:
Imad Syed <imad.syed@amd.com> Reviewed-by:
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Jun Lei authored
[why] dc_stream_state containing a pointer to sink is poor design. Sink describes the display, and the specifications or capabilities it has. That information is irrelevant for dc_stream_state, which describes hardware state, and is generally used for hardware programming. It could further be argued that dc_sink itself is just a convenience dc provides, and DC should be perfectly capable of programming hardware without any dc_sinks (for example, emulated sinks). [how] Phase 1: Deprecate use of dc_sink pointer in dc_stream. Most references are trivial to remove, but some call sites are risky (such as is_timing_changed) with no obvious logical replacement. These will be removed in follow up change. Add dc_link pointer to dc_stream. This is the typical reason DC really needed sink pointer, and most call sites are replaced with this. DMs also need minor updates, as all 3 DMs leverage stream->sink for some functionality. this is replaced instead by a pointer to private data inside dc_stream_state, which is used by DMs as a quality of life improvment for some key functionality. it allows DMs to set pointers have to their own objects which associate OS objects to dc_stream_states (such as DisplayTarget and amdgpu_dm_connector). Without the private pointer, DMs would be forced to perform a lookup for callbacks. Signed-off-by:
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Hugo Hu authored
[Why] So that we can adjust fclk for debugging purposes. [How] Add option to force adjust fclk request to pplib. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Eric Yang authored
[why] There was a recent fix in the BW spreadsheet to allow timing with very large vblank. Need to be ported into driver. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Krunoslav Kovac authored
[Why] We are not correctly handling the wrap around case. VLine interrupt is relative to position of VUpdate interrupt. Both VUpdate interrupt and VLine interrupt could possibly be in front porch or back porch. [How] Fix wraparound case by checking for line number that is greater than the VTOTAL of the OTG timing. In this case, the interrupt should occur on the next frame. Also fix some variable naming and remove some dead code. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] Driver didn't check plane size and surface size is mismatch. It will cause pitch data incorrect. [How] Add condition to check is plane change and update surface Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Some components depend on dc to constuct but need to assign callback functions to dc. [how] Instead of assigning dc callback functions in dc_create, decouple the callback init to a standlone function after dc_create. This is currently a no-op. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Remove braces around single-line conditionals Signed-off-by:
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Fatemeh Darbehani authored
[Why] To make sure future changes in DAL for SMU msgs will not change the current behaviour and to make sure clock registeres are programmed correctly based on SMU msgs that DAL sends. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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Eric Bernstein authored
1) Rename and make public definition of input CSC matrix struct. 2) Make wm_read_state() function an interface of hubbub, and check if watermark registers exist before read/write to them. 3) Check if OTG_INTERLACE_CONTROL register exists before updating 4) Add dummy functions for set_input/output_transfer function to avoid errors due to differences in CM registers. 5) Added missing register field definition in header file Signed-off-by:
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Eric Bernstein authored
Expose this function for future use. Signed-off-by:
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Jun Lei authored
Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Steven Chiu authored
Signed-off-by:
Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by:
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wentalou authored
psp_ring_destroy inside psp_load_fw cause psp->km_ring.ring_mem NULL. Call Trace occurred when psp_cmd_submit. should be psp_ring_stop instead. Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Signed-off-by:
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Xiangliang Yu authored
There isn't ucode when executing INVOKE command, so current code can't check the failure of INVOKE command. Remove the ucode check. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Oak Zeng authored
Use sdma_engine[8] array instead of sdma_engine0~7 so it is easier to program. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Xiangliang Yu authored
Driver get session id after loading TA FW and the session id is used by driver instances to communicate with TA. PF and VF have different session id. xGMI session id should get from response buffer, correct it. Signed-off-by:
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Amber Lin authored
kgd2kfd function pointers and global kgd2kfd pointer are no longer in use. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Amber Lin authored
After amdkfd is merged into amdgpu module, amdgpu can call amdkfd functions directly. Signed-off-by:
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Amber Lin authored
Since amdkfd is merged into amdgpu module and amdgpu can access amdkfd directly, move declaration of kgd2kfd functions from kfd_priv.h to amdgpu_amdkfd.h Signed-off-by:
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Christian König authored
We hit a problem with IOMMU with that. Disable until we have time to debug further. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Jim Qu authored
effect asics: VEGA10 and VEGA12 Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Acked-by:
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Tao Zhou authored
Fix CPDMA hang in PRT mode for both VEGA10 and VEGA20 Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Tested-by:
Yukun.Li <yukun1.li@amd.com> Acked-by:
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Evan Quan authored
Since soft min setting is enough. Hard min setting is redundant. Reported-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Evan Quan authored
Make sure the clock level enforced is within the allowed ranges. Signed-off-by:
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Evan Quan authored
Since pp_od_clk_voltage device file is for OD related sysfs operations. Signed-off-by:
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Evan Quan authored
For those ASICs with no overdrive capabilities, the OD support flag will be reset. Signed-off-by:
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Likun Gao authored
MGCG should RLC enter into safe mode first. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Kent Russell authored
These 2 variables are unused now, so remove their references. Fixes: e4ae0fc3 drm/amdgpu: implement gfx8 post_soft_reset Fixes: 5e01c09 drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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