- 16 Jan, 2020 26 commits
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Huang Rui authored
The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by MAP_QUEUES packet. So we only need set cp active field for kiq queue. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yong Zhao authored
SW scheduler is previously called non HW scheduler, or non HWS. This message is useful when triaging issues from dmesg. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
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Alex Deucher authored
count is size_t so don't use negative values. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Nirmoy Das authored
This patch uses score based logic to select a new rq for better loadbalance between multiple rq/scheds instead of num_jobs. Below are test results after running amdgpu_test from mesa drm Before this patch: sched_name num of many times it got scheduled ========= ================================== sdma0 314 sdma1 32 comp_1.0.0 56 comp_1.0.1 0 comp_1.1.0 0 comp_1.1.1 0 comp_1.2.0 0 comp_1.2.1 0 comp_1.3.0 0 comp_1.3.1 0 After this patch: sched_name num of many times it got scheduled ========= ================================== sdma0 216 sdma1 185 comp_1.0.0 39 comp_1.0.1 9 comp_1.1.0 12 comp_1.1.1 0 comp_1.2.0 12 comp_1.2.1 0 comp_1.3.0 12 comp_1.3.1 0 Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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James Zhu authored
Implement indirect DPG SRAM mode for vcn2.5 Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Add dpg pause mode support for vcn2.5 Signed-off-by:
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James Zhu authored
Add DPG mode start and stop functions for vcn2.5 v2: Correct firmware ucode index in vcn_v2_5_mc_resume_dpg_mode Signed-off-by:
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James Zhu authored
Move macro from vcn2.0 to amdgpu_vcn to share with vcn2.5 v2: squash in macro fix Signed-off-by:
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James Zhu authored
Add multiple instance direct SRAM read and write support for vcn2.5 v2: squash in indexing fix Signed-off-by:
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James Zhu authored
Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by:
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Jack Zhang authored
There's no need to dump ACTIVITY_MONITOR_COEFF under VF. Therefore, Skip the update of SMU_TABLE_ACTIVITY_MONITOR_COEFF under SRIOV VF. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
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Tianci.Yin authored
[why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was encroached by UMC firmware during GDDR6 BIST training, this cause page fault. [how] Forcing stolen_size to 3MB, then the bottom region of VRAM was allocated as stolen memory, GTT corruption avoid. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
remove registers: mmSPI_CONFIG_CNTL add registers: mmSPI_CONFIG_CNTL_1 Reviewed-by:
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Tianci.Yin authored
remove registers: mmSPI_CONFIG_CNTL add registers: mmSPI_CONFIG_CNTL_1 Reviewed-by:
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shaoyunl authored
In SRIOV, rlc_g firmware is loaded by host, guest driver won't load it which will cause the rlc_fw pointer is null Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Christian König authored
Entirely unused. Signed-off-by:
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Nirmoy Das authored
Disabled HW IP's entity initialized with NULL rq. We should not process any submit request from userspace for a disabled HW IP. Signed-off-by:
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Huang Rui authored
To align with gfx v9, we use the map_queues packet to load hiq MQD. Signed-off-by:
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Aaron Liu authored
There is an issue that CP will check the HIQ queue to be configured and mapped with KIQ ring, otherwise, it will be unable to read back the secure buffer while the gfxoff is enabled even with trusted IP blocks. v1 -> v2: - Fix to remove surplus set_resources packets. - Fill the whole configuration in MQD. - Change the author as Aaron because he addressed the key point of this issue. - Add kiq ring lock. v2 -> v3: - Free the lock while in error return case. - Remove the programming only needed by the queue is unmapped. v3 -> v4: - Remove doorbell programming because it's used for restarting queue. - Remove CP scheduler programming because map_queue packet will handle this. v4 -> v5: - Remove cp_hqd_active because mec ucode will enable it while use map_queues. - Revise goto out_unlock. - Correct the right doorbell offset for HIQ that kfd driver assigned in the packet. v5 -> v6: - Merge Arcturus fix into this patch because it will get oops in Arcturus platform. Reported-by:
Lisa Saturday <Lisa.Saturday@amd.com> Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Alex Sierra authored
[Why] kfd2kgd interface will be deprecated. This removal only covers TLB invalidation for now. They have been replaced in amdgpu_amdkfd API. [How] TLB invalidate functions removed from the different amdkfd_gfx_v* versions. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
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Alex Sierra authored
[Why] TLB flush method has been deprecated using kfd2kgd interface. This implementation is now on the amdgpu_amdkfd API. [How] TLB flush functions now implemented in amdgpu_amdkfd. Signed-off-by:
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Alex Sierra authored
This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Signed-off-by:
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Alex Sierra authored
[Why] There are HW-indpendent functions that enables and disables kcq. These functions use the kiq_pm4_funcs implementation. [How] Local kcq enable and disable functions removed and replace it by the generic kcq enable under amdgpu_gfx Signed-off-by:
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Alex Sierra authored
tlbs invalidate pointer function added to kiq_pm4_funcs struct. This way, tlb flush can be done through kiq member. TLBs invalidatation implemented for gfx9 and gfx10. Signed-off-by:
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Alex Sierra authored
Functions implemented from kiq_pm4_funcs struct members for gfx_v9 version. Signed-off-by:
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Alex Sierra authored
[Why] Avoid reclaim filesystem while eviction lock is held called from MMU notifier. [How] Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked. Using memalloc_nofs_save / memalloc_nofs_restore API. Signed-off-by:
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- 14 Jan, 2020 14 commits
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Alex Deucher authored
If driver debugfs files are accessed, power up the GPU when necessary. Reviewed-by:
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Alex Deucher authored
If power management sysfs or debugfs files are accessed, power up the GPU when necessary. Reviewed-by:
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Flora Cui authored
Fixes: 4dee6e4c ("drm/amdgpu: use linux size macro to simplify ONE_Kib & One_Mib") Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Chen Zhou authored
The conversion to bool is not needed, remove it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Chen Zhou <chenzhou10@huawei.com> Signed-off-by:
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Mario Kleiner authored
read_current_link_settings_on_detect() on eDP 1.4+ may use the edp_supported_link_rates table which is set up by detect_edp_sink_caps(), so that function needs to be called first. Reviewed-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Martin Leung <martin.leung@amd.com> Signed-off-by:
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Alex Deucher authored
So that it gets included in the initrd. At the moment this is optional firmware that contains support for HDCP. Reviewed-by:
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Joseph Greathouse authored
On Arcturus, data fabric hashing is set by the VBIOS, and affects which addresses map to which memory channels. The gfx core's caches also need to know this mapping, but the hash settings for these these caches is set by the driver. This change queries the DF to understand how the VBIOS configured DF, then matches the TC hash configuration bits to do the same thing. v2: squash in warning fix Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
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Joseph Greathouse authored
On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by:
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Joseph Greathouse authored
The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon. Signed-off-by:
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Michael Strauss authored
[WHY] Only a single voltage level should be available to Pollock (min level) Pollock & Dali get misidentified as Renoir, use wrong clk mgr constructor [HOW] Add provided Pollock IDs to ASIC Rev. ID list. Create new Pollock ASIC RID check, fix RV2 & Dali ASIC checks. Check RID and set max voltage level to 0 if Pollock is detected. Work around broken ASICREV_IS_RENOIR, IS_RAVEN2, etc. checks by performing Dali/Pollock checks before they can be misidentified as RN. Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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John Clements authored
between UMC RAS err register access restore previous RSMU UMC index mode state Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
in event of GPU reset, XGMI TA unload causes unrecoverable GPU hang Acked-by:
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Aaron Liu authored
Update mmSDMA0_UTCL1_WATERMK golden setting for renoir. Signed-off-by:
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Aaron Liu authored
This patch updates SMU12_DRIVER_IF_VERSION to 11. Signed-off-by:
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