- 24 Jan, 2023 39 commits
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Aurabindo Pillai authored
[Why&How] Switching between certain modes that are freesync video modes and those are not freesync video modes result in timing not changing as seen by the monitor due to incorrect timing being driven. The issue is fixed by ensuring that when a non freesync video mode is set, we reset the freesync status on the crtc. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jingwen Zhu authored
[Why] This is a workaround for an dcn3.1 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig was disabled. Reviewed-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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Stylon Wang authored
[Why] Connecting displays to TBT3 docks often produces invalid replies for DPIA AUX requests. It turns out the completion structure was not re-initialized before reusing it, resulting in immature wake up to completion. [How] Properly call reinit_completion() on reused completion structure. Cc: stable@vger.kernel.org Reviewed-by:
Solomon Chiu <solomon.chiu@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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Robin Chen authored
[Why] When DSC is enabled, the PSRSU seletive update region must be multiple number of DSC slice height number. The original solution is to overwrite the SU Y granularity by DSC slice height in DAL driver. However, the size of the SU Y granularity variable only has 8 bytes and the DSC slice height may over the 8 bytes size. [How] Instead of overwriting the SU Y granularity value, add a new DSC slice height pararmeter and pass it to DMUB PSRSU FW. The PSRSU FW will refer to the DSC slice height value and extend the SU region. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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Wenjing Liu authored
[why] Temporarly merge dc_link_dp functions into dc_link for the purpose of removing dc_link_dp files. This is a transitional change for later commits where we will further refactor dc_link file. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
Create new files link_dp_cts.c and link_dp_cts.h, and move DP cts functions into them. Reviewed-by:
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Wenjing Liu authored
Create new files link_dp_irq_handler.c and link_dp_irq_handler.h, and move DP irq handler functions into them. Reviewed-by:
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Sung Joon Kim authored
[why] Start enabling AdaptiveSync feature on Linux environment. [how] Adding AdaptiveSync support in DC layer - building AdaptiveSync info_packets - adjusting the v_startup parameter Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Samson Tam authored
[Why] MALL size available can vary for different SKUs. Use num_chans read from VBIOS to determine the available MALL size we can use [How] Define max_chans for DCN32 and DCN321. If num_chans is max_chans, then return max_chans as we can access the entire MALL space. Otherwise, define avail_chans as the number of available channels we are allowed instead. Return corresponding number of channels back and use this to calculate available MALL size. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Set init frequency for DCFCLK DS - For now choose 10Mhz after turning off all pipes on init - DCN32 spreadsheet shows 8Mhz is min for any display config Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Alvin Lee authored
[Description] Use |= when assigning to wm_optimized required because we don't want to overwrite the flag in case the optimize did not happen yet Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Wenjing Liu authored
Create new file link_edp_panel_control.c and link_edp_panel_control.h, and move eDP panel control logic into them. Reviewed-by:
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Wenjing Liu authored
[why] link component contains three sub folders: accessories - utilities for improving testability, logging or tracing, doesn't impact end user use cases. protocols - specs defined protocols used in end user use cases hwss - hwss owned link_hwss object, served as an abstraction layer in hwss to access various types of encoder/phy/dpia endpoints in a unified interface. sooner we will have files directly under link folder one for the implementation of each major link behavior such as link_create, link_detect, link_validate and link_set_dpms. Reviewed-by:
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Alvin Lee authored
[Description] - We cannot enable subvp on PSR panels because when PSR is active, HUBP is turned off and we cannot rely on the HUBP vline interrupt - When in PSR, surface data also cannot be prefetched to MALL because the main HUBP will be off Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - [FW Promotion] Release 0.0.150.0 - Correcting prefetch mode for fast validate - Set hvm_enabled flag for S/G mode - set allow_freesync parameter in DM - Revert "ignore msa parameter only if freesync is enabled" - Allow idle optimization after turning off all pipes - Guard Freesync HDMI parsing with dc_lock - Speed up DML fast_validate path - Disable MALL SS and messages for PSR supported configs - force connector state when bpc changes during compliance Acked-by:
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Anthony Koo authored
- Add comments to reserved bit Reviewed-by:
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David (Ming Qiang) Wu authored
AV1 is only supported on the first instance. Added vcn_v4_0_enc_find_ib_param() to help search for an IB param. Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Reviewed-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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Saaem Rizvi authored
[WHY and HOW] When fast validating, we should be agnostic to any sort of optimizations such as supporting Pstate or stutter in Vblank. We should change our prefetch mode for fast validate to support none of these optimizations. For example, Valve Index running at 144Hz can only be validated without any support these optimizations. Reviewed-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Roman Li authored
[Why] After enabling S/G on dcn314 a screen corruption may be observed. HostVM flag should be set in S/G mode to be included in DML calculations. [How] In S/G mode gpu_vm_support flag is set. Use its value to init is_hvm_enabled. Reviewed-by:
Roman Li <roman.li@amd.com> Tested-by:
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Wayne Lin authored
[why & how] adjust the coding in dm_helpers_dp_mst_send_payload_allocation() for reading easily. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Wayne Lin authored
[why & how] The term (i.e. port & mst_port) that we used to use in amdgpu is a bit confusing. Rename them to mst_output_port & mst_root respectively. Signed-off-by:
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Wayne Lin authored
[why & how] We still need to refer to port while removing payload at commit_tail. we should keep the kref till then to release. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171Signed-off-by:
Didier Raboud <odyx@debian.org> Signed-off-by:
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Wayne Lin authored
[why & how] __drm_dbg() parameter set format is wrong and not aligned with the format under CONFIG_DRM_USE_DYNAMIC_DEBUG is on. Fix it. Signed-off-by:
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Wayne Lin authored
[Why & How] Now the vc_start_slot is controlled at drm side. When we service a long HPD, we still need to run dm_helpers_dp_mst_write_payload_allocation_table() to update drm mst_mgr's relevant variable. Otherwise, on the next plug-in, payload will get assigned with a wrong start slot. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171Signed-off-by:
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Wayne Lin authored
[Why] amdgpu expects to update payload table for one stream one time by calling dm_helpers_dp_mst_write_payload_allocation_table(). Currently, it get modified to try to update HW payload table at once by referring mst_state. [How] This is just a quick workaround. Should find way to remove the temporary struct dc_dp_mst_stream_allocation_table later if set struct link_mst_stream_allocatio directly is possible. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171Signed-off-by:
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Lyude Paul authored
Looks like I made a pretty big mistake here without noticing: it seems when I moved the assignments of mst_state->pbn_div I completely missed the fact that the reason for us calling drm_dp_mst_update_slots() earlier was to account for the fact that we need to call this function using info from the root MST connector, instead of just trying to do this from each MST encoder's atomic check function. Otherwise, we end up filling out all of DC's link information with zeroes. So, let's restore that and hopefully fix this DSC regression. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171Signed-off-by:
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Tim Huang authored
The psp suspend & resume should be skipped to avoid destroy the TMR and reload FWs again for IMU enabled APU ASICs. Signed-off-by:
Tim Huang <tim.huang@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&how] There are cases where VRR is possible but not enabled. If allow_freesync parameter is not set, SubVP logic defaults to checking only the ignore MSA parameter that is always set if display is DRR capable, which breaks the system while trying to enable SubVP on multi monitor configs where freesync does not work due to Xorg limitation. SubVP uses allow_freesync parameter to check if SubVP + DRR case can be executed. Reviewed-by:
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Aurabindo Pillai authored
This reverts commit 6ffa6799. This commit introduced a regression in Unigine Heaven benchmark where the display would turn off due to incorrect handling of the parameter to ignore MSA packets. Reviewed-by:
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Alvin Lee authored
[Why] In certain D3 cases (BOCO / BOMACO) the hardware is reset but software state still has idle_optimizations = true. This prevents us from entering idle optimizations again if no display is connected. [How] In hw init, reset the idle optimization state, and allow idle optimizations after all pipes have been turned off. Reviewed-by:
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Stylon Wang authored
[Why] All calls into DC must be guarded by dc_lock because DC code is not safe against multi-thread or re-entry. [How] Hold dc_lock when calling DC interfaces to parse Freesync HDMI. Reviewed-by:
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Ilya Bakoulin authored
[Why] Iterating over every voltage state when we need to validate thousands of configurations all at once (i.e. display hotplug) can take a significant amount of time. [How] Check just the highest voltage state when fast_validate is true to verify whether the configuration can work at all, then do a proper validation including all voltage states later when fast_validate is false. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Dillon Varone authored
[Description] The two features are not supported at the same time in driver at this time, so disable it. Reviewed-by:
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Qingqing Zhuo authored
[Why] During DP DSC compliance tests, bpc requested would change between sub-tests, which requires stream to be recommited. [How] Force connector to disconnect and reconnect whenever there is a bpc change in automated test. Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Tested-by:
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Hamza Mahfooz authored
Not all ASICs support LTTPR, however if they don't it doesn't mean that we have encountered unexpected behaviour. So, use DC_NOT_SUPPORTED instead of DC_ERROR_UNEXPECTED. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Li Ma authored
To support new mes ip block Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Li Ma authored
The GC 11.0.4 needs load IMU to power up GFX before loads GFX firmware. Signed-off-by:
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Evan Quan authored
Add SMU13.0.0 AllowIHInterrupt message mapping. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Jonathan Kim authored
Rebase of driver has incorrect unconditional trap enablement for GFX11 when adding mes queues. Reported-by:
Graham Sider <graham.sider@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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- 19 Jan, 2023 1 commit
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Alex Deucher authored
Update to the latest launched dGPUs. Link: https://www.amd.com/en/graphics/radeon-rx-graphics Link: https://www.amd.com/en/graphics/amd-radeon-rx-laptopsReviewed-by:
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