- 08 May, 2024 9 commits
-
-
Ville Syrjälä authored
Child device 0x2 used to be "TV" until redefined to mean EFP5 in version 215. Add a define for the old meaning as well. Technically it was probably deprecated a lot before version 215 since native TV encoders were last seen on CTG, and SDVO was fully gone by HSW. So something like "???-164" might also be a reasonable way to document this, but no real harm in saying "???-214" since nothing else presumably occupied that bit in the meantime. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-7-ville.syrjala@linux.intel.comAcked-by:
Jani Nikula <jani.nikula@intel.com>
-
Ville Syrjälä authored
The SDVO LVDS blocks are specifically about LVDS, so stick to naming that reflects that. This also makes the names match the spec. Signed-off-by:
-
Ville Syrjälä authored
The LFP data applies to all kinds of display interfaces, so stop calling things by the "LVDS" name. Signed-off-by:
-
Ville Syrjälä authored
VBT reuses a bunch of EDID data structures. Flag those as such for clarity. I chose "bdb_edid_" as the namespace for these. Signed-off-by:
-
Ville Syrjälä authored
DEVICE_HANDLE_EFP4 has actually been in use since the very beginning, or at least something has been occupying that bit because old VBTs actually use it, and it definitely looks to be about external displays given how its used. So let's ignore what the current spec claims and remove the misleading version number comment. Signed-off-by:
-
Ville Syrjälä authored
There's a new "DSC disable" bit in the eDP VBT block. Define it. TODO: actually use it? Signed-off-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_DFT2_G4X register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_* register macros. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_CTL register macro. Reviewed-by:
-
- 07 May, 2024 1 commit
-
-
Karthikeyan Ramasubramanian authored
Starting BDB version 239, hdr_dpcd_refresh_timeout is introduced to backlight BDB data. Commit 70003456 ("drm/i915/bios: Define more BDB contents") updated the backlight BDB data accordingly. This broke the parsing of backlight BDB data in VBT for versions 236 - 238 (both inclusive) and hence the backlight controls are not responding on units with the concerned BDB version. backlight_control information has been present in backlight BDB data from at least BDB version 191 onwards, if not before. Hence this patch extracts the backlight_control information for BDB version 191 or newer. Tested on Chromebooks using Jasperlake SoC (reports bdb->version = 236). Tested on Chromebooks using Raptorlake SoC (reports bdb->version = 251). v2: removed checking the block size of the backlight BDB data [vsyrjala: this is completely safe thanks to commit e163cfb4 ("drm/i915/bios: Make copies of VBT data blocks")] Fixes: 70003456 ("drm/i915/bios: Define more BDB contents") Cc: stable@vger.kernel.org Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Karthikeyan Ramasubramanian <kramasub@chromium.org> Signed-off-by:
-
- 06 May, 2024 19 commits
-
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_LFPS_CTL register macro. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.comSigned-off-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL2 register macro. Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/09acf2751cfd2f524e6ba97c3ac285495eae5c86.1714471597.git.jani.nikula@intel.comSigned-off-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_SRCSZ_ERLY_TPT register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_MAN_TRK_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_SU_STATUS register macro. v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo) Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_STATUS register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR_EVENT register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_DEBUG register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_PERF_CNT register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_STATUS register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_DATA register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IIR register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IMR register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_CTL register macro. Reviewed-by:
-
Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_EXITLINE register macro. Reviewed-by:
-
- 03 May, 2024 11 commits
-
-
Balasubramani Vivekanandan authored
Enable the display support for Battlemage Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-20-radhakrishna.sripada@intel.com
-
Matthew Auld authored
Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
-
Nirmoy Das authored
Display surfaces can be tagged as transient by mapping it using one of the various L3:XD PAT index modes on Xe2. The expectation is that KMD needs to request transient data flush at the start of flip sequence to ensure all transient data in L3 cache is flushed to memory. Add a routine for this which we can then call from the display code. v2: rebase(RK) Signed-off-by:
-
Matthew Auld authored
Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by:
-
Balasubramani Vivekanandan authored
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by:
-
Ankit Nautiyal authored
This reverts commit 562f3383. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
-
Matt Roper authored
Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by:
Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by:
-
José Roberto de Souza authored
No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
-
Matt Roper authored
Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
-
Anusha Srivatsa authored
Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
-
Lucas De Marchi authored
Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
-
