- 24 Mar, 2021 40 commits
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Christian König authored
Separate the drm_mm_node walking from the actual handling. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Oak Zeng <Oak.Zeng@amd.com> Tested-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Arunpravin <Arunpravin.PaneerSelvam@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Separate the drm_mm_node walking from the actual handling. Signed-off-by:
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Christian König authored
Separate the drm_mm_node walking from the actual handling. Signed-off-by:
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Christian König authored
Allows to walk over the drm_mm nodes in a TTM resource object. v2: squash in fix from Felix Signed-off-by:
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Lijo Lazar authored
Cleanup pdb0 bo before bo_fini gets called Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Hawking Zhang authored
driver needs to query umc_info_v3_3 for ecc capability in sienna_cichlid Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Hawking Zhang authored
new member introduced in umc_info v3_3 to indicate ECC capability Signed-off-by:
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Oak Zeng authored
1. make function mmhub_v1_7_setup_vm_pt_regs static 2. indent a if statement Signed-off-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Oak Zeng authored
ioremap_cache is not supported on some architecture such as s390. Put the codes into a #ifdef to fix some compile error reported by test robot. v2: squash in non-x86 fix Signed-off-by:
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Harish Kasiviswanathan authored
This reverts commit 73bf5cad. Fixed in newer firmware Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
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Felix Kuehling authored
Using 'imply AMD_IOMMU_V2' does not guarantee that the driver can link against the exported functions. If the GPU driver is built-in but the IOMMU driver is a loadable module, the kfd_iommu.c file is indeed built but does not work: x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_bind_process_to_device': kfd_iommu.c:(.text+0x516): undefined reference to `amd_iommu_bind_pasid' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_unbind_process': kfd_iommu.c:(.text+0x691): undefined reference to `amd_iommu_unbind_pasid' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_suspend': kfd_iommu.c:(.text+0x966): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0x97f): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0x9a4): undefined reference to `amd_iommu_free_device' x86_64-linux-ld: drivers/gpu/drm/amd/amdkfd/kfd_iommu.o: in function `kfd_iommu_resume': kfd_iommu.c:(.text+0xa9a): undefined reference to `amd_iommu_init_device' x86_64-linux-ld: kfd_iommu.c:(.text+0xadc): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xaff): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xc72): undefined reference to `amd_iommu_bind_pasid' x86_64-linux-ld: kfd_iommu.c:(.text+0xe08): undefined reference to `amd_iommu_set_invalidate_ctx_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xe26): undefined reference to `amd_iommu_set_invalid_ppr_cb' x86_64-linux-ld: kfd_iommu.c:(.text+0xe42): undefined reference to `amd_iommu_free_device' Use IS_REACHABLE to only build IOMMU-V2 support if the amd_iommu symbols are reachable by the amdkfd driver. Output a warning if they are not, because that may not be what the user was expecting. Fixes: 64d1c3a4 ("drm/amdkfd: Centralize IOMMUv2 code and make it conditional") Reported-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Sebastian Andrzej Siewior authored
gfx_v8_0_parse_sq_irq() is using in_task() to distinguish if it is invoked from a workqueue worker or directly from the interrupt handler. The usage of in_interrupt() in drivers is phased out and Linus clearly requested that code which changes behaviour depending on context should either be separated or the context be conveyed in an argument passed by the caller, which usually knows the context. gfx_v8_0_parse_sq_irq() is invoked directly either from a worker or from the interrupt service routine. The worker is only bypassed if the worker is already busy. Add an argument `from_wq' to gfx_v8_0_parse_sq_irq() which is true if invoked from the worker. Reviewed-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
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Sebastian Andrzej Siewior authored
gfx_v9_0_get_gpu_clock_counter() acquires a mutex_t lock and is the only caller of gfx_v9_0_kiq_read_clock(). If it safe to acquire a mutex_t then gfx_v9_0_get_gpu_clock_counter() is always invoked from preemptible context. Remove in_interrupt() because it superfluous as it will always return false. Reviewed-by:
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Sebastian Andrzej Siewior authored
The usage of in_interrupt() in gmc_v*_process_interrupt() is intended to use a different code path if invoked from the interrupt handler vs invoked from the workqueue. The usage of in_interrupt() in drivers is phased out and Linus clearly requested that code which changes behaviour depending on context should either be separated or the context be conveyed in an argument passed by the caller, which usually knows the context. gmc_v*_process_interrupt() is invoked via the ->process() callback from amdgpu_ih_process() which in turn is invoked either from amdgpu_irq_handler() (the interrupt handler) or from amdgpu_irq_handle_*() which is a workqueue. amdgpu_irq::ih is always processed from the interrupt handler, the other three struct amdgpu_ih_ring members are processed from a workqueue. Replace the in_interrupt() check with a comparison against adev->irq.ih. A similar check is already done to check if the ih pointer is from ih_soft. Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in a drm debug message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
For consistency with SMU10. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Was added in newer versions of the firmware. Add support for it. v2: return an error in SMU error, drop needless break. Reviewed-by:
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Kenneth Feng authored
On some Intel platforms, audio noise can be detected due to high pcie speed switch latency. This patch leaverages ppfeaturemask to fix to the highest pcie speed then disable pcie switching. v2: coding style fix Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Jinzhou Su authored
update secure display TA header file. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Feifei Xu authored
In gpu reset, XGMI TA unload will cause gpu hang. Skip it on A+A aldebaran. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Anson Jacob authored
'drm/drm_hdcp.h' included in 'amdgpu_dm.c' is duplicated. Reported-by:
Zhang Yunkai <zhang.yunkai@zte.com.cn> Signed-off-by:
Anson Jacob <Anson.Jacob@amd.com> Acked-by:
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Anson Jacob authored
This reverts commit 51713e4e. The duplicate from #79 should be removed instead. Signed-off-by:
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shaoyunl authored
SMU introduce the new interface to enable light Secondary Bus Reset mode, driver enable it on passthrough + XGMI configuration Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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shaoyunl authored
This new MSG provide the interface for driver to enable/disable the Light Secondary Bus Reset support from SMU. When enabled, SMU will only do minimum NBIO response to the SBR request and leave the real HW reset to be handled by driver later. When disabled (default state),SMU will pass the request to PSP for a HW reset Signed-off-by:
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shaoyunl authored
Read eeprom through SMU doesn't works stable on XGMI reset during test. skip it for now Signed-off-by:
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Qingqing Zhuo authored
[Why] CONFIG_DRM_AMD_DC_DCN3_0 has been folded into CONFIG_DRM_AMD_DC_DCN and is not needed. [How] Drop CONFIG_DRM_AMD_DC_DCN3_0. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Alex Deucher authored
Need to check the module variant as well. Acked-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Christian König authored
Silence static checker warning. Signed-off-by:
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Christian König authored
When AGP is compiled as module radeon must be compiled as module as well. Signed-off-by:
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Christian König authored
Otherwise we will run into a NULL ptr deref. Signed-off-by:
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Evan Quan authored
The "/ 10" should be applied to the right-hand operand instead of the left-hand one. Signed-off-by:
Georgios Toptsidis <gtoptsid@gmail.com> Reviewed-by:
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shaoyunl authored
This recent change introduce SDMA interrupt info printing with irq->process function. These functions do not require a set function to enable/disable the irq Signed-off-by:
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Kenneth Feng authored
Currently the pcie dpm has two problems. 1. Only the high dpm level speed/width can be overrided if the requested values are out of the pcie capability. 2. The high dpm level is always overrided though sometimes it's not necesarry. Signed-off-by:
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Jonathan Kim authored
Add IH function to allow caller to wait until ring entries are processed until the checkpoint write pointer. This will be primarily used by HMM to drain pending page fault interrupts before memory unmap to prevent HMM from handling stale interrupts. Suggested-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] DC needs to communicate with PM FW through GPU memory. In order to do so we need to be able to allocate memory from within DC. [How] Call amdgpu_bo_create_kernel to allocate GPU memory and use a list in amdgpu_display_manager to track our allocations so we can clean them up later. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Zhan Liu authored
[Why] For DGPU Navi, the wm_table.nv_entries are used. These entires are not populated for DCN301 Vangogh APU, but instead wm_table.entries are. [How] Use DCN21 Renoir style wm calculations. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Nirmoy Das authored
FB BO should not be ttm_bo_type_kernel type and amdgpufb_create_pinned_object() pins the FB BO anyway. Signed-off-by:
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shaoyunl authored
In passthrough configuration, hypervisior will trigger the SBR(Secondary bus reset) to the devices without sync to each other. This could cause device hang since for XGMI configuration, all the devices within the hive need to be reset at a limit time slot. This serial of patches try to solve this issue by co-operate with new SMU which will only do minimum house keeping to response the SBR request but don't do the real reset job and leave it to driver. Driver need to do the whole sw init and minimum HW init to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at the same time Signed-off-by:
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shaoyunl authored
The gmc.xgmi.head list originally is designed for device list in the XGMI hive. Mix use it for reset purpose will prevent the reset function to adjust XGMI device list which is required in next change Signed-off-by:
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shaoyunl authored
The MQD might not be initialized duirng first init period if the device need to be reset druing probe. Driver need to proper init them in gpu recovery period Signed-off-by:
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