- 30 Aug, 2023 28 commits
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Lijo Lazar authored
Add a function to wait till bootloader has reached steady state. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Tested-by:
Alex Deucher <alexander.deucher@amd.com>
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Horace Chen authored
[What] Current SRIOV still using adev->clock.default_XX which gets from atomfirmware. But these fields are abandoned in atomfirmware long ago. Which may cause function to return a 0 value. [How] We don't need to check whether SR-IOV. For SR-IOV one-vf-mode, pm is enabled and VF is able to read dpm clock from pmfw, so we can use dpm clock interface directly. For multi-VF mode, VF pm is disabled, so driver can just react as pm disabled. One-vf-mode is introduced from GFX9 so it shall not have any backward compatibility issue. Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lijo Lazar authored
BACO dummy mode could be set under reset conditions and that affects framebuffer access. Check If baco dummy mode is set, unset it if so. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Alvin Lee authored
[Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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ChunTao Tso authored
[Why] If VBlank_nom is too small, it will cause VStartUP_Start smaller than VBackPorch + VSync width which is an invalid case for VStartUP_Start and where to send AS-SDP. [How] Setup a minimum value to VBlank_nom Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
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Reza Amini authored
[why] vstartup is calculated to be a large number. it works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [how] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by:
Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Ovidiu Bunea authored
[why] This Unit correction exposes a Replay corruption. [how] This reverts commit: commit dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Roll back unit conversion until Replay can fix their corruption. Fixes: dbd29029 ("drm/amd/display: Correct unit conversion for vstartup") Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] DMUB subsystem was continuing to use compile time offset calculation for register access. Switch this to runtime calculation to stay consistent with rest of DC code. To enable this, an additional interface init_reg_offsets() are added to DMUB's hw_funcs struct. Asics with runtime register offset calculation enabled shall populate this hook with a fn pointer that will invoke the necessary macros to calculate the offset. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Ian Chen authored
[Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Krunoslav Kovac authored
[WHY & HOW] PQ has a fixed range of 0-10,000 nits. Using 1=80 nits normalization, PQ should map to 1.0 for X=125.0 HW LUT used for interpolation does not have X=125 so it's interpolated. However, we cap Y to 1 for all X>=125. The closest larger HW point is 128. What we want is Y(128) such that interpolation through 125 gives 1.0. Such value is ~1.00256. Another change is to hardcode PQ table, we pretty much always have 1=80 normalization so the table can be static. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Tested-by:
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Krunoslav Kovac authored
[WHY & HOW] HW LUTs changed slightly in DCN3: 256 base+slope pairs were replaced by 257 bases. Code was still calculating all 256 base+slope and then creating 257th pt as last base + last slope. This was done in wrong format, and then "fixed" it by making the last two points the same thus making the last slope=0. However, this also created some precision problems near the end that are not visible but they do show up with capture cards. Solution is to calculate 257 and remove deltas since we no longer have those HW registers. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Export a debugfs file to report whether MALL cache is supported by the asic or not. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Srinivasan Shanmugam authored
The assignment of the else if and else branches is the same, so the else if here is redundant, hence removed it. Fixes the below: drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c:4664:8-10: WARNING: possible condition with no effect (if == else) Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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YiPeng Chai authored
Enable ras for mp0 v13_0_6 sriov Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following: WARNING: Possible repeated word: 'Fences' WARNING: Missing a blank line after declarations WARNING: braces {} are not necessary for single statement blocks WARNING: braces {} are not necessary for any arm of this statement WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: quoted string split across lines WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line Cc: Guchun Chen <guchun.chen@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following coccicheck: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:94:102-107: WARNING: conversion to bool not needed here drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:102:72-77: WARNING: conversion to bool not needed here Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Sierra authored
if hmm_range_get_pages returns EBUSY error during svm_range_validate_and_map, within the context of a page fault interrupt. This should retry through svm_range_restore_pages callback. Therefore we treat this as EAGAIN error instead, and defer it to restore pages fallback. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
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Samir Dhume authored
Powergating is handled in the host driver. Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
Samir Dhume <samir.dhume@amd.com> Signed-off-by:
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Lijo Lazar authored
Instead of maintaining a list per device, keep the reset handlers common per ASIC family. A pointer to the list of handlers is maintained in reset control. Signed-off-by:
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Asad Kamal authored
Add critical temperature message support func for smu v13.0.6 and expose critical temperature as part of hw mon attributes for GC v9.4.3 v2: Added comment for pmfw version requirement & move the check to get_thermal_temperature_range function Signed-off-by:
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Asad Kamal authored
Update PMFW interface headers for updated metrics table and critical temperature message Signed-off-by:
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Le Ma authored
Several new fields are exposed in gc_info v2_1 Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
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Le Ma authored
Mall info v2 is introduced in ip discovery Signed-off-by:
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Candice Li authored
RAS EEPROM device is only supported on dGPU platform for smu v13_0_6. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Lijo Lazar authored
7957ec80 ("drm/amdgpu: Add FRU sysfs nodes only if needed") moved the documentation for some of the sysfs nodes to amdgpu_fru_eeprom.c. Update the documentation accordingly. Signed-off-by:
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Chen Jiahao authored
Using kmemdup() helper function rather than implementing it again with kmalloc() + memcpy(), which improves the code readability. Signed-off-by:
Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by:
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Bokun Zhang authored
- There is a DPM issue where if DC is not present, FCLK will stay at low level. We need to send a SMU message to configure the DPM - Reuse smu_v13_0_notify_display_change() for this purpose Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Bokun Zhang <bokun.zhang@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
- Setup replay config on device init. - Enable replay if feature is enabled (prioritize replay over PSR, since it can be enabled in more usecases) - Add debug masks to enable replay on supported ASICs Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 25 Aug, 2023 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2023-08-24' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Fix TLB invalidation (Alan) - Fix Display HPD polling (Imre) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZOdOP31OE/Cf1ojo@intel.com
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- 24 Aug, 2023 7 commits
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-08-24' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * gpuva: Cleanups * kunit: Documentation fixes * nouveau: * UAPI: Avoid implicit NO_PREFETCH flag * Scheduler fixes * Fix remap * ttm: Fix type conversion in tests Signed-off-by:
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Danilo Krummrich authored
The prev pointer in __drm_gpuva_sm_map() was used to implement automatic merging of mappings. Since automatic merging did not make its way upstream, remove this leftover. Fixes: e6303f32 ("drm: manager to keep track of GPUs VA mappings") Signed-off-by:
Danilo Krummrich <dakr@redhat.com> Reviewed-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/tests/drm_kunit_helpers.c:172: warning: expecting prototype for drm_kunit_helper_context_alloc(). Prototype was for drm_kunit_helper_acquire_ctx_alloc() instead Signed-off-by:
Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230824073710.2677348-10-lee@kernel.org Link: https://lore.kernel.org/r/20230824073710.2677348-14-lee@kernel.org [mripard: Squashed the two patches together] Signed-off-by:
Maxime Ripard <mripard@kernel.org>
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Danilo Krummrich authored
Currently, NO_PREFETCH is passed implicitly through drm_nouveau_gem_pushbuf_push::length and drm_nouveau_exec_push::va_len. Since this is a direct representation of how the HW is programmed it isn't really future proof for a uAPI. Hence, fix this up for the new uAPI and split up the va_len field of struct drm_nouveau_exec_push, such that we keep 32bit for va_len and 32bit for flags. For drm_nouveau_gem_pushbuf_push::length at least provide NOUVEAU_GEM_PUSHBUF_NO_PREFETCH to indicate the bit shift. While at it, fix up nv50_dma_push() as well, such that the caller doesn't need to encode the NO_PREFETCH flag into the length parameter. Signed-off-by:
Faith Ekstrand <faith.ekstrand@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230823181746.3446-1-dakr@redhat.com
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Danilo Krummrich authored
Transfer the region pointer of a uvma to the new uvma(s) on re-map to prevent potential shader faults when the re-mapped uvma(s) are unmapped. Signed-off-by:
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Danilo Krummrich authored
If a sched job depends on a dma-fence from a job from the same GPU scheduler instance, but a different scheduler entity, the GPU scheduler does only wait for the particular job to be scheduled, rather than for the job to fully complete. This is due to the GPU scheduler assuming that there is a scheduler instance per ring. However, the current implementation, in order to avoid arbitrary amounts of kthreads, has a single scheduler instance while scheduler entities represent rings. As a workaround, set the DRM_SCHED_FENCE_DONT_PIPELINE for all out-fences in order to force the scheduler to wait for full job completion for dependent jobs from different entities and same scheduler instance. There is some work in progress [1] to address the issues of firmware schedulers; once it is in-tree the scheduler topology in Nouveau should be re-worked accordingly. [1] https://lore.kernel.org/dri-devel/20230801205103.627779-1-matthew.brost@intel.com/Signed-off-by:
Faith Ekstrand <faith.ekstrand@collaboralcom> Link: https://patchwork.freedesktop.org/patch/msgid/20230811010632.2473-1-dakr@redhat.com
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
Updates for v6.6, which includes a backmerge of msm-fixes to avoid conficts. Core: - SM6125 MDSS support DPU: - SM6125 DPU support - Added subblocks to display snapshot - Use UBWC data from MDSS driver rather than duplicating it - dpu_core_perf cleanup DSI: - Enabled burst mode to fix CMD mode panels - Runtime PM support - refgen regulator support DSI PHY: - SM6125 support in 14nm DSI PHY driver GPU: - Rework GPU identification to prepare for a7xx, and other a7xx prep - Cleanups and fixes - Disallow legacy relocs on a6xx and newer - a690: switch to using a660_gmu.bin fw as this is what we have in linux-firmware and we see no evidence that it should be different from other a660 family (a6xx subgen 4) devices - Submit overhead opts, 1.6x faster for NO_IMPLICIT_SYNC commits with 100 BOs to 2.5x faster for 1000 BOs Signed-off-by:
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- 23 Aug, 2023 3 commits
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Dave Airlie authored
Linux 6.5-rc7 This is needed for the CI stuff and the msm pull has fixes in it. Signed-off-by: -
Imre Deak authored
After the commit in the Fixes: line below, HPD polling stopped working on i915, since after that change calling drm_kms_helper_poll_enable() doesn't restart drm_mode_config::output_poll_work if the work was stopped (no connectors needing polling) and enabling polling for a connector (during runtime suspend or detecting an HPD IRQ storm). After the above change calling drm_kms_helper_poll_enable() is a nop after it's been called already and polling for some connectors was disabled/re-enabled. Fix this by calling drm_kms_helper_poll_reschedule() added in the previous patch instead, which reschedules the work whenever expected. Fixes: d33a54e3 ("drm/probe_helper: sort out poll_running vs poll_enabled") CC: stable@vger.kernel.org # 6.4+ Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230822113015.41224-2-imre.deak@intel.com (cherry picked from commit 50452f2f) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Imre Deak authored
Add a helper to reschedule drm_mode_config::output_poll_work after polling has been enabled for a connector (and needing a reschedule, since previously polling was disabled for all connectors and hence output_poll_work was not running). This is needed by the next patch fixing HPD polling on i915. CC: stable@vger.kernel.org # 6.4+ Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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- 22 Aug, 2023 1 commit
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Alan Previn authored
When getting the next gt's seqno to be stored into an objects mm.tlb[gt_id] array, fix the retrieval code to get it from the correct gt instead of the same one. Fixes: d6c531ab ("drm/i915: Invalidate the TLBs on each GT") Signed-off-by:
Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230814182449.1060747-1-alan.previn.teres.alexis@intel.com (cherry picked from commit 90b8ad13) Signed-off-by:
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