- 27 Sep, 2021 20 commits
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Konrad Dybcio authored
Add SDHCI1/2 nodes for eMMC and uSD card respectively. Do note that most SM6350 devices seem to come with UFS. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Replaced SM6350_CX with its constant value] Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org
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Konrad Dybcio authored
Add RPMHPD node, its OPP table and BCM voter to prepare for performance level voting. Signed-off-by:
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Konrad Dybcio authored
Add a node for the PRNG to enable hw-accelerated pseudo-random number generation. Signed-off-by:
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Konrad Dybcio authored
Add a node for SPMI to allow for communication with on-board PMICs. Signed-off-by:
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Konrad Dybcio authored
Add a node for AOSS_QMP in preparation for remote processor enablement. Signed-off-by:
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Konrad Dybcio authored
Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by:
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Konrad Dybcio authored
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by:
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Konrad Dybcio authored
Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and SC7180 IP, so no additional code porting is required. Acked-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by:
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Konrad Dybcio authored
Add and configure GCC node to allow for referencing GCC-controlled clocks in other nodes. Reviewed-by:
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Konrad Dybcio authored
Add RPMHCC node to allow for referencing RPMH-controlled clocks in other nodes. Reviewed-by:
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Konrad Dybcio authored
Add a node for LLCC with SM6350-specific compatible. Acked-by:
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Konrad Dybcio authored
Add a base DT for SM6350 SoC Signed-off-by:
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Konrad Dybcio authored
Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350). Reviewed-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8350 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8250 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8150 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SDM845 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7280 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
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Sibi Sankar authored
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7180 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
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- 24 Sep, 2021 17 commits
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Douglas Anderson authored
The commit 82ea7d41 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") and the commit be0416a3 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") passed each other in the tubes that make up the Internet. Despite the fact the patches didn't cause a merge conflict, they need to account for each other. Do that. Fixes: 82ea7d41 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") Fixes: be0416a3 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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AngeloGioacchino Del Regno authored
All smartphones of this platform are equipped with a WCD9335 audio codec, getting its MCLK from PM8998 gpio13: add this clock to DT. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
All of the machines of the Sony Yoshino platform are equipped with two cameras, sharing the same regulators configuration. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add configuration for the LAB and IBB regulators (in boost mode): this platform has smartphones with three different display sizes, hence different displays requiring different voltage. The common configuration parameters have been put in the common device-tree, while specific voltage specs and soft-start-us are variant specific, so they have been put into the machine specific dts file. Signed-off-by:
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AngeloGioacchino Del Regno authored
All smartphones in the Sony Yoshino platforms have got a simple vibrator hooked to a GPIO: add support for that and add its own pin configuration. Signed-off-by:
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AngeloGioacchino Del Regno authored
This platform uses the WCN3990 Bluetooth chip, reachable on UART-3. Signed-off-by:
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AngeloGioacchino Del Regno authored
All of the devices in the Sony Yoshino platform are using a Synaptics RMI4-compatible touch IC with identical pins and supplies: enable the I2C-5 bus and add the rmi4-i2c node along with the required pin configurations. Signed-off-by:
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AngeloGioacchino Del Regno authored
This commit introduces support for the Sony Yoshino platform, using the MSM8998 SoC, including: - Sony Xperia XZ1 (codename Poplar), - Sony Xperia XZ1 Compact (codename Lilac), - Sony Xperia XZ Premium (codename Maple). All of the three aforementioned smartphones are sharing a 99% equal board configuration, with very small differences between each other, which is the reason for the introduction of a common msm8998-sony-xperia-yoshino DT. This base configuration includes regulators and project-wide pin configurations and it's made to boot to a serial console. Signed-off-by:
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Shawn Guo authored
It turns out that the pm660 PON is a GEN2 device. Update the compatible to "qcom,pm8998-pon" and add reboot mode support, so that devices can be rebooted into bootloader and recovery mode. Tested on Xiaomi Redmi Note 7 phone. While at it, drop the unnecessary newline between 'compatible' and 'reg' property. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Reviewed-by:
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Rajesh Patil authored
Add aliases for i2c and spi for sc7280 soc. Signed-off-by:
Rajesh Patil <rajpat@codeaurora.org> Reviewed-by:
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Roja Rani Yarubandi authored
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. Signed-off-by:
Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by:
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Rajesh Patil authored
Add bluetooth uart pin configuration for sc7280-idp. Signed-off-by:
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Roja Rani Yarubandi authored
Uart5 is treated as dedicated debug uart.Change the compatible as "qcom,geni-uart" in SoC DT to make it generic and later update it as "qcom,geni-debug-uart" in sc7280-idp Add interconnects and power-domains. Split the pinctrl functions and correct the gpio pins. Signed-off-by:
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Roja Rani Yarubandi authored
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. Signed-off-by:
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Rajesh Patil authored
Add spi-nor flash node and pinctrl configurations for the SC7280 IDP. Signed-off-by:
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Roja Rani Yarubandi authored
Add QSPI DT node and qspi_opp_table for SC7280 SoC. Move qspi_opp_table to / because SPI nodes assume any child node is a spi device and so we can't put the table underneath the spi controller. Signed-off-by:
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Fabio Estevam authored
dtc complains about the leading zeroes: arch/arm64/boot/dts/qcom/sm6125.dtsi:497.19-503.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f121000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:505.19-510.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f123000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:512.19-517.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f124000: unit name should not have leading 0 Remove them. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Martin Botka <martin.botka@somainline.org> Signed-off-by:
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- 23 Sep, 2021 1 commit
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Shaik Sajida Bhanu authored
The current drive strength values are not sufficient on non discrete boards and this leads to CRC errors during switching to HS400 enhanced strobe mode. Hardware simulation results on non discrete boards shows up that use the maximum drive strength values for data and command lines could helps in avoiding these CRC errors. So, update data and command line drive strength values to maximum. Signed-off-by:
Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-by:
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- 21 Sep, 2021 2 commits
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Sujit Kautkar authored
Enable the IPA node for LTE and skip for wifi-only SKUs Signed-off-by:
Sujit Kautkar <sujitka@chromium.org> Reviewed-by:
Alex Elder <elder@linaro.org> Signed-off-by:
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Stephan Gerhold authored
According to Documentation/devicetree/bindings/mmc/sdhci-msm.txt a SoC specific compatible should be used in addition to the IP version compatible, but for some reason it was never added for MSM8916. Add the "qcom,msm8916-sdhci" compatible additionally to make the device tree match the documented bindings. Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
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