- 25 Oct, 2019 40 commits
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Evan Quan authored
Those swSMU APIs used internally are moved to smu_internal.h while others are kept in amdgpu_smu.h. V2: give a better name smu_internal.h for the place to hold those internal APIs Signed-off-by:Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Acked-by:
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Jane Jian authored
Add mmsch part registers Signed-off-by:
Jane Jian <jane.jian@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] This workaround was put in dcn2 DMLv1, and now we need it in DMLv2. Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Eric Yang authored
[Why] Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A. Was not filled in. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Dmytro Laktyushkin authored
We are currently incorrectly processing avoid split at highest voltage level. Signed-off-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Sung Lee authored
[Why] In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP. This causes an issue on dc init where dcn2_1_soc which has been updated by update_bw_bounding_box gets put into dml->soc. As update_bw_bounding_box is currently incorrect for dcn2.1, this makes dml calculations fail due to incorrect parameters, leading to a crash on PnP. [How] Comment out update_bw_bounding_box call for now. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Reza Amini authored
[why] We want to use maximum space on display to show source [how] For Centered Mode: Replicate source as many times as possible to use maximum of display active space add borders. Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Lewis Huang authored
[Why] Signal is update to EDP when driver disable first encoder. The following encoder using SIGNAL_TYPE_EDP to handle other device. When encoder signal is HDMI, driver will detect it is dp and release phy. It cause hw hang. [How] Take signal type from link->connector_signal. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Noah Abradjian authored
[Why] * Clk Mgr DTO update point did not cover all needed updates, as it included a check for plane_state which does not exist yet when the updater is called on driver startup * This resulted in another update path in the pipe programming sequence, based on a dppclk update flag * However, this alternate path allowed for stray DTO updates, some of which would occur in the wrong order during dppclk lowering and cause underflow [How] * Remove plane_state check and use of plane_res.dpp->inst, getting rid of sequence dependencies (this results in extra dto programming for unused pipes but that doesn't cause issues and is a small cost) * Allow DTOs to be updated even if global clock is equal, to account for edge case exposed by diags tests * Remove update_dpp_dto call in pipe programming sequence (leave update to dppclk_control there, as that update is necessary and shouldn't occur in clk mgr) * Remove call to optimize_bandwidth when committing state, as it is not needed and resulted in sporadic underflows even with other fixes in place Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
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Krunoslav Kovac authored
[Why&How] BT.2390 EETF is used for tone mapping/range reduction. Say display is 0.1 - 500 nits. The problematic case is when content is 0-400. We apply EETF because 0<0.1 so we need to reduce the range by 0.1. In the commit, we ignore the bottom range. Most displays map 0 to min and then have a ramp to 0.1, so sending 0.1 is actually >0.1. Furthermode, HW that uses 3D LUT also assumes min=0. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Eric Yang authored
[Why] SMU does not keep the wm table across S3, S4, need to re-send the table. Also defer sending the cable to after DCN bave initialized [How] Send table at end of init hw Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Jun Lei authored
[why] A display that supports DRR can never really be considered "synchronized" with any other display because we can dynamically enable DRR (i.e. without modeset). this will cause their relative CRTC positions to drift and lose sync. this will disrupt features such as MCLK switching that assume and depend on their permanent alignment (that can only change with modeset) [how] check for ignore_msa in stream when considered synchronizability this ignore_msa is basically actually implemented as "supports drr" Signed-off-by:
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Anthony Koo authored
[Why] When aux engine acquire fails, we missed populating the operation_result that describes the failure reason. [How] Set operation_result to new type: AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE in the case aux engine acquire has failed. Signed-off-by:
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Michael Strauss authored
[WHY] force_single_disp_pipe_split is a debug flag for use on DCN1 but isn't necessary otherwise as DCN2+ splits by default Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Michael Strauss authored
[WHY] i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles The call is expected to fail in DVI-D case but pass in HDMI case Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D [HOW] Retry i2c_read to ensure failed result is valid Signed-off-by:
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Yogesh Mohan Marimuthu authored
[Why] The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are initialized at index 6. Due to this mismatch, if monitor is attached to port using TRANSMITTER_UNIPHY_G then the monitor blanks out. [How] add function map_transmitter_id_to_phy_instance() and use the function to map enum transmitter to link regs. Signed-off-by:
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by:
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Jun Lei authored
[why] SLT tests require that diag can drive eDP even if nothing is connected, this is not typical production use case, so we need to add flag [how] add flag, and this flag supercedes "should destroy" logic Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
These are specific to dcn21 and should not be increased for reuse on other asics. Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] vm should be enabled by default for rn to get right dml. Signed-off-by:
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Aidan Yang authored
[why] There's a use case for inverted gamma and it's been confirmed that negative slopes are ok. [how] Remove code for blocking non-monotonically increasing gamma Signed-off-by:
Aidan Yang <Aidan.Yang@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] NV12 has lower min dcfclk [How] Add update in update_bounding_box Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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Paul Hsieh authored
[Why] On some systems, we need to check the dcn version in runtime system, not in compile time. [How] Stub in dcn version parameter to find_first_free_audio Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] DML is incorrectly initialized with 4 pipes on 3 pipe configs RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display) [HOW] Set correct number of DPP/OTGs for dml init to generate correct DPP topology Double RequiredDPPCLK after clock is halved for pipe split and find_secondary_pipe fails to fix underflow Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
This value will be needed by dml and therefore should be externally accessible. Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Dmytro Laktyushkin authored
One of odm variables was not initialized in dml. Signed-off-by:
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Dmytro Laktyushkin authored
Split a large function into smaller, reusable chunks. Signed-off-by:
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Anthony Koo authored
[Why] In diags environment we are not programming the DPP DTO correctly. [How] Populate the dpp refclk in dccg so it can be used to correctly program DPP DTO. Signed-off-by:
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Roman Li authored
[Why] PSR (Panel Self-Refresh) is a power-saving feature for eDP panels. The feature has support in DMCU (Display MicroController Unit). DMCU/driver communication is implemented in DC. DM can use existing DC PSR interface to use PSR feature. [How] - Read psr caps via dpcd - Send vsc infoframe if panel supports psr - Disable psr before h/w programming (FULL_UPDATE) - Enable psr after h/w programming - Disable psr for fb console Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Roman Li authored
[Why] For upcoming PSR stupport it's useful to have debug entry to verify psr state. [How] - Enable psr dc api for Linux - Add psr_state file to eDP connector debugfs usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state Signed-off-by:
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Aric Cyr authored
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Dmytro Laktyushkin authored
Commit hints are unnecessary after front end programming redesign. Signed-off-by:
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Jordan Lazare authored
[Why] For loop below the assert already checks for the number of instances to create. ASSERT is meaningless and causing spam. [How] dd Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Aidan Yang authored
[why] Optimized gamma22 assumes fixed point distribution which is not true for eetf true. [how] Use long calculation for eetf. Signed-off-by:
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Yongqiang Sun authored
[Why] System hang during S0i3 if DP only connected due to clk is disabled when doing link training. During S0i3, clk is disabled while the clk state is updated when ini_hw called, and at the moment clk is still disabled which indicating a wrong state for next time trying to enable clk. [How] Add an unknown state and initialize it during int_hw, make sure enable clk command be sent to smu. Signed-off-by:
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Jun Lei authored
[why] Hard to determine if pipe combine is done with MPC or ODM [how] Add new visual confirm type, this will mark each MPCC tree with a different color Signed-off-by:
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Jun Lei authored
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