- 06 Jun, 2022 1 commit
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José Roberto de Souza authored
This workaround brings some regressions to DG2 and if really necessary for DG2 an alternative workaround will be implemented. BSpec: 54077 Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220602201730.199418-1-jose.souza@intel.com
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- 03 Jun, 2022 2 commits
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Jani Nikula authored
Split out audio registers to a header of its own to reduce the size of i915_reg.h. TODO: Remove direct audio register access from intel_ddi.c. However, unification of audio get config is cumbersome due to the audio enable bit being in the DP or HDMI registers on older platforms. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Balasubramani Vivekanandan authored
Voltage swing table updated for eDP HBR3 Bspec: 49291 Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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- 01 Jun, 2022 7 commits
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Ville Syrjälä authored
Some machines declare DRRS type = seamless, DRRS = no, DMRRS = yes. I *think* DMRRS stands for "dynamcic media refresh rate", and I suspect the way it's meant to work is that it lets the driver switch refresh rates to match the frame rate for media playback. Obviously for us all that kind of policy stuff is entirely up to userspace, so the only thing we may do is make the extra refresh rate(s) available. So let's treat this case as just static DRRS for now. In the future We might want to differentiate the "seamless w/ downclocking" vs. "seamless w/o downclocking" cases so that we could do seamless refresh rate changes for systems that only claim to support DMRRS. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125Acked-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-7-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Add a bunch of new struff we're missing in various BDB blocks. TODO: Bunch of these might actually need to be taken into use... v2: s/lfp_features/lfp_power/features/ (Jani) Reviewed-by:
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Ville Syrjälä authored
Fix various typos around "aggressiveness". Note that the VBT spec also sometimes missspells it as "agressiveness" so I guess that's where some of the typos came from. Reviewed-by:
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Ville Syrjälä authored
It seem that when dealing with VRR capable eDP panels we need to accept fixed modes with variable vblank length (which is what VRR varies dynamically). Typically the preferred mode seems to be a non-VRR more (lowish dotclock/refresh rate + short vblank). We also have examples where it looks like even the hblank length is a bit different between the preferred mode vs. VRR mode(s). So let's just accept anything that has matching hdisp+vdisp+flags. v2: Document that is_alt_drrs_mode() is a subset of is_alt_vrr_mode() (Jani) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125Reviewed-by:
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Ville Syrjälä authored
To help with debugging DRRS/VRR panel init let's dump out all the fixed modes we rejected for whatever reason. Reviewed-by:
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Ville Syrjälä authored
VBT seems to have an extra flag for VRR vs. not. Let's consult that for eDP panels. Reviewed-by:
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Jani Nikula authored
Avoid bringing the entire machine down even if there's a bug that shouldn't happen, but won't corrupt the system either. Log them loudly and limp on. Signed-off-by:
Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531162527.1062319-1-jani.nikula@intel.com
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- 31 May, 2022 10 commits
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Ville Syrjälä authored
No idea why the DG2 PLL DP link frequency calculation is allowing a non-exact match. That makes no sense so get rid of it. Signed-off-by:
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Ville Syrjälä authored
Don't see a real reson not to check hw.active and hw.enable in intel_pipe_config_compare(). We do have some checks for them at a higher level, but I think better check them also in intel_pipe_config_compare() in case something else doesn't do a thorough enough job. Also shuffle the mst_master_transcoder check next to the cpu_transcoder check for a bit of consistency. Signed-off-by:
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Ville Syrjälä authored
Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs so we know more about what has happened during the modeset state computation. Also tweak the connector bpp debug message a bit to make it less confusing. Signed-off-by:
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Ville Syrjälä authored
Rename some of the 'pipe_config's to the more modern 'crtc_state'. Signed-off-by:
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Ville Syrjälä authored
Use the state+crtc calling convention for intel_modeset_pipe_config() and othere related functions. Many of these need the full atomic state anyway so passing it all the way through is just nicer than having to worry about whether it can actually be extracted from eg. the crtc state passed in. Signed-off-by:
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Ville Syrjälä authored
Deduplicate the drm_rect comparisons. We also drop the redundant pch_pfit.enabled check since the pch_pfit.dst rectanble will be zeroed anyway when the pfit is not enabled. v2: Document why we drop the enabled check (Jani) Signed-off-by:
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Ville Syrjälä authored
Deduplicate the crtc_ timings comparisons. Signed-off-by:
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Ville Syrjälä authored
The debugs in lower level DPLL code don't really provide any useful extra information AFAICS. Better just streamline the code and just put the necessary debugs (to identify at which step the modeset failed) into the higher level code. In addition we'll get the full state dump as well, which should hopefully have enough information to figure out what went wrong. Reviewed-by:
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Ville Syrjälä authored
Split the DPLL state computation into a separate function from the current .get_dplls() which currently serves a dual duty by also reserving the shared DPLLs. v2: s/false/-EINVAL/ (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Vivek Kasireddy authored
Commit 30e114ef ("drm/i915/tc: Check for DP-alt, legacy sinks before taking PHY ownership") defaults any disconnected Type-C ports to TBT-alt mode which presents a problem (which could most likely result in a system hang) when userspace forces a modeset on a Type-C port that is wired for legacy HDMI. The following warning is seen when Weston forces a modeset on a disconnected legacy Type-C port (HDMI) on a TGL based Gigabyte system: (https://www.gigabyte.com/Mini-PcBarebone/GB-BSi3-1115G4-rev-10#ov) Missing case (clock == 173000) WARNING: CPU: 1 PID: 438 at drivers/gpu/drm/i915/display/intel_ddi.c:245 icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915] CPU: 1 PID: 438 Comm: kworker/u8:3 Tainted: G U W E 5.18.0-rc5-drm-tip+ #20 Hardware name: GIGABYTE GB-BSi3-1115G4/GB-BSi3-1115G4, BIOS F9 10/16/2021 Workqueue: i915_modeset intel_atomic_commit_work [i915] RIP: 0010:icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915] Code: 74 6c 7f 10 81 fd d0 78 02 00 74 6d 81 fd b0 1e 04 00 74 70 48 63 d5 48 c7 c6 c0 7b ab c0 48 c7 c7 20 75 ab c0 e8 b8 b5 c1 f0 <0f> 0b 45 31 ed e9 fb fe ff ff 49 63 d5 48 c7 c6 80 7b ab c0 48 c7 RSP: 0018:ffff8882522c78f0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000000 RDX: 0000000000000027 RSI: 0000000000000004 RDI: ffffed104a458f10 RBP: 0000000000011558 R08: ffffffffb078de4e R09: ffff888269ca748b R10: ffffed104d394e91 R11: 0000000000000000 R12: ffff888255a318f8 R13: 0000000000000002 R14: ffff888255a30000 R15: ffff88823ef00348 FS: 0000000000000000(0000) GS:ffff888269c80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fd7afa42000 CR3: 0000000255c02004 CR4: 00000000007706e0 PKRU: 55555554 Call Trace: <TASK> intel_ddi_pre_enable.cold+0x96/0x5bf [i915] intel_encoders_pre_enable+0x10e/0x140 [i915] hsw_crtc_enable+0x207/0x99d [i915] ? ilk_crtc_enable.cold+0x2a/0x2a [i915] ? prepare_to_wait_exclusive+0x120/0x120 intel_enable_crtc+0x9a/0xf0 [i915] skl_commit_modeset_enables+0x466/0x820 [i915] ? intel_commit_modeset_enables+0xd0/0xd0 [i915] ? intel_mbus_dbox_update+0x1ed/0x250 [i915] intel_atomic_commit_tail+0xf2d/0x3040 [i915] _raw_spin_lock_irqsave+0x87/0xe0 _raw_read_unlock_irqrestore+0x40/0x40 __update_load_avg_cfs_rq+0x70/0x5c0 __i915_sw_fence_complete+0x85/0x3b0 [i915] ? intel_get_crtc_new_encoder+0x190/0x190 [i915] ? sysvec_irq_work+0x13/0x90 ? asm_sysvec_irq_work+0x12/0x20 ? _raw_spin_lock_irq+0x82/0xd0 ? read_word_at_a_time+0xe/0x20 ? process_one_work+0x393/0x690 process_one_work+0x393/0x690 worker_thread+0x2b7/0x620 ? process_one_work+0x690/0x690 kthread+0x15a/0x190 ? kthread_complete_and_exit+0x20/0x20 ret_from_fork+0x1f/0x30 Continuing with the modeset without setting the DDI clock results in more warnings and eventually a system hang. This does not seem to happen with disconnected legacy or DP-alt DP ports because the clock rate defaults to 162000 (which is a valid TBT clock) during the link training process. Therefore, to fix this issue, this patch avoids setting disconnected Type-C legacy ports to TBT-alt mode which prevents the selection of TBT PLL when a modeset is forced. v2: (Imre) - Retain the check for legacy hotplug live status to account for incorrect VBTs. Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Vivek Kasireddy <vivek.kasireddy@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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- 27 May, 2022 14 commits
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Ville Syrjälä authored
Apparently when the VBT panel_type==0xff we should trawl through the PNPID table and check for a match against the EDID. If a match is found the index gives us the panel_type. Tried to match the Windows behaviour here with first looking for an exact match, and if one isn't found we fall back to looking for a match w/o the mfg year/week. v2: Rebase due to vlv_dsi changes v3: Adjust to .get_panel_type() vfunc Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5545Reviewed-by:
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Ville Syrjälä authored
Move the panel specific VBT parsing to happen during the output probing stage. Needs to be done because the VBT parsing will need to look at the EDID to determine the correct panel_type on some machines. We split the parsed VBT data (i915->vbt) along the same boundary. For the moment we just hoist all the panel specific stuff into connector->panel.vbt since that seems like the most convenient place for eg. the backlight code. Note that we simply drop the drrs type check from intel_drrs_frontbuffer_update() since that operates on the whole device rather than a specific connector/encoder. But the check was just a micro optimization so removing it doesn't actually mattter for correctness. TODO: Lot's of cleanup to be done in the future. Eg. most of the DSI stuff could probably be eliminated entirely and just parsed on demand during DSI init. v2: Note the intel_drrs_frontbuffer_update() change Signed-off-by:
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Ville Syrjälä authored
Parsing the panel specific data (anything that depends on panel_type) from VBT is currently happening too early. Split the whole thing into global vs. panel specific parts so that we can start doing the panel specific parsing at a later time. v2: Clarify that this is about panel_type (Jani) Split out the leak checks (Jani) Reviewed-by: -
Ville Syrjälä authored
We use the "driver features" block for two different kinds of data: global data, and per panel data. Split the function into two parts along that line so that we can start doing the parsing in two different locations. Reviewed-by:
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Ville Syrjälä authored
Disable the delayed VDD off work during the eDP probe. If we never turn off the VDD then we can't violate the panel's power sequencing delays despite not having read them out yet from the VBT. This is mostly a belt+suspenders type of thing since the the timeout we'd use for the delayed work should be long enough that this won't normally happen. But I don't really like relying on timeouts for correctless so might as well make sure. Signed-off-by:
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Ville Syrjälä authored
During the eDP probe we may not yet know the panel_type used to index the VBT panel tables. So the initial eDP probe will have to be done without that, and thus we won't yet have the PPS delays from the VBT. Once the VBT has been fully parse we should reinit the PPS delays to make sure it's fully accounted for. Signed-off-by:
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Ville Syrjälä authored
Split the PPS init to something we do at the start of the eDP probe and a second part we do at the end. Signed-off-by:
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Ville Syrjälä authored
In order to do the panel VBT parsing after the EDID read (needed to determine panel_type from PNPID) we need to stash away the original BIOS programmed PPS delays so that we can consult them again when we reinit the PPS delays after the VBT parsing has been done. Signed-off-by:
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Ville Syrjälä authored
Skip QUIRK_INCREASE_T12_DELAY and the t11_t12 adjustment of the VBT PPS delays if we've not yet initialized them. Will be important later when the PPS delay init can happen before VBT parsing. Signed-off-by:
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Ville Syrjälä authored
Add a small helper that determines if the PPS delays have been initialized or not. Signed-off-by:
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Ville Syrjälä authored
Split each of the hw/vbt/spec PPS delay initialization into separate functions to make the whole thing less cluttered. Signed-off-by:
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Ville Syrjälä authored
We have the same "override eDP VBT bpp with the current bpp" code duplciated in two places. Extract it to a helper function. TODO: Having this in .get_config() is pretty ugly. Should probably try to move it somewhere else (setup_hw_state()/etc.)... Signed-off-by:
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Ville Syrjälä authored
Pass intel_connector instead of drm_connector to intel_vrr_is_capable(). Will result in less ugly casts. Signed-off-by:
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Balasubramani Vivekanandan authored
New updates to HDMI combo PHY voltage swing tables. Actually with this update (bspec updated on 08/17/2021), the values are reverted back to be same as icelake for HDMI combo PHY. Bspec: 49291 Signed-off-by:
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- 25 May, 2022 1 commit
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Vandita Kulkarni authored
This patch adds a fix to support 297MHz of dot clock by calculating the pll values using synopsis algorithm. This will help to support 4k@30 mode for HDMI monitors on DG2. v2: As per the algorithm, set MPLLB VCO range control bits to 3, in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt) v3: Fix typo. (Ankit) Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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- 24 May, 2022 1 commit
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Julia Lawall authored
Spelling mistakes (triple letters) in comments. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by:
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- 23 May, 2022 3 commits
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Imre Deak authored
Based on a bspec update the DMC firmware's flip queue handling events need to be disabled before enabling DC5/6. i915 doesn't use the flip queue feature atm, so disable it already after loading the firmware. This removes some overhead of the event handler which runs at a 1 kHz frequency. Bspec: 49193, 72486, 72487 v2: - Fix the DMC pipe A register offsets for GEN12. - Disable the events on DG2 only on pipe A..D . v3: (Lucas) - Add TODO: to clarify the disabling sequence on all D13+ - s/intel_dmc_has_fw_payload/has_dmc_id_fw/ - s/simple_flipq/flipq/ - s/_GEN12,_GEN13/TGL_,ADLP_/ - s/MAINDMC/DMC/ v4: - Only disable flip queues on TGL/DG2, as on other platforms the corresponding event handlers don't exist. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220521130808.637449-1-imre.deak@intel.com
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Ville Syrjälä authored
Give block_size()/block_offset() a "raw_" prefix since they both operate on the "raw" (as in not duplicated) BDB block contents. What actually spurred this was a conflict between intel_bios.c block_size() vs. block_size() from blkdev.h. That only happened to me on a custom tree where we somehow manage to include blkdev.h into intel_bios.c. But I think the rename makes sense anyway to clarify the purpose of these functions. Signed-off-by:
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Jani Nikula authored
The VBT send packet port selection was never updated for ICL+ where the 2nd link is on port B instead of port C as in VLV+ DSI. First, single link DSI needs to use the configured port instead of relying on the VBT sequence block port. Remove the hard-coded port C check here and make it generic. For reference, see commit f915084e ("drm/i915: Changes related to the sequence port no for") for the original VLV specific fix. Second, the sequence block port number is either 0 or 1, where 1 indicates the 2nd link. Remove the hard-coded port C here for 2nd link. (This could be a "find second set bit" on DSI ports, but just check the two possible options.) Third, sanity check the result with a warning to avoid a NULL pointer dereference. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5984 Cc: stable@vger.kernel.org # v4.19+ Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by:
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- 20 May, 2022 1 commit
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Dale B Stimson authored
Some dGfx pcode commands take additional sub-commands and parameters. Add a couple of helpers to help formatting these commands to improve code readability. v2: Fixed commit author (Rodrigo) v3: Function rename and convert to new uncore interface for pcode functions Remove unnecessary #define's (Andi) v4: Another function rename Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-3-tvrtko.ursulin@linux.intel.com
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