- 05 Jun, 2024 40 commits
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Fangzhi Zuo authored
IPX involvment proven to affect LT, causing link loss. Need to prevent IPX enabled in LT process in which link detect and set mode are main procedures that have LT taken place. Reviewed-by:
Roman Li <roman.li@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Fangzhi Zuo <jerry.zuo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jesse Zhang authored
idr_for_each_entry can ensure that mem is not empty during the loop. So don't need check mem again. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Lin.Cao authored
Flag "mes.ring.shced.ready" will be set as true after mes hw init and set as false when mes hw fini to avoid duplicate initialization. But hw fini will not be called when function level reset, which will cause mes hw init be skipped during FLR, which will leads to mapping legacy queue fail. Set this flag as false when post reset will fix this issue. Signed-off-by:
Lin.Cao <lincao12@amd.com> Acked-by:
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Daniel Sa authored
[Why] When performing P-State switching with Subvp on 8k (downscaled to 4k). corruption can be seen on the screen. MALL data was not being fetched from DC, and the system things there is more MALL space then what is actually available. [How] Read MALL size from dc caps. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Daniel Sa <daniel.sa@amd.com> Tested-by:
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Samson Tam authored
[Why] Missing check causes sequence error which results in chroma filter coefficients not being updated in certain modes when we display YUV video in fullscreen. This results in color corruption in video [How] Add back chroma_coef_mode check in dscl_set_scl_filter so that filter coefficients are calculated and updated when we have YUV surface Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Eric Huang authored
reset cause is requested by customer as additional info for gpu reset smi event. v2: integerate reset sources suggested by Lijo Lazar Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Frank Min authored
Update to latest changes. Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Frank Min authored
Set PTE_IS_PTE bit while PRT is enabled on gfx12. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Relja Vojvodic authored
why: optc_401_set_drr was using an old optc3 function to update vtotal min and max, causing crashes when disabling FAMS2 how: Updated dcn401 to point to opt401 function for vtotal updates. This version of the function has FAMS2 logic that allows for FAMS2 to be disabled. Reviewed-by:
Relja Vojvodic <relja.vojvodic@amd.com> Tested-by:
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Eric Huang authored
reset source or reset cause is very useful info for reset context, it will be used by events API. Suggested-by:
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Dillon Varone authored
[WHY&HOW] Improves on the SMU interface to explicitly declare P-State support. Reviewed-by:
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Alvin Lee authored
[Description] When checking the subvp type of the previous state we must pass in current_state to the interface instead of context otherwise we will get the wrong result. Reviewed-by:
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Bob Zhou authored
Check return value to avoid null pointer dereference. Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Bob Zhou authored
Check return value and conduct null pointer handling to avoid null pointer dereference. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Shane Xiao authored
This patch changes the implementation of AMDGPU_PTE_MTYPE_VG10, clear the bits before setting the new one. Suggested-by:
longlyao <Longlong.Yao@amd.com> Signed-off-by:
Shane Xiao <shane.xiao@amd.com> Reviewed-by:
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Jesse Zhang authored
kfd_create_vcrat_image_gpu itself checks the avail_size at the start. So the value of avail_size is at least VCRAT_SIZE_FOR_GPU(16384), minus struct crat_header(40UL) and struct crat_subtype_compute(40UL) it cannot be less than 0. Signed-off-by:
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Jesse Zhang authored
The expression caps | HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED and caps | HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED are always 1/true regardless of the values of its operand. Fixes: 9243240b ("drm/amdkfd: enable single alu ops for gfx12") Signed-off-by:
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Jesse Zhang authored
To fix the warning about unused value, remove the use_static and use the parameter is_static directly. Signed-off-by:
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Alvin Lee authored
[Description] Refactor code and move fpo_in_use into stream_status to avoid unexpected changes to previous dc_state (i.e., current_state). Since stream pointers are shared between current and new dc_states, updating parameters of one stream will update the other as well which causes unexpected behaviors (i.e., checking that fpo_in_use isn't set in previous state and set in the new state is invalid). To avoid incorrect updates to current_state, move the fpo_in_use flag into dc_stream_status since stream_status is owned by dc and are not shared between different dc_states. Reviewed-by:
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Alvin Lee authored
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by:
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Joan Lee authored
[why & how] Sometimes read DPCD return fail while result not retrieved yet. Add retries mechanism in Replay handle hpd irq to get real result. Reviewed-by:
Joan Lee <joan.lee@amd.com> Tested-by:
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Nicholas Susanto authored
[Why] When an eDP with high clock states is going into s0i3, stream_count is 0. This causes DML to not update the clks to the lowest state and blocking us to enter s0i3 since eDP is out of vmin. [How] When stream_count is 0, set all the clocks to the lowest state. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Jay Cornwall authored
A wavefront may deallocate its VGPRs at the end of a program while waiting for memory transactions to complete. If it subsequently receives a context save exception it will be unable to save, since this requires VGPRs. In this case the trap handler should terminate the wavefront. Fixes intermittent VM faults under context switching load. V2: Use S_ENDPGM instead of S_ENDPGM_SAVED for performance counters Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Lancelot Six <lancelot.six@amd.com> Signed-off-by:
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Chris Park authored
[Why] Page table definition increased up to 2MB. [How] Define new use case of page table for VA. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Joshua Aberback authored
[Why] Currently there's an issue on DCN401 that prevents oled eDP panels from being lit up that is still under investigation. To unblock dev work while investigating, we can work around the issue by skipping toggling the enablement of the backlight. [How] - new debug bit that will skip touching backlight enable DPCD for oled Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Chun-LiangChang authored
[Why] Add parameters for set_abm_event to enable varibright scaling. VariBright Scaling is a feature to refer to system states like 1. Power mode 2. Battery Life percent 3. FullScreen video 4. Backlight slider to adjust variBright strength to get low power or user experience. [How] Add parameters of set_abm_event for VB Scaling Reviewed-by:
Chun-LiangChang <chuchang@amd.com> Tested-by:
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Joshua Aberback authored
[Why] The values calculated in optc1_get_otg_active_size are assigned to the wrong output parameters, vertical blank is being used for horizontal size and vice versa. This results in DPG test pattern looking wrong during hardware init, as the DPG dimensions get assigned from this output, and potentially other issues. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Dillon Varone authored
[WHY&HOW] When updating clocks via SMU, DAL needs to wait for requests to be fulfilled before proceeding. Reviewed-by:
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Wenjing Liu authored
[why] In order to support glitchless display clock ramping for virtual stream, we must turn on symclk for stream encoder. The code will power on phy and enable symclk for dio encoder during virtual stream dpms sequence. Reviewed-by:
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yi-lchen authored
[why] Vbios & Driver have difference pixel rate div policy. When enabling fast boot & performing blank & unblank w/o timing setting, pixel clock & pixel rate dividor are not match. It would cause too high pixel reate and eDP would be black screen. [How] We would keep pixel rate div setting by Vbios until next timing setting. Reviewed-by:
yi-lchen <yi-lchen@amd.com> Tested-by:
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Alex Deucher authored
This reverts commit 6670142d. Pierre-Eric reported problems with this on his navi33. Revert for now until we understand what is going wrong. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Alex Deucher authored
Add some additional registers. Reviewed-by:
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Marek Olšák authored
define new gfx12 uapi flags Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Jesse Zhang authored
The varible uncached set false, the condition uncached cannot be true. So remove the dead code, mapping flags will set the flag AMDGPU_VM_MTYPE_UC in else. Signed-off-by:
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Shane Xiao authored
This patch changes the implementation of AMDGPU_PTE_MTYPE_NV10, clear the bits before setting the new one. Suggested-by:
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Yifan Zhang authored
This patch to disable lane0 L1TLB and enable lane1 L1TLB. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch to configure mmhub3.3 SAW registers Signed-off-by:
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Tasos Sahanidis authored
Flexible arrays used [1] instead of []. Replace the former with the latter to resolve multiple UBSAN warnings observed on boot with a BONAIRE card. In addition, use the __counted_by attribute where possible to hint the length of the arrays to the compiler and any sanitizers. Signed-off-by:
Tasos Sahanidis <tasos@tasossah.com> Signed-off-by:
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Colin Ian King authored
There are a few spelling mistakes in dml2_printf messages. Fix them. Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Sunil Khatri authored
Fix comments and error messages to rightly represent the information. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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