- 13 Sep, 2019 14 commits
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Hawking Zhang authored
call helper function in late init phase to handle ras init for nbio ip block v2: init local var r to 0 in case the function return failure on asics that don't have ras_late_init implementation Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Hawking Zhang authored
ras_late_init callback function will be used to do common ras init in late init phase. v2: call ras_late_fini to do cleanup when fails to enable interrupt v3: rename sysfs/debugfs node name to pcie_bif_xxx Signed-off-by:
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Hawking Zhang authored
The function will be called in late init phase to do mmhub ras init v2: check ras_late_init function pointer before invoking the function Signed-off-by:
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Hawking Zhang authored
call helper function in late init phase to handle ras init for gmc ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by:
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Hawking Zhang authored
call helper function in late init phase to handle ras init for sdma ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by:
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Hawking Zhang authored
call helper function in late init phase to handle ras init for gfx ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by:
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Hawking Zhang authored
In late_init for ras, the helper function will be used to 1). disable ras feature if the IP block is masked as disabled 2). send enable feature command if the ip block was masked as enabled 3). create debugfs/sysfs node per IP block 4). register interrupt handler v2: check ih_info.cb to decide add interrupt handler or not v3: add ras_late_fini for cleanup all the ras fs node and remove interrupt handler Signed-off-by:
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Hawking Zhang authored
For the hardware that can not enable BIF ring for IH cookies for both ras_controller_irq and err_event_athub_irq, the driver has to poll the status register in irq handling and ack the hardware properly when there is interrupt triggered Signed-off-by:
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Hawking Zhang authored
Ras controller interrupt and Ras err event athub interrupt are two dedicated interrupts for RAS support. Signed-off-by:
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Hawking Zhang authored
Add mmBIF_INTR_CNTL and its shift mask. Signed-off-by:
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Hawking Zhang authored
nbif v7_4 interrupt source definition Signed-off-by:
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Hawking Zhang authored
ras_controller_interrupt and err_event_interrupt are ras specific interrupts. add functions to check their status and ack them if they are generated. both funcitons should only be invoked in ISR when BIF ring is disabled or even not initialized. Signed-off-by:
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Hawking Zhang authored
no functional change, just switch to new structures Signed-off-by:
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Hawking Zhang authored
More nbio funcitonalities will be added and nbio could be treated as an ip block like gfx/sdma.etc Signed-off-by:
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- 06 Sep, 2019 2 commits
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
single etnaviv fix for an error path. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/4ae00cfb47c8e6fffca5dbb45ae9370cd4e5eaf4.camel@pengutronix.de
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
drm-next-5.4-2019-08-30: amdgpu: - Add DC support for Renoir - Add some GPUVM hw bug workarounds - add support for the smu11 i2c controller - GPU reset vram lost bug fixes - Navi1x powergating fixes - Navi12 power fixes - Renoir power fixes - Misc bug fixes and cleanups Signed-off-by:
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- 03 Sep, 2019 1 commit
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Dave Airlie authored
Merge tag 'exynos-drm-next-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next - JUst one cleanup which drops the use of drmP.h header file. Signed-off-by:
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- 02 Sep, 2019 1 commit
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Wei Yongjun authored
Add the missing unlock before return from function etnaviv_iommuv1_context_alloc() in the error handling case. Fixes: 27b67278 ("drm/etnaviv: rework MMU handling") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de>
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- 01 Sep, 2019 1 commit
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Sam Ravnborg authored
There was a few uses of drmP that was missed in the last patch removing this header from exynos. Remove the final uses of this header. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Cc: Inki Dae <inki.dae@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Cc: Seung-Woo Kim <sw0312.kim@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jingoo Han <jingoohan1@gmail.com> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
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- 30 Aug, 2019 6 commits
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Austin Kim authored
Null pointer dereference check should have been checked, ahead of below routine. struct amdgpu_device *adev = hwmgr->adev; With this commit, it could avoid potential NULL dereference. Signed-off-by:
Austin Kim <austindh.kim@gmail.com> Signed-off-by:
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Petr Cvek authored
There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC configurations. This will cause link error. The patch is fixing that. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979Signed-off-by:
Petr Cvek <petrcvekcz@gmail.com> Signed-off-by:
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Aaron Liu authored
In renoir's vega10_ih model, there's a security change in mmIH_CHICKEN register, that limits IH to use physical address (FBPA, GPA) directly. Those chicken bits need to be programmed first. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Aaron Liu authored
In Renoir's emulator, those chicken bits need to be programmed. Signed-off-by:
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Aaron Liu authored
For apu, SMU_MSG_OverridePcieParameters is unsupport. So return directly in smu_override_pcie_parameters function. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Andrey Grodzovsky authored
This should be checked at all places job is accessed. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 29 Aug, 2019 15 commits
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Roman Li authored
Enable DC support for renoir. Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Roman Li authored
Hook up the DML changes for renoir. Acked-by:
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Roman Li authored
Need to check for renoir first. Acked-by:
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Bhawanpreet Lakha authored
Add a kconfig option to enable renoir. Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Enable the building of dcn21 support. Acked-by:
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Bhawanpreet Lakha authored
Add missing parameters, to make dcn21 compile without errors Acked-by:
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Bhawanpreet Lakha authored
Add the rev id for renoir. Acked-by:
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Bhawanpreet Lakha authored
call update_bw_bounding_box in DC construct Acked-by:
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Bhawanpreet Lakha authored
Hook up renoir support to KMS. v2: squash in "Fixes for Renoir in amdgpu_dm" Acked-by:
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Bhawanpreet Lakha authored
add Renoir DCN version in DC and handle it Acked-by:
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Bhawanpreet Lakha authored
rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in the register files Acked-by:
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Bhawanpreet Lakha authored
DML provides the display configuration validation as provided by the hw teams. Acked-by:
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Bhawanpreet Lakha authored
Misc display related configuration details. Acked-by:
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Bhawanpreet Lakha authored
Manages the renoir display resources (crtcs, phys, plls, etc.). v2: rebase (Alex) Acked-by:
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Bhawanpreet Lakha authored
Controls display clocks and interfaces with powerplay for clock and power requirements. Acked-by:
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