- 03 Jan, 2024 29 commits
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Asad Kamal authored
Use separate metric table for APU and Non APU systems for smu_v_13_0_6 to get metric data Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom Chung authored
[WHY] Prepare for enabling the Panel Replay feature [HOW] - Add some Panel Replay setting functions in DC - Add the Panel Replay resource in dcn35_resource.c - Add debug masks for Panel Replay Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Ivan Lipski authored
This reverts commit 44e60b14. Since, it causes a regression in which eDP displays with PSR support, but no Replay support (Sink support <= 0x03), fail to enable PSR and consequently all IGT amd_psr tests fail. So, revert this until a more suitable fix can be found. This got brought back accidently with the backmerge. Acked-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Relja Vojvodic authored
For certain dual display configs that had one display using a 1080p mode, the DPM level used to drive the configs regressed from DPM 0 to DPM 3. This was caused by a missing check that should have only limited the pipe segments on non-phantom pipes. This caused issues with detile buffer allocation, which dissallow subvp from being used Tested-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] A hang was observed where a read-modify-write access occurred due to the register for idle state being shared between DMCUB and driver. dmcub read - idle allow / no commit driver read - idle allow / no commit driver write - idle disallow / no commit dmcub write - idle allow / commit Resulting in DMCUB re-entering IPS after a disable and keeping the allow high. [How] Long term we need to split commit/allow into two registers or use shared DRAM state, but short term we can reduce the repro rate by ensuring that the disallow went through by bounding the expected worst case scenario. Tested-by:
Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Gabe Teeger authored
[Why] Failing mode validation during dc_commit, leading to blackscreen with an 8k DP2 display during mode change. [What] Fix mixmatch between pipe and stream, which prevented us from recognizing the link as DP2. Tested-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Revalla authored
[why] Move all init files to hwss folder. [how] moved the dcnxx_init.c and .h files into inside the hwss and cleared the linkage errors. Tested-by:
Revalla <hrevalla@amd.com> Signed-off-by:
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Alvin Lee authored
For FPO and SubVP/DRR cases we need to ensure to program OTG_V_TOTAL_MIN/MAX_SEL, otherwise stretching the vblank in FPO / SubVP / DRR cases will not have any effect and we could hit underflow / corruption. Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] If bandwidth allocation feature is enabled, connection manager wont limit the dp tunnel bandwidth. So, need to do display mode validation for streams on dpia links to avoid oversubscription of dp tunnel bandwidth. [How] - To read non reduced link rate and lane count and update reported link capability. - To calculate the bandwidth required for streams of dpia links per host router and validate against the allocated bandwidth for the host router. Tested-by:
PeiChen Huang <peichen.huang@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Race condition between notification of driver idle and the command being processed. We could theoretically enter idle between the submission and the wait for idle that occurs after. [How] Switch the notification to NO_WAIT to avoid the RPTR access. Tested-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
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Jack Xiao authored
It's required to take the gfx mutex before access to CP_VMID_RESET, for there is a race condition with CP firmware to write the register. v2: add extra code to ensure the mutex releasing is successful. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] If we time out waiting for PMFW to finish the exit sequence and touch the DMCUB register the system will hang in a hard locked state. [How] Pol forever. This covers the case where things take too long but also enables for debugging to occur since the cores won't be hardlocked. Tested-by:
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Nicholas Kazlauskas authored
[Why] dc->idle_optimizations_allowed may be desynced with the hardware state. [How] Make sure we always exit out when dc_dmub_srv_exit_low_power_state is called by removing the check. Tested-by:
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Relja Vojvodic authored
[Why] Some debug tools, sometimes wrap around to multiple lines which causes issues with the DPM test script while it is looking for the logs. Need a way to tell when the log is finished. [How] Added "LOG_END" to the end of the log. Tested-by:
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Alvin Lee authored
A new check was added to ensure FPO is not enabled when the FPO pipe has 0 planes. This requires the stream status to check the plane count, but the stream status was not assigned for FPO + Vactive cases which leads to FPO not be enabled always. Tested-by:
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Felix Kuehling authored
Change the rules for amdgpu_sync_resv to let KFD synchronize with VM fences on page table reservations. This fixes intermittent memory corruption after evictions when using amdgpu_vm_handle_moved to update page tables for VM mappings managed through render nodes. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Wayne Lin authored
link_rate sometime will be changed when DP MST connector hotplug, so pbn_div also need be updated; otherwise, it will mismatch with link_rate, causes no output in external monitor. Cc: stable@vger.kernel.org Tested-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
Wade Wang <wade.wang@hp.com> Signed-off-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
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Camille Cho authored
[Why] BL1_PWM_USER_LEVEL is meant for the user brightness level setting from OS. However, we update it along with other ABM levels to the real PWM value which could be ABMed. [How] Driver to cache and restore the user brightness level setting so that DMUB can retrieve the last user setting in ABM config initialization. Tested-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Camille Cho <camille.cho@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] Fix minor issues in BW Allocation Phase2. [How] - In set_usb4_req_bw_req(), link->dpia_bw_alloc_config.response_ready flag should be reset before writing DPCD REQUEST_BW. - Fix the granularity for value of 2 in get_bw_granularity(). - Removed bandwidth allocation support display fw boot option as the fw would read feature enable status from bios. - Clean up DPIA_EST_BW_CHANGED and DPIA_BW_REQ_SUCCESS cases in dpia_handle_bw_alloc_response(). - Removed allocate_usb4_bw and deallocate_usb4_bw. - Optimized loop in get_lowest_dpia_index(). - Updated link_dp_dpia_allocate_usb4_bandwidth_for_stream() and set_usb4_req_bw_req() to always issue request bw. Tested-by:
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Josip Pavic authored
[Why] Some functions whose output is typically checked for null are not being checked for null at several call sites, causing some static analysis tools to throw an error. [How] Add null pointer guards around functions that typically have them at other call sites. Tested-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why] Certain HDMI modes failed at dml cap check for uncompressed video but they can still be supported for compressed video. [How] Add HDMI capacity computations using fixed31_32 in dc side. Tested-by:
Chris Park <chris.park@amd.com> Acked-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Relja Vojvodic authored
[Why] More information is desired for the test tools. [How] Refactored get_subvp_visual_confirm_color and get_mclk_switch_visual_confirm_color to support the new method of storing the p_state type, which was changed so that it could also be saved and output by the DPM log. Ensured that the p_state type is kept updated by looping through the pipes within commit_planes_for_stream. Tested-by:
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Alvin Lee authored
In DCN32/321 FPO uses per-pipe P-State force. If there is no plane, then then HUBP is power gated, in which case any programming in HUBP has no effect and the pipe is always asserting P-State allow. This is contrary to what we want to happen for FPO (FW should moderate the P-State assertion), so block FPO if there's no plane for the FPO pipe. Tested-by:
Samson Tam <samson.tam@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
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Alvin Lee authored
[Why] There is some logic error where the wrong variable was used to check for OTG_MASTER and DPP_PIPE. [How] Add booleans to confirm that the expected pipes were found before validating schedulability. Tested-by:
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Stanley.Yang authored
The ecc_irq is disabled while GPU mode2 reset suspending process, but not be enabled during GPU mode2 reset resume process. Changed from V1: only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip delete amdgpu_ras_late_resume function Changed from V2: check umc ras supported before put ecc_irq Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Roman Li authored
[Why] Idle power optimization was disabled on dcn35 by default. [How] Enable by setting disable_idle_power_optimizations to false. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Roman Li authored
[Why] Instability is observed on DCN35 if idle power optimization is enabled. [How] Disable IPS until issue is resolved. Signed-off-by:
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Mangesh Gadre authored
SMN address is larger than 32 bits for registers on different AID's Updating existing interface to support access to such registers. Signed-off-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by:
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Colin Ian King authored
Variable remainder is being initialized with a value that is never read, the assignment is redundant and can be removed. Also add a newline after the declaration to clean up the coding style. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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- 19 Dec, 2023 11 commits
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ZhenGuo Yin authored
Idle bo's PTE needs to be re-created when resetting VM state machine. Set idle bo's vm_bo as moved to mark it as invalid. Fixes: 55bf196f ("drm/amdgpu: reset VM when an error is detected") Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Reviewed-by:
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YiPeng Chai authored
Add umc page retirement for umc v12_0. V2: 1. Changed umc page retirement check condition to call umc_v12_0_is_uncorrectable_error. 2. Use memset to clear the contents of the umc error address structure. Signed-off-by:YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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YiPeng Chai authored
smu v13_0_6 supports ecc info by default. Signed-off-by:
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YiPeng Chai authored
Add poison mode check error condition for umc v12_0. Signed-off-by:
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YiPeng Chai authored
MCA supports recording umc address information. V2: Move err_addr variable from struct ras_err_node to struct ras_err_info. Signed-off-by:
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Aric Cyr authored
This DC patchset brings improvements in multiple areas. In summary, we highlight: - change static screen wait frame_count for ips - Fix hang/underflow when transitioning to ODM4:1 - Only clear symclk otg flag for HDMI - Fix lightup regression with DP2 single display configs - Refactor phantom resource allocation - Refactor dc_state interface - Wake DMCUB before executing GPINT commands - Wake DMCUB before sending a command - Refactor DMCUB enter/exit idle interface - enable dcn35 idle power optimization - fix usb-c connector_type - add debug option for ExtendedVBlank DLG adjust - Set test_pattern_changed update flag on pipe enable - dereference variable before checking for zero - get dprefclk ss info from integration info table - skip error logging when DMUB is inactive from S3 - make flip_timestamp_in_us a 64-bit variable - Add case for dcn35 to support usb4 dmub hpd event - Add function for dumping clk registers - Unify optimize_required flags and VRR adjustments - Revert using channel_width as 2 for vram table 3.0 - remove HPO PG in driver side - do not send commands to DMUB if DMUB is inactive from S3 Acked-by:
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Anthony Koo authored
- Remove unused dmub_fw_boot_options flag Acked-by:
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Allen Pan authored
[Why] the original wait for 2 static frames before enter static screen was not good enough for IPS-enabled case since enter/exit takes more time. [How] Changed logic for hardcoded wait frame values. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Allen Pan <allen.pan@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] Under some circumstances, disabling an OPTC and attempting to reclaim its OPP(s) for a different OPTC could cause a hang/underflow due to OPPs not being properly disconnected from the disabled OPTC. [How] Ensure that all OPPs are unassigned from an OPTC when it gets disabled. Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Alvin Lee authored
[Description] There is a corner case where the symclk otg flag is cleared when disabling the phantom pipe for subvp (because the phantom and main pipe share the same link). This is undesired because we need the maintain the correct symclk otg flag state for the main pipe. For now only clear the flag only for HDMI signal type, since it's only set for HDMI signal type (phantom is virtual). The ideal solution is to not clear it if the stream is phantom but currently there's a bug that doesn't allow us to do this. Once this issue is fixed the proper fix can be implemented. Reviewed-by:
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Michael Strauss authored
[WHY] Previous fix for multiple displays downstream of DP2 MST hub caused regression [HOW] Match sink IDs instead of sink struct addresses Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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