- 17 Nov, 2022 1 commit
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Neil Armstrong authored
This converts the Semtech SX150Xq bindings to dt-schemas, add necessary bindings documentation to cover all differences between HW variants and current bindings usage. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221005-mdm9615-sx1509q-yaml-v3-0-e8b349eb1900@linaro.orgSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 14 Nov, 2022 2 commits
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Andy Shevchenko authored
First of all, while for_each_maps() is private to pin control subsystem it's still better to have it put into a namespace. Besides that, users are not relying on iterator variable, so hide it inside for-loop. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Thierry Reding authored
Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.comSigned-off-by:
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- 10 Nov, 2022 16 commits
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Andy Shevchenko authored
It's slightly better to read when compound literal data and type are separated by a space. Signed-off-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20221109152356.39868-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Wei Li authored
Rename the header guard of mt6795-pinfunc.h from __DTS_MT8173_PINFUNC_H to __DTS_MT6795_PINFUNC_H what corresponding with the file name. Fixes: 81557a71 ("dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings") Signed-off-by:
Wei Li <liwei391@huawei.com> Link: https://lore.kernel.org/r/20221108094529.3597920-1-liwei391@huawei.comSigned-off-by:
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Jesse Taube authored
The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
Jesse Taube <Mr.Bossman075@gmail.com> Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.comSigned-off-by:
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Jesse Taube authored
Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
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Jesse Taube authored
Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
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Jesse Taube authored
Both the i.MXRT1170 and 1050 have the same GPT timer as "fsl,imx6dl-gpt" Add i.MXRT to the compatible list. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20221107071511.2764628-4-Mr.Bossman075@gmail.comSigned-off-by:
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Jesse Taube authored
Reference to pinfunc.h was wrong. Fix it. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
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Jesse Taube authored
Recently the imxrt1050 was added but the cpu compatible node wasn't added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by:
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Sam Shih authored
Commit fb34a9ae ("pinctrl: mediatek: support rsel feature") add SoC specify 'pull_type' attribute for bias configuration. This patch add pull_type attribute to pinctrl-mt7986.c, and make bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. Signed-off-by:
Sam Shih <sam.shih@mediatek.com> Signed-off-by:
Frank Wunderlich <frank-w@public-files.de> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.deSigned-off-by:
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Sam Shih authored
Commit fb34a9ae ("pinctrl: mediatek: support rsel feature") introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo and mtk_pinconf_bias_get_combo, and make the functions able to support almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. This patch enables pinctrl_moore to support these functions. Signed-off-by:
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Sam Shih authored
Correct the bias-pull-up, bias-pull-down and bias-disable register offset of mt7986 pin-42 to pin-49, in the original driver, the relative offset value was erroneously decremented by 1. Fixes: 360de672 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by:
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Sam Shih authored
Since the bias-pull-{up,down} attribute already defines in pinctrl driver of mediatek MT7986 SoC, this patch updates bindings to support mediatek common bias-pull* function. Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221106080114.7426-4-linux@fw-web.deSigned-off-by:
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Frank Wunderlich authored
Fix mmc and uart pins after uart splitting. Some pinmux pins of the mt7986 pinctrl driver is composed of multiple pinctrl groups, the original binding only allows one pinctrl group per dts node, this patch sets "maxItems" for these groups and add new examples to the binding documentation. Fixes: 65916a1c ("dt-bindings: pinctrl: update bindings for MT7986 SoC") Signed-off-by:
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Frank Wunderlich authored
Allow multiple items for pcie, pwm and spi function. Signed-off-by:
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Jonathan Neuschäfer authored
SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0 selects the GPIO function and 1 selects the special function, in these two fields, 0 selects the special function and 1 selects the GPIO function. Adjust the code to handle this quirk. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.netSigned-off-by:
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Jonathan Neuschäfer authored
In preparation for the next patch, which makes the logic around setting/resetting bits in MFSEL a little more complicated, move that code to a new function Signed-off-by:
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- 09 Nov, 2022 8 commits
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Siarhei Volkau authored
The example declares "struct pinctrl *p" but refers to "foo->p" which isn't declared in the context of the example. Signed-off-by:
Siarhei Volkau <lis8215@gmail.com> Link: https://lore.kernel.org/r/20221101205159.1468069-3-lis8215@gmail.comSigned-off-by:
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Siarhei Volkau authored
The function requires two arguments. Signed-off-by:
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Jonathan Neuschäfer authored
Commit 6c846d02 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning for irqchips that are not marked with IRQCHIP_IMMUTABLE. Convert the pinctrl-wpcm450 driver to an immutable irqchip. Signed-off-by:
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Yassine Oudjana authored
Clarify the meaning of sysirq to avoid confusion. Suggested-by:
Yassine Oudjana <y.oudjana@protonmail.com> Acked-by:
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Yassine Oudjana authored
The document currently states a maximum of 1 interrupt, but the DT has 2 specified causing a dtbs_check error. Replace the maximum limit with a minimum and add per-interrupt descriptions to pass the check. Fixes: 81557a71 ("dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings") Suggested-by:
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Yassine Oudjana authored
Combine MT6797 pin controller document into MT6779 one. reg and reg-names property constraints are set using conditionals. A conditional is also used to make interrupt-related properties required on the MT6779 pin controller only, since the MT6797 controller doesn't support interrupts (or not yet, at least). drive-strength and slew-rate properties which weren't described in the MT6779 document before are brought in from the MT6797 one. Both pin controllers share a common driver core so they should both support these properties. Signed-off-by:
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Yassine Oudjana authored
The pin controller can function without specifying gpio-ranges so remove it from required properties. This is also done in preparation for adding other pin controllers which currently don't have the gpio-ranges property defined where they are used in DTS. This allows dtbs_check to pass on those device trees. Signed-off-by:
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Yassine Oudjana authored
The current description mentions having to put the pin controller node under a syscon node, but this is not the case in the current MT6779 device tree. This is not actually needed, so replace the current description with something more generic that describes the use of the hardware block. Signed-off-by:
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- 08 Nov, 2022 2 commits
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Shenwei Wang authored
On i.MX8QM/QXP/DXL SoCs, even a GPIO is selected as the wakeup source, the GPIO block will be powered off when system enters into suspend state. This can greatly reduce the power consumption of suspend state because the whole partition can be shutdown. This is called PAD wakeup feature on i.MX8x platform. This patch adds the noirq suspend/resume hooks and uses the pad wakeup feature as the default wakeup method for GPIO modules on i.MX8QM/QXP/DXL platforms. Signed-off-by:
Shenwei Wang <shenwei.wang@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Acked-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20221027130859.1444412-6-shenwei.wang@nxp.comSigned-off-by:
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Shenwei Wang authored
add the logic to configure the pad wakeup function via the pin_config_set handler. Signed-off-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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- 07 Nov, 2022 2 commits
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Balsam CHIHI authored
On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.comSigned-off-by:
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Balsam CHIHI authored
On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by:
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- 26 Oct, 2022 1 commit
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Linus Walleij authored
Merge tag 'intel-pinctrl-v6.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.1-2 * Add missing and remove unused headers in the pin control and GPIO drivers * Revise the pin control and GPIO headers
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- 24 Oct, 2022 8 commits
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Andy Shevchenko authored
There is a few things done: - include only the headers we are direct user of - when pointer is in use, provide a forward declaration - add missing headers - group generic headers and subsystem headers - sort each group alphabetically While at it, fix some awkward indentations. Signed-off-by: -
Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com>
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Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by:
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Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by:
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Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by:
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Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: -
Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: -
Andy Shevchenko authored
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by:
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