- 02 Jul, 2024 20 commits
-
-
Lorenzo Bianconi authored
Introduce Tx-Rx detection Time and Rx AEQ training mappings to phy-airoha-pcie driver. This is a preliminary patch to introduce PCIe support to En7581 SoC through the mediatek-gen3 PCIe driver. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/edf3b28926177166c65256604d69f2f576cb6fb3.1719682943.git.lorenzo@kernel.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
-
Lorenzo Bianconi authored
Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581 PCIe-PHY binding. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.orgSigned-off-by:
-
Shresth Prasad authored
Convert txt bindings of Rockchip EMMC PHY to dtschema to allow for validation. Signed-off-by:
Shresth Prasad <shresthprasad7@gmail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240620212806.3011-2-shresthprasad7@gmail.comSigned-off-by:
-
Yijie Yang authored
Correct the spelling error, changing 'com' to 'qcom'. Cc: stable@vger.kernel.org Fixes: f75a4b3a ("dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY") Signed-off-by:
Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by:
-
André Draszik authored
Add support for the Exynos USB 3.1 DRD combo phy, as found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and DisplayPort. In terms of UTMI+, this is very similar to the existing Exynos850 support in this driver. The difference is that this combo phy supports both UTMI+ (HS) and PIPE3 (SS). It also supports DP alt mode. The number of ports for UTMI+ and PIPE3 can be determined using the LINKPORT register (which also exists on Exynos E850). For SuperSpeed (SS) a new SS phy is in use and its PIPE3 interface is new compared to Exynos E850, and also very different from the existing support for older Exynos SoCs in this driver. The SS phy needs a bit more configuration work and register tuning for signal quality to work reliably, presumably due to the higher frequency, e.g. to account for different board layouts. Additionally, power needs to be enabled before writing to the SS phy registers. This commit adds the necessary changes for USB HS and SS to work. DisplayPort is out of scope in this commit. Notes: * For the register tuning, exynos5_usbdrd_apply_phy_tunes() has been added with the appropriate data structures to support tuning at various stages during initialisation. Since these are hardware specific, the platform data is supposed to be populated accordingly. The implementation is loosely modelled after the Samsung UFS PHY driver. There is one tuning state for UTMI+, PTS_UTMI_POSTINIT, to execute after init and generally intended for HS signal tuning, as done in this commit. PTS_PIPE3_PREINIT PTS_PIPE3_INIT PTS_PIPE3_POSTINIT PTS_PIPE3_POSTLOCK are tuning states for PIPE3. In the downstream driver, preinit differs by Exynos SoC, and postinit and postlock are different per board. The latter haven't been implemented for gs101 here, because downstream doesn't use them on gs101 either. * Signal lock acquisition for SS depends on the orientation of the USB-C plug. Since there currently is no infrastructure to chain connector events to both the USB DWC3 driver and this phy driver, a work-around has been added in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock() to check both registers if it failed in one of the orientations. * Equally, we can only establish SS speed in one of the connector orientations due to programming differences when selecting the lane mux in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(), which really needs to be dynamic, based on the orientation of the connector. * As is, we can establish a HS link using any cable, and an SS link in one orientation of the plug, falling back to HS if the orientation is reversed to the expectation. Signed-off-by:
André Draszik <andre.draszik@linaro.org> Reviewed-by:
Peter Griffin <peter.griffin@linaro.org> Tested-by:
Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-6-b66de9ae7424@linaro.orgSigned-off-by:
-
André Draszik authored
Using the regulator_bulk APIs, the handling of power supplies becomes much simpler. There is no need anymore to check if regulators have been acquired or not, the bulk APIs will do all the work for us. We can also drop the various handles to the individual power supplies in the driver runtime data and instead simply treat them all as one thing. Error cleanup also becomes much simpler. Converting to the regulator_bulk APIs also makes it easier to add support for those SoCs that have additional power supplies for the PHY. Google Tensor gs101 is one example of such a SoC. Otherwise we'd have to add all additional supplies individually via individual calls to regulator_get() and enable/disable handle them all individually, including complicated error handling. That doesn't scale and clutters the code. Just update the code to use the regulator_bulk APIs. Signed-off-by:
-
André Draszik authored
In preparation for support for additional platforms, convert the phy register access clock to using the clk_bulk interfaces. Newer SoCs like Google Tensor gs101 require additional clocks for access to additional (different) register areas (PHY, PMA, PCS), and converting to clk_bulk simplifies addition of those extra clocks. Signed-off-by:
-
André Draszik authored
Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. No need to check any flags whether or not certain clocks exist or not. Further, we can drop the various handles to the individual clocks in the driver data and instead simply treat them all as one thing. So far, this driver assumes that all platforms have a clock "ref". It also assumes that the clocks "phy_pipe", "phy_utmi", and "itp" exist if the platform data "has_common_clk_gate" is set to true. It then goes and individually tries to acquire and enable and disable all the individual clocks one by one. Rather than relying on these implicit clocks and open-coding the clock handling, we can just explicitly spell out the clock names in the different device data and use that information to populate clk_bulk_data, allowing us to use the clk_bulk APIs for managing the clocks. As a side-effect, this change highlighted the fact that exynos5_usbdrd_phy_power_on() forgot to check the result of the clock enable calls. Using the clk_bulk APIs, the compiler now warns when return values are not checked - therefore add the necessary check instead of silently ignoring failures and continuing as if all is OK when it isn't. For consistency, also change a related dev_err() to dev_err_probe() in exynos5_usbdrd_phy_clk_handle() to get consistent error message formatting. Finally, exynos5_usbdrd_phy_clk_handle() prints an error message in all cases as necessary (except for -ENOMEM). There is no need to print another message in its caller (the probe() function), and printing errors during OOM conditions is usually discouraged. Drop the duplicated message in exynos5_usbdrd_phy_probe(). Signed-off-by:
-
André Draszik authored
Some versions of this IP have been integrated using separate PMU power control registers for the HS and SS parts. One example is the Google Tensor gs101 SoC. Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value. The existing 'usbdrdphy' alias can not be used in this case because that is meant for determining the correct PMU offset if multiple distinct PHYs exist in the system (as opposed to one PHY with multiple isolators). Signed-off-by:
-
André Draszik authored
Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor gs101 SoC. It needs additional clocks enabled for register access, and additional memory regions (PCS & PMA) are required for successful configuration. It also requires various power supplies (regulators) for the internal circuitry to work. The required voltages are: * pll-supply: 0.85V * dvdd-usb20-supply: 0.85V (+10%, -7%) * vddh-usb20-supply: 1.8V (+10%, -7%) * vdd33-usb20-supply: 3.3V (+10%, -7%) * vdda-usbdp-supply: 0.85V * vddh-usbdp-supply: 1.8V Signed-off-by:
-
Miaoqian Lin authored
of_phy_put is used for of_phy_get to release the reference count. Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20240626080911.203630-1-linmq006@gmail.comSigned-off-by:
-
Changhuang Liang authored
We actually want to calculate the alignment values first, then use the alignment value to look up the data from reg_configs[]. Fixes: d3ab7955 ("phy: starfive: Add mipi dphy tx support") Reviewed-by:
Shengyang Chen <shengyang.chen@starfivetech.com> Signed-off-by:
Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240627020059.163535-1-changhuang.liang@starfivetech.comSigned-off-by:
-
Sean Anderson authored
Add support for printing some basic status information to debugfs. This is helpful when debugging phy consumers to make sure they are configuring the phy appropriately. Signed-off-by:
Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-6-sean.anderson@linux.devSigned-off-by:
-
Sean Anderson authored
Take the phy mutex in xlate to protect against concurrent modification/access to gtr_phy. This does not typically cause any issues, since in most systems the phys are only xlated once and thereafter accessed with the phy API (which takes the locks). However, we are about to allow userspace to access phys for debugging, so it's important to avoid any data races. Signed-off-by:
-
Sean Anderson authored
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by:
-
Sean Anderson authored
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by:
-
Sean Anderson authored
Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d70083 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save") Signed-off-by:
-
Ma Ke authored
cdns_torrent_dp_set_power_state() does not consider that ret might be overwritten. Add return value check of regmap_read_poll_timeout() after register read in cdns_torrent_dp_set_power_state(). Fixes: 5b16a790 ("phy: cadence-torrent: Reorder few functions to remove function declarations") Signed-off-by:
Ma Ke <make24@iscas.ac.cn> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cnSigned-off-by:
-
Liu Jing authored
The word 'swtich' is wrong, so fix it. Signed-off-by:
Liu Jing <liujing@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20240701112517.6597-1-liujing@cmss.chinamobile.comSigned-off-by:
-
Cristian Ciocaltea authored
Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be283 ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.comSigned-off-by:
-
- 20 Jun, 2024 3 commits
-
-
Lorenzo Bianconi authored
Introduce support for Airoha PCIe PHY controller available in EN7581 SoC. Reviewed-by:
Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by:
-
Lorenzo Bianconi authored
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY controller. Reviewed-by:
-
Nathan Chancellor authored
In various configurations/architectures, bitfield.h may not be transitively included, which results in a compiler error because FIELD_PREP is an unexpanded macro: drivers/phy/freescale/phy-fsl-imx8qm-hsio.c:459:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 459 | val = FIELD_PREP(HSIO_MODE_MASK, val); | ^ 1 error generated. Include bitfield.h explicitly to fix the build. Fixes: 82c56b6d ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by:Nathan Chancellor <nathan@kernel.org> Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406170340.7mk3WU3Q-lkp@intel.com/Reviewed-by:
Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240620-phy-fsl-imx8qm-hsio-add-bitfield-include-v1-1-5c7c09ed87e6@kernel.orgSigned-off-by:
-
- 15 Jun, 2024 7 commits
-
-
Richard Zhu authored
Add i.MX8QM HSIO PHY driver support. i.MX8QM HSIO has three lane PHY instances, and can be bound to the following controllers in the different use cases listed in below table. - two lanes capable PCIEA controller. - one lane PCIEB controller. - AHCI SATA controller. i.MX8QM HSIO PHYs support the following use cases. +----------------------------------------------------+ | | Lane0| Lane1| Lane2| |-------------------------------|------|------|------| | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA | |-------------------------------|------|------|------| | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| |-------------------------------|------|------|------| | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | +----------------------------------------------------+ Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by:
-
Richard Zhu authored
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at initialization according to board design. Signed-off-by:
-
Shengyang Chen authored
Add mipi dphy tx support for the StarFive JH7110 SoC. It is a module which is used to receive data from DSI driver and transfer data to DSI interface like mipi screen. Signed-off-by:
-
Shengyang Chen authored
StarFive SoCs like the jh7110 use a MIPI D-PHY TX controller based on a M31 IP. Add a binding for it. Signed-off-by:
-
Herman van Hazendonk authored
Adds qcom,usb-hs-phy-msm8660 compatible Used by HP Touchpad (tenderloin) for example. Signed-off-by:
Herman van Hazendonk <github.com@herrie.org> Reviewed-by:
Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240417065454.3599824-1-github.com@herrie.orgSigned-off-by:
-
Dmitry Baryshkov authored
There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. Partially revert commit 72bea132 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs"), returning compatibility with the existing device tree: reduce clock-output-names to always contain a single entry. Fixes: 72bea132 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs") Acked-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-2-730d1811acf4@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9cc ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
-
- 12 Jun, 2024 9 commits
-
-
Neil Armstrong authored
On newer SoCs, the USB2 PHY can require a power-domain to operate, add it as optional. Signed-off-by:
-
Jeff Johnson authored
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb3.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by:
Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240608-md-drivers-phy-broadcom-v1-1-f070f84cc3f0@quicinc.comSigned-off-by:
-
Jan Kiszka authored
Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/60089a71-dad2-4a87-a304-a738e3334d4a@siemens.comSigned-off-by:
-
Josua Mayer authored
Armada CP110 UTMI supports swapping D+ and D- signals. usb251xb.yaml already describes a suitable device-tree property for the same purpose but as child usb controller node. Add optional swap-dx-lanes device-tree property to armada cp110 utmi phy with same semantics as usb251xb: The property lists all ports that swap D+ and D-, unlisted ports are considered correct. Signed-off-by:
Josua Mayer <josua@solid-run.com> Reviewed-by:
-
André Draszik authored
While commit 255ec387 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Signed-off-by:
-
André Draszik authored
Using 0x82 seems odd, where everything else is just a sequence. On E850, this macro isn't used (as a register value), only to assign its value to the 'extrefclk' variable, which is otherwise unused on that platform. Older platforms don't appear to support 26MHz in the first place (since this macro was added for E850). Furthermore, the downstream driver uses 0x82 to denote USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the other values we match downstream's non-DIFF macros. Update to avoid confusion. No functional change intended. Signed-off-by:
-
André Draszik authored
on / not on is just a boolean flag and is a bit misleading as currently on==1 means to turn off the power, and on==0 to turn power on. Rename the flag and make it a bool to avoid confusion of future readers of this code. No functional change. While at it, fix a whitespace issue in nearby comment. No functional change. Signed-off-by:
-
André Draszik authored
The timers-howto recommends using usleep_range() and friends anytime waiting for >= ~10us is required. Doing so can help the timer subsystem a lot to coalesce wakeups. Additionally, fsleep() exists as a convenient wrapper so we do not have to think about which exact sleeping function is required in which case. Convert all udelay() calls in this driver to use fsleep() to follow the recommendataion. Signed-off-by:
-
André Draszik authored
Most of the macros are ordered high -> low, but there are some outliers. Order them all uniformly from high to low. This will allow adding additional register (field) definitions in a consistent way. While at it, also remove some extra empty lines to group register bit field definitions together with the relevant register. This makes the registers easier to distinguish visually. No functional change. Signed-off-by:
-
- 03 Jun, 2024 1 commit
-
-
devi priya authored
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Co-developed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.comSigned-off-by:
-
