- 19 May, 2022 8 commits
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YueHaibing authored
drivers/dma/tegra186-gpc-dma.c: In function ‘tegra_dma_probe’: drivers/dma/tegra186-gpc-dma.c:1364:24: error: ‘struct iommu_fwspec’ has no member named ‘ids’ stream_id = iommu_spec->ids[0] & 0xffff; ^~ Make TEGRA186_GPC_DMA depends on IOMMU_API to fix this. Fixes: ee170280 ("dmaengine: tegra: Add tegra gpcdma driver") Signed-off-by:YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20220505093236.15076-1-yuehaibing@huawei.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Miquel Raynal authored
The Renesas RZN1 DMA IP is very close to the original DW DMA IP, a DMA router has been introduced to handle the wiring options that have been added. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-By:
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Miquel Raynal authored
The clock controller device on r9a06g032 takes all the memory range that is described as being a system controller. This range contains many different (unrelated?) registers besides the ones belonging to the clock controller, that can necessitate to be accessed from other peripherals. For instance, the dmamux registers are there. The dmamux "device" will be described as a child node of the clock/system controller node, which means we need the top device driver (the clock controller driver in this case) to populate its children manually. In case of error when populating the children, we do not fail the probe on purpose to keep the clk driver up and running. Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Reviewed-by:
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Miquel Raynal authored
The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional dmamux register located in the system control area which can take up to 32 requests (16 per DMA controller). Each DMA channel can be wired to two different peripherals. We need two additional information from the 'dmas' property: the channel (bit in the dmamux register) that must be accessed and the value of the mux for this channel. Signed-off-by:
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20220427095653.91804-6-miquel.raynal@bootlin.comSigned-off-by:
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Miquel Raynal authored
The dmamux register is located within the system controller. Without syscon, we need an extra helper in order to give write access to this register to a dmamux driver. Signed-off-by:
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Miquel Raynal authored
Just like for the NAND controller that is also on this SoC, let's provide a SoC generic and a more specific couple of compatibles for the DMA controller. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Miquel Raynal authored
This system controller contains several registers that have nothing to do with the clock handling, like the DMA mux register. Describe this part of the system controller as a subnode. Signed-off-by:
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Miquel Raynal authored
The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional dmamux register located in the system control area which can take up to 32 requests (16 per DMA controller). Each DMA channel can be wired to two different peripherals. Signed-off-by:
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- 16 May, 2022 16 commits
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Minghao Chi authored
Calling synchronize_irq() right before free_irq() is quite useless. On one hand the IRQ can easily fire again before free_irq() is entered, on the other hand free_irq() itself calls synchronize_irq() internally (in a race condition free way), before any state associated with the IRQ is freed. Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220516115412.1651772-1-chi.minghao@zte.com.cnAcked-by:
Dave Jiang <dave.jiang@intel.com> Signed-off-by:
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Dave Jiang authored
When setting DMA_INTERRUPT capability, a callback function dma->device_prep_dma_interrupt() is needed to support this capability. Without setting the callback, dma_async_device_register() will fail dma capability check. Fixes: 4e5a4eb2 ("dmaengine: idxd: set DMA_INTERRUPT cap bit") Signed-off-by:
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Krzysztof Kozlowski authored
The generic property, used in most of the drivers and defined in generic dma-common DT bindings, is 'dma-channels'. Switch to new property while keeping backward compatibility. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/20220503065147.51728-3-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
The generic property, used in most of the drivers and defined in generic dma-common DT bindings, is 'dma-channels'. Signed-off-by:
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Dave Jiang authored
Skip wq irq resources freeing when wq type is not kernel since the driver skips the irq alloction during wq enable. Add check in wq type check in idxd_wq_free_irq() to mirror idxd_wq_request_irq(). Fixes: 63c14ae6 ("dmaengine: idxd: refactor wq driver enable/disable operations") Reported-by:
Tony Zu <tony.zhu@intel.com> Tested-by:
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Dave Jiang authored
Since idxd_register/unregister_dma_channel() are only called locally, make them static. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Radhey Shyam Pandey authored
pm_runtime_resume_and_get() automatically handle dev->power.usage_count decrement on errors, so prefer using it and also implement it's error handling. Signed-off-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1652166762-18317-4-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by:
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Shravya Kumbham authored
Add condition to check the return value of dma_async_device_register and implement its error handling. Addresses-Coverity: Event check_return. Signed-off-by:
Shravya Kumbham <shravya.kumbham@xilinx.com> Signed-off-by:
Harini Katakam <harini.katakam@xilinx.com> Signed-off-by:
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Radhey Shyam Pandey authored
In zynqmp_dma_alloc/free_chan_resources functions there is a potential overflow in the below expressions. dma_alloc_coherent(chan->dev, (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS), &chan->desc_pool_p, GFP_KERNEL); dma_free_coherent(chan->dev,(2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS), chan->desc_pool_v, chan->desc_pool_p); The arguments desc_size and ZYNQMP_DMA_NUM_DESCS were 32 bit. Though this overflow condition is not observed but it is a potential problem in the case of 32-bit multiplication. Hence fix it by changing the desc_size data type to size_t. In addition to coverity fix it also reuse ZYNQMP_DMA_DESC_SIZE macro in dma_alloc_coherent API argument. Addresses-Coverity: Event overflow_before_widen. Signed-off-by: -
Dave Jiang authored
idxd_wq_device_reset_cleanup() already calls idxd_wq_disable_cleanup(). There is no need to call idxd_wq_disable_cleanup() again in idxd_device_wqs_clear_state(). Remove redudant call from idxd_wq_device_reset_cleanup(). Fixes: 0dcfe41e ("dmanegine: idxd: cleanup all device related bits after disabling device") Signed-off-by:
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Dave Jiang authored
Call idxd_wq_free_irq() in the drv_disable_wq() function before idxd_wq_reset() is called. Otherwise the wq type is reset and the irq does not get freed. Fixes: 63c14ae6 ("dmaengine: idxd: refactor wq driver enable/disable operations") Signed-off-by:
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Dave Jiang authored
Jacob reported that with lockdep debug turned on, idxd_device_driver removal causes kernel splat from lock assert warning for idxd_device_wqs_clear_state(). Make sure idxd_device_wqs_clear_state() holds the wq lock for each wq when cleaning the wq state. Move the call outside of the device spinlock. Reported-by:
Jacob Pan <jacob.jun.pan@intel.com> Signed-off-by:
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Dave Jiang authored
The idxd driver always gated the pasid enabling under a single knob and this assumption is incorrect. The pasid used for kernel operation can be independently toggled and has no dependency on the user pasid (and vice versa). Split the two so they are independent "enabled" flags. Signed-off-by:
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Geert Uytterhoeven authored
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence move its compatible value to the R-Car Gen4 section. Signed-off-by:
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Christophe JAILLET authored
If a call to alloc_chrdev_region() fails, the already allocated resources are leaking. Add the needed error handling path to fix the leak. Fixes: 42d279f9 ("dmaengine: idxd: add char driver to expose submission portal to userland") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by:
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Akhil R authored
Use platform_irq_get() instead platform_get_resource() for IRQ resource to fix the probe failure. platform_get_resource() fails to fetch the IRQ resource as it might not be ready at that time. platform_irq_get() is also the recommended way to get interrupt as it directly gives the IRQ number and no conversion from resource is required. Fixes: ee170280 ("dmaengine: tegra: Add tegra gpcdma driver") Reported-by:
Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by:
Akhil R <akhilrajeev@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
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- 22 Apr, 2022 4 commits
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Yunbo Yu authored
It is unnecessary to call spin_lock_bh() for that you are already in a tasklet. Signed-off-by:
Yunbo Yu <yuyunbo519@gmail.com> Link: https://lore.kernel.org/r/20220420122754.148359-1-yuyunbo519@gmail.comSigned-off-by:
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Dave Jiang authored
Move the core driver operations from wq driver to the drv_enable_wq() and drv_disable_wq() functions. The move should reduce the wq driver's knowledge of the core driver operations and prevent code confusion for future wq drivers. Signed-off-by:
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Jayesh Choudhary authored
Correct the RX PSIL thread for sa3ul. Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com> Fixes: 5ac6bfb5 ("dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data") Link: https://lore.kernel.org/r/20220421065323.16378-1-j-choudhary@ti.comSigned-off-by:
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Vinod Koul authored
LKP bot reports a new warning: Warning: drivers/dma/ptdma/ptdma-dmaengine.c:262:1: warning: no previous prototype for 'pt_tx_status' [-Wmissing-prototypes] pt_tx_status() should be static, so declare as such. Reported-by:
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- 20 Apr, 2022 12 commits
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Ben Walker authored
The value parameter is a single byte, so duplicate it to the 8 byte range that is used as the pattern. Signed-off-by:
Ben Walker <benjamin.walker@intel.com> Cc: Sinan Kaya <okaya@kernel.org> Link: https://lore.kernel.org/r/20220301182551.883474-5-benjamin.walker@intel.comSigned-off-by:
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Ben Walker authored
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by:
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Ben Walker authored
The value passed in to .prep_dma_memset is to be treated as a single byte repeating pattern. Signed-off-by:
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Ben Walker authored
Document this function to make clear the expected behavior of the 'value' parameter. It was intended to match the behavior of POSIX memset as laid out here: https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/Signed-off-by:
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Dave Jiang authored
Move the calling of request_irq() and other related irq setup code until after the WQ is successfully enabled. This reduces the amount of setup/teardown if the wq is not configured correctly and cannot be enabled. Signed-off-by:
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Jiapeng Chong authored
Eliminate the follow versioncheck warning: ./drivers/dma/tegra186-gpc-dma.c: 21 linux/version.h not needed. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/20220413083842.69845-1-jiapeng.chong@linux.alibaba.comSigned-off-by:
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Dave Jiang authored
Looks like I forgot to add DMA_INTERRUPT cap setting to the idxd driver and dmatest is still working regardless of this mistake. Add an explicit check of DMA_INTERRUPT capability for dmatest to make sure the DMA device being used actually supports interrupt before the test is launched and also that the driver is programmed correctly. Signed-off-by:
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Haowen Bai authored
This fixes the following sparse warnings: drivers/dma/mediatek/mtk-hsdma.c:604:26: warning: Using plain integer as NULL pointer Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1649750340-30777-1-git-send-email-baihaowen@meizu.comSigned-off-by:
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Haowen Bai authored
Unneeded variable: "retval". Return "NULL" , so we have to make code clear. better way, drop the function. Signed-off-by:
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Dave Jiang authored
Load the max_xfer_size and max_batch_size values from the values read from registers to the shadow variables. This will allow the read-only device to display the correct values for the sysfs attributes. Signed-off-by:
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Dave Jiang authored
Even though idxd driver has always supported interrupt, it never actually set the DMA_INTERRUPT cap bit. Rectify this mistake so the interrupt capability is advertised. Reported-by:
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Aidan MacDonald authored
Set the maximum segment size, since the hardware can do transfers larger than the default 64 KiB returned by dma_get_max_seg_size(). The maximum segment size is limited by the 24-bit transfer count field in DMA descriptors. The number of bytes is equal to the transfer count times the transfer size unit, which is selected by the driver based on the DMA buffer address and length of the transfer. The size unit can be as small as 1 byte, so set the maximum segment size to 2^24-1 bytes to ensure the transfer count will not overflow regardless of the size unit selected by the driver. Signed-off-by:
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220411153618.49876-1-aidanmacdonald.0x0@gmail.comSigned-off-by:
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