- 30 Nov, 2022 1 commit
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Daniele Ceraolo Spurio authored
The fence is only tracking if the HuC load is in progress or not and doesn't distinguish between already loaded, not supported or disabled, so we can always initialize it to completed, no matter the actual support. We already do that for most platforms, but we skip it on GTs that lack VCS engines (e.g. MTL root GT), so fix that. Note that the cleanup is already unconditional. While at it, move the init/fini to helper functions. Fixes: 8e5f3782 ("drm/i915/huc: fix leak of debug object in huc load fence on driver unload") Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by:
John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221123235417.1475709-1-daniele.ceraolospurio@intel.com (cherry picked from commit 14347a9c) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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- 29 Nov, 2022 5 commits
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Mikko Kovanen authored
intel_dsi->ports contains bitmask of enabled ports and correspondingly logic for selecting port for VBT packet sending must use port specific bitmask when deciding appropriate port. Fixes: 08c59dde ("drm/i915/dsi: fix VBT send packet port selection for ICL+") Cc: stable@vger.kernel.org Signed-off-by:
Mikko Kovanen <mikko.kovanen@aavamobile.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Xia Fukun authored
When (size != 0 || ptrs->lvds_ entries != 3), the program tries to free() the ptrs. However, the ptrs is not created by calling kzmalloc(), but is obtained by pointer offset operation. This may lead to memory leaks or undefined behavior. Fix this by replacing the arguments of kfree() with ptrs_block. Fixes: a87d0a84 ("drm/i915/bios: Generate LFP data table pointers if the VBT lacks them") Signed-off-by:
Xia Fukun <xiafukun@huawei.com> Signed-off-by:
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Janusz Krzysztofik authored
Users of intel_gt_retire_requests_timeout() expect 0 return value on success. However, we have no protection from passing back 0 potentially returned by a call to dma_fence_wait_timeout() when it succedes right after its timeout has expired. Replace 0 with -ETIME before potentially using the timeout value as return code, so -ETIME is returned if there are still some requests not retired after timeout, 0 otherwise. v3: Use conditional expression, more compact but also better reflecting intention standing behind the change. v2: Move the added lines down so flush_submission() is not affected. Fixes: f33a8a51 ("drm/i915: Merge wait_for_timelines with retire_request") Signed-off-by:Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Cc: stable@vger.kernel.org # v5.5+ Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221121145655.75141-3-janusz.krzysztofik@linux.intel.com (cherry picked from commit f301a29f) Signed-off-by:
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Janusz Krzysztofik authored
Commit b97060a9 ("drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC") extended the API of intel_gt_retire_requests_timeout() with an extra argument 'remaining_timeout', intended for passing back unconsumed portion of requested timeout when 0 (success) is returned. However, when request retirement happens to succeed despite an error returned by a call to dma_fence_wait_timeout(), that error code (a negative value) is passed back instead of remaining time. If we then pass that negative value forward as requested timeout to intel_uc_wait_for_idle(), an explicit BUG will be triggered. If request retirement succeeds but an error code is passed back via remaininig_timeout, we may have no clue on how much of the initial timeout might have been left for spending it on waiting for GuC to become idle. OTOH, since all pending requests have been successfully retired, that error code has been already ignored by intel_gt_retire_requests_timeout(), then we shouldn't fail. Assume no more time has been left on error and pass 0 timeout value to intel_uc_wait_for_idle() to give it a chance to return success if GuC is already idle. v3: Don't fail on any error passed back via remaining_timeout. v2: Fix the issue on the caller side, not the provider. Fixes: b97060a9 ("drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC") Signed-off-by:
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Daniele Ceraolo Spurio authored
The fence is always initialized in huc_init_early, but the cleanup in huc_fini is only being run if HuC is enabled. This causes a leaking of the debug object when HuC is disabled/not supported, which can in turn trigger a warning if we try to register a new debug offset at the same address on driver reload. To fix the issue, make sure to always run the cleanup code. Reported-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reported-by:
Brian Norris <briannorris@chromium.org> Fixes: 27536e03 ("drm/i915/huc: track delayed HuC load with a fence") Signed-off-by:
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- 23 Nov, 2022 6 commits
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Umesh Nerlige Ramappa authored
Engine busyness samples around a 10ms period is failing with busyness ranging approx. from 87% to 115% as shown below. The expected range is +/- 5% of the sample period. Fail 10% of the time. rcs0: reported 11716042ns [91%] busyness while spinning [for 12805719ns] When determining busyness of active engine, the GuC based engine busyness implementation relies on a 64 bit timestamp register read. The latency incurred by this register read causes the failure. On DG1, when the test fails, the observed latencies range from 900us - 1.5ms. Optimizing the 2x32 read by acquiring the lock and forcewake prior to all reg reads reduces the rate of failure to around 2%, but does not eliminate it. In order to make the selftest more robust and always account for such latencies, increase the sample period to 100 ms. This eliminates the issue as seen in a 1000 runs. v2: (Ashutosh) - Add error to commit msg - Include gitlab bug - Update commit for inclusion of 2x32 optimized read Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4418Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Acked-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
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Umesh Nerlige Ramappa authored
PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower 32 bit registers are read in a loop, there is a latency involved between getting the GT timestamp and the CPU timestamp. As part of the resolution, refactor intel_uncore_read64_2x32 to acquire forcewake and uncore lock prior to reading upper and lower regs. Signed-off-by:
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Jani Nikula authored
The default_lists array should be in rodata. Fixes: dce2bd54 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.") Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221122141616.3469214-1-jani.nikula@intel.com (cherry picked from commit 8b7f7a9b) Signed-off-by:
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Ville Syrjälä authored
bigjoiner_pipes() doesn't consider that: - RKL only has three pipes - some pipes may be fused off This means that intel_atomic_check_bigjoiner() won't reject all configurations that would need a non-existent pipe. Instead we just keep on rolling witout actually having reserved the slave pipe we need. It's possible that we don't outright explode anywhere due to this since eg. for_each_intel_crtc_in_pipe_mask() will only walk the crtcs we've registered even though the passed in pipe_mask asks for more of them. But clearly the thing won't do what is expected of it when the required pipes are not present. Fix the problem by consulting the device info pipe_mask already in bigjoiner_pipes(). Cc: stable@vger.kernel.org Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221118185201.10469-1-ville.syrjala@linux.intel.comReviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> (cherry picked from commit f1c87a94) Signed-off-by:
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Tvrtko Ursulin authored
In 36537275 ("drm/i915: Simplify internal helper function signature") I broke the old platforms by not noticing engine workaround init does not initialize the list on old platforms. Fix it by always initializing which already does the right thing by mostly not doing anything if there aren't any workarounds on the list. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221118115249.2683946-1-tvrtko.ursulin@linux.intel.com (cherry picked from commit 71feb6f9) Signed-off-by:
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Matt Roper authored
The GT MCR code currently relies on uncore->lock to avoid race conditions on the steering control register during MCR operations. The *_fw() versions of MCR operations expect the caller to already hold uncore->lock, while the non-fw variants manage the lock internally. However the sole callsite of intel_gt_mcr_wait_for_reg_fw() does not currently obtain the forcewake lock, allowing a potential race condition (and triggering an assertion on lockdep builds). Furthermore, since 'wait for register value' requests may not return immediately, it is undesirable to hold a fundamental lock like uncore->lock for the entire wait and block all other MMIO for the duration; rather the lock is only needed around the MCR read operations and can be released during the delays. Convert intel_gt_mcr_wait_for_reg_fw() to a non-fw variant that will manage uncore->lock internally. This does have the side effect of causing an unnecessary lookup in the forcewake table on each read operation, but since the caller is still holding the relevant forcewake domain, this will ultimately just incremenent the reference count and won't actually cause any additional MMIO traffic. In the future we plan to switch to a dedicated MCR lock to protect the steering critical section rather than using the overloaded and high-traffic uncore->lock; on MTL and beyond the new lock can be implemented on top of the hardware-provided synchonization mechanism for steering. Fixes: 3068bec8 ("drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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- 22 Nov, 2022 4 commits
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
GVT Changes: - gvt-next stuff mostly with refactor for the new MDEV interface. i915 Changes: - PSR fixes and improvements (Jouni) - DP DSC fixes (Vinod, Jouni) - More general display cleanups (Jani) - More display collor management cleanup targetting degamma (Ville) - remove circ_buf.h includes (Jiri) - wait power off delay at driver remove to optimize probe (Jani) - More audio cleanup targeting the ELD precompute readout (Ville) - Enable DC power states on all eDP ports (Imre) - RPL-P stepping info (Matt Atwood) - MTL enabling patches (RK) - Removal of DG2 force_probe (Matt) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Y3f71obyEkImXoUF@intel.com
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2022-11-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Core Changes: - Backmerge of drm-next Driver Changes: - Restore probe_range behaviour for userptr (Matt A) - Fix use-after-free on lmem_userfault_list (Matt A) - Never purge busy TTM objects (Matt A) - Meteorlake enabling (Daniele, Badal, Daniele, Stuart, Aravind, Alan) - Demote GuC kernel contexts to normal priority (John) - Use RC6 residency types as arguments to residency functions (Ashutosh, Rodrigo, Jani) - Convert some legacy DRM debugging macros to new ones (Tvrtko) - Don't deadlock GuC busyness stats vs reset (John) - Remove excessive line feeds in GuC state dumps (John) - Use i915_sg_dma_sizes() for all backends (Matt A) - Prefer REG_FIELD_GET in intel_rps_get_cagf (Ashutosh, Rodrigo) - Use GEN12_RPSTAT register for GT freq (Don, Badal, Ashutosh) - Remove unwanted TTM ghost obj check (Matt A) - Update workaround documentation (Lucas) - Coding style and static checker fixes and cleanups (Jani, Umesh, Tvrtko, Lucas, Andrzej) - Selftest improvements (Chris, Daniele, Riana, Andrzej) Signed-off-by:
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.2-2022-11-18: amdgpu: - SR-IOV fixes - Clean up DC checks - DCN 3.2.x fixes - DCN 3.1.x fixes - Don't enable degamma on asics which don't support it - IP discovery fixes - BACO fixes - Fix vbios allocation handling when vkms is enabled - Drop buggy tdr advanced mode GPU reset handling - Fix the build when DCN is not set in kconfig - MST DSC fixes - Userptr fixes - FRU and RAS EEPROM fixes - VCN 4.x RAS support - Aldrebaran CU occupancy reporting fix - PSP ring cleanup amdkfd: - Memory limit fix - Enable cooperative launch on gfx 10.3 amd-drm-next-6.2-2022-11-11: amdgpu: - SMU 13.x updates - GPUVM TLB race fix - DCN 3.1.4 updates - DCN 3.2.x updates - PSR fixes - Kerneldoc fix - Vega10 fan fix - GPUVM locking fixes in error pathes - BACO fix for Beige Goby - EEPROM I2C address cleanup - GFXOFF fix - Fix DC memory leak in error pathes - Flexible array updates - Mtype fix for GPUVM PTEs - Move Kconfig into amdgpu directory - SR-IOV updates - Fix possible memory leak in CS IOCTL error path amdkfd: - Fix possible memory overrun - CRIU fixes radeon: - ACPI ref count fix - HDA audio notifier support - Move Kconfig into radeon directory UAPI: - Add new GEM_CREATE flags to help to transition more KFD functionality to the DRM UAPI. These are used internally in the driver to align location based memory coherency requirements from memory allocated in the KFD with how we manage GPUVM PTEs. They are currently blocked in the GEM_CREATE IOCTL as we don't have a user right now. They are just used internally in the kernel driver for now for existing KFD memory allocations. So a change to the UAPI header, but no functional change in the UAPI. From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221118170807.6505-1-alexander.deucher@amd.comSigned-off-by:
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
please pull the following etnaviv changes for the next merge window. Mostly some small workarounds to get new hardware support going. But also more fixes to the softpin MMU handling and a nice addition from Christian to make the kernel logs on hang detection more useful. Signed-off-by:
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- 21 Nov, 2022 1 commit
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 6.2: UAPI Changes: Cross-subsystem Changes: - fbdev: Add support for the nomodeset kernel parameter Core Changes: - client: Add kunit tests for drm_connector_pick_cmdline_mode() - dma-buf: Move dma_buf_mmap_internal() to new locking specification - edid: Dump EDID on drm_edid_get_panel_id() failure, Stop using a temporary device to load the EDID through the firmware mechanism - fb-helper: Remove damage worker - gem-vram: Fix deadlock in drm_gem_vram_vmap() - modes: Named mode parsing improvements - tests: Add Kunit helpers to create a DRM device Driver Changes: - hisilicon: convert to drm_mode_init() - malidp: Use drm-managed resources - msm: convert to drm_mode_init() and drm_mode_copy() - mtk: convert to drm_mode_init() - nouveau: Support backlight control for nva3 - rockchip: convert to drm_mode_copy() - sti: convert to drm_mode_copy() - v3d: Switch to drm-managed resources - vc4: Fix potential NULL pointer dereference - panels: - New panel: NewVision NV3051D Signed-off-by:
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- 18 Nov, 2022 13 commits
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Matt Roper authored
DG2 has been very usable for a while now, and all of the uapi changes related to fundamental platform usage have been finalized. Recent CI results have also been healthy, so we're ready to drop the force_probe requirement and enable the platform by default. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Radhakrishna Sripada authored
MTL LPDDR5 reported 16b with 8 channels. Previous platforms reported 32b with 4 channels and hence needed a multiplication by a factor of 2. Skip increasing the channels for MTL. v2: Use version check instead of platform check(MattR) Bspec: 64631 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
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Radhakrishna Sripada authored
MEM_SS_INFO_GLOBAL Register info read from the hardware is cached in val. However the variable is being modified when determining the DRAM type thereby clearing out the channels and qgv info extracted later in the function xelpdp_get_dram_info. Preserve the register value and use extracted fields in the switch statement. Fixes: 825477e7 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox") Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Matt Atwood authored
Add stepping-substepping info in accordance to bpsec changes. Bspec: 55376 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by:
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Imre Deak authored
MTL+ requires the AUX_IO power for the main link only on eDP, so don't enable it in other cases. v2: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
Factor out functions to get/put the AUX_IO power domain for the main link on DDI ports. While at it clarify the corresponding code comment. No functional change. v2: - s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put) (Jani) - Clarify in the code comment that AUX_IO is needed only by TypeC besides eDP/PSR. v3: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. v4: - Don't call fetch_and_zero() with side-effect during variable declaration. (Ville) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Add the missing DC_OFF power domain -> DC_OFF power well mappings on all platforms. This didn't cause a problem as the DC_OFF power domain is only used on JSL, where the mapping was already correct. Signed-off-by:
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Imre Deak authored
BXT and GLK were missing the AUX_IO_A power domain -> PHY A common power well mapping, add these now. This didn't cause a problem as the AUX_IO_A and DDI_LANES_A power domains are acquired together. Signed-off-by:
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Imre Deak authored
Starting with TGL eDP is supported on ports B+ (besides port A), so make sure DC states are not blocked on any such ports. For this add an AUX_IO_<port> power domain for each port with eDP support. These domains similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an enabled port, whereas the existing AUX_<port> domains enable both the AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers. v2: (Ville) - Split the change using AUX vs. AUX_IO on port A to a separate patch. - Select AUX_IO vs. AUX based on crtc_state->has_psr instead of is_edp(). v3: - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr. v4: - Fix warn in intel_display_power_aux_io_domain(). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Use the AUX_IO_A display power domain only for eDP on port A where PSR is also supported. This is the case where DC states need to be enabled while the output is enabled - ensured by AUX_IO_A domain not enabling the DC_OFF power well. Otherwise port A can be treated the same way as other ports with an external DP output: using the AUX_<port> domain which disables the unrequired DC states. This change prepares for the next patch enabling DC states on all ports supporting eDP/PSR besides port A. v2: - Check the encoder PSR capability instead of PSR being enabled in the crtc_state, as the latter can be changed with a fastset. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
Move the definition of the AUX_IO_A power domain, requiring only the corresponding AUX_IO_A power well to be enabled, before all the AUX_<port> power domains, which require both the AUX_IO_<port> and the DC_OFF power wells to be enabled. No functional change. Signed-off-by:
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Imre Deak authored
Since the current size of intel_display_power_domain_set struct is close to 1kB, it's better to use preallocated memory for it. The only user of the intel_display_power_get/put_in_set() allocating the struct on stack is hsw_get_pipe_config(), so we can avoid potential stack overallocations by moving the struct here to the preallocated intel_crtc struct (hsw_get_pipe_config() is non-reentrant wrt. each CRTC). This patch replaces https://lore.kernel.org/intel-gfx/20221107170917.3566758-5-imre.deak@intel.com/T/#md3f6cdf17fcdSuggested-by:
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Imre Deak authored
The intel_display_power_*_domain() functions should always warn if a default domain is returned as a fallback, fix this up. Spotted by Ville. Fixes: 979e1b32 ("drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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- 17 Nov, 2022 10 commits
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Alex Deucher authored
All of the IP specific versions are the same now, so we can just use a common function. Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This matches what we do for psp 3.1 and makes ring_init common for all PSP versions. Acked-by:
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Randy Dunlap authored
Fix these kernel-doc complaints: drivers/gpu/drm/amd/display/dc/dc.h:505: warning: cannot understand function prototype: 'struct dc_clocks ' dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID' not described in enum 'pipe_split_policy' dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID_MULT_DISP' not described in enum 'pipe_split_policy' dc.h:532: warning: Incorrect use of kernel-doc format: * @fw_based_mclk_switching Fixes: ea76895f ("drm/amd/display: Document pipe split policy") Fixes: 1682bd1a ("drm/amd/display: Expand kernel doc for DC") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Jonathan Kim authored
FW fix available to enable cooperative launch for GFX10.3. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Ramesh Errabolu authored
Allow user to know number of compute units (CU) that are in use at any given moment. Enable access to the method kgd_gfx_v9_get_cu_occupancy that computes CU occupancy. Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by:
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Tao Zhou authored
Register related irq handler. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Register irq handler. Signed-off-by:
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Tao Zhou authored
Add interrupt source id macros. Signed-off-by:
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Tao Zhou authored
Initialize JPEG RAS structure and add error query interface. Signed-off-by:
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Tao Zhou authored
Initialize VCN RAS structure and add RAS status query function. Signed-off-by:
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