- 20 Feb, 2015 13 commits
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Chandrakala Chavva authored
Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by:
Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by:
Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8936/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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David Daney authored
It wasn't being saved on task switch. Signed-off-by:
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David Daney authored
The wide multiplier is twice as wide, so we need to save twice as much state. Detect the multiplier type (CPU type) at start up and install model specific handlers. [aleksey.makarov@auriga.com: conflict resolution, support for old compilers] Signed-off-by:
Leonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by:
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Markos Chandras authored
Allow more compression algorithms as well as uncompressed uImage.bin to be generated. An uncompressed image might be useful to rule out problems in the decompression code in the bootloader or even speed up the boot process at the expense of a bigger uImage file. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9271/Signed-off-by:
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David Daney authored
Signed-off-by:
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Lars-Peter Clausen authored
There are currently no gio device drivers that implement suspend/resume and this patch removes the bus specific legacy suspend and resume callbacks. This will allow us to eventually remove struct bus_type legacy suspend and resume support altogether. gio device drivers wanting to implement suspend and resume can use dev PM ops which will work out of the box without further modifications necessary. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Acked-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8920/Signed-off-by:
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Zubair Lutfullah Kakakhel authored
Without these, there are multiple definitions of pci_proc_domain() and pci_domain_nr() if linux/pci.h and asm/pci.h are included. Add #ifdefs around them Signed-off-by:
Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by:
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Manuel Lauss authored
The current code uses bits 0-6 of the sys_cpupll register to calculate core clock speed. However this is only valid on Au1300, on all earlier models the hardware only uses bits 0-5 to generate core clock. This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll is set as well, which ultimately lead the code to calculate a bogus cpu core clock and also uart base clock down the line. Signed-off-by:
Manuel Lauss <manuel.lauss@gmail.com> Reported-by:
John Crispin <blogic@openwrt.org> Tested-by:
Bruno Randolf <br1@einfach.org> Cc: stable@vger.kernel.org [v3.17+] Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9279/Signed-off-by:
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Manuel Lauss authored
set_cpuspec() has been dropped with commit 074cf656 ("MIPS: Alchemy: remove cpu_table.") in late 2008. Signed-off-by:
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Manuel Lauss authored
This was lost during the rewrite of clock framework support. Signed-off-by:
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Manuel Lauss authored
The Au1000 and Au1500 calculate the LRCLK a bit differently than newer models: a single bit in MEM_STCFG0 selects if pclk is divided by 4 or 5. Signed-off-by:
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Steven J. Hill authored
Build set and clear macros for the PageGrain register. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9289/Signed-off-by:
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- 19 Feb, 2015 8 commits
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Steven J. Hill authored
* Clean up white spaces and tabs. * Get rid of remaining hardcoded values for calculating shifts and masks. * Get rid of redundant macro values. * Do not use page table bits directly in #ifdef's. Signed-off-by: -
Ralf Baechle authored
Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/linux into mips-for-linux-next
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James Hogan authored
Export the _save_msa asm function used by the lose_fpu(1) macro to GPL modules so that KVM can make use of it when it is built as a module. This fixes the following build error when CONFIG_KVM=m and CONFIG_CPU_HAS_MSA=y due to commit f798217d ("KVM: MIPS: Don't leak FPU/DSP to guest"): ERROR: "_save_msa" [arch/mips/kvm/kvm.ko] undefined! Fixes: f798217d (KVM: MIPS: Don't leak FPU/DSP to guest) Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/9261/Signed-off-by:
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James Hogan authored
Export the _save_fp asm function used by the lose_fpu(1) macro to GPL modules so that KVM can make use of it when it is built as a module. This fixes the following build error when CONFIG_KVM=m due to commit f798217d ("KVM: MIPS: Don't leak FPU/DSP to guest"): ERROR: "_save_fp" [arch/mips/kvm/kvm.ko] undefined! Signed-off-by:
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Kevin Cernekee authored
This function was renamed to mips_cpu_irq_of_init(), so fix it to avoid a compile error. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8834/Signed-off-by:
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Petr Malat authored
Provide correct siginfo_t.si_stime on MIPS64 Bug description: MIPS version of copy_siginfo() is not aware of alignment on platforms with 64-bit long integers, which leads to an incorrect si_stime passed to signal handlers, because the last element (si_stime) of _sifields._sigchld is not copied. If _MIPS_SZLONG is 64, then the _sifields starts at the offset of 4 * sizeof(int). Patch description: Use the generic copy_siginfo, which doesn't have this problem. Signed-off-by:
Petr Malat <oss@malat.biz> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8671/Signed-off-by:
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Markos Chandras authored
We need to check the ASEs support against the core's CFLAGS instead of depending to the default -march option from the toolchain. Signed-off-by:
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Ralf Baechle authored
The loongson 3A cores do not select a suitable -march option so the build system uses the default one from the toolchain. This may or may not be suitable for a loongson 3A build. In order to avoid that, we explicitly set a suitable -march option for that core. Furthermore, some very old compilers don't support -march= at all and there is the possibility of toolchain combinations such as GCC 4.9 and binutils 2.24 for which -march=loongson3a will result in MIPS64 R2 code being generated but then rejected by GAS. So treat the Longsoon 3A as an R2 CPU. Signed-off-by:
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- 17 Feb, 2015 19 commits
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Markos Chandras authored
Add a Malta defconfig for the 32-bit MIPS R6 core as emulated by QEMU. Signed-off-by: -
Markos Chandras authored
The Malta platform supports MIPS R6 (via QEMU or real bitstreams) so add support for it. Signed-off-by: -
Markos Chandras authored
The previous implementation did not cover all possible FPU combinations and it silently allowed ABI incompatible objects to be loaded with the wrong ABI. For example, the previous logic would set the FP_64 ABI as the matching ABI for an FP_XX object combined with an FP_64A object. This was wrong, and the matching ABI should have been FP_64A. The previous logic is now replaced with a new one which determines the appropriate FPU mode to be used rather than the FP ABI. This has the advantage that the entire logic is much simpler since it is the FPU mode we are interested in rather than the FP ABI resulting to code simplifications. This also removes the now obsolete FP32XX_HYBRID_FPRS option. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by: -
Markos Chandras authored
MIPS32 R6 has a 64-bit FPU so add the necessary MIPS R6 definition. Signed-off-by: -
Markos Chandras authored
A prctl() call to set FR=0 for MIPS R6 should not be allowed since FR=1 is the only option for R6 cores. Cc: Paul Burton <paul.burton@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Signed-off-by: -
Markos Chandras authored
MIPS R2 FPU instructions are also present in MIPS R6 so amend the preprocessor definitions to take MIPS R6 into consideration. Signed-off-by: -
Markos Chandras authored
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: -
Leonid Yegoshin authored
MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
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Markos Chandras authored
If Config5/LLB is set in the core, then software can write the LLB bit in the LLADDR register. Signed-off-by: -
Markos Chandras authored
The LLBIT (bit 4) in the Config5 CP0 register indicates the software availability of the Load-Linked bit. This bit is only set by hardware and it has the following meaning: 0: LLB functionality is not supported 1: LLB functionality is supported. The following feature are also supported: - ERETNC instruction. Similar to ERET but it does not clear the LLB bit in the LLAddr register. - CP0 LLAddr/LLB bit must be set - LLbit is software accessible through the LLAddr[0] This will be used later on to emulate R2 LL/SC instructions. Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: -
Markos Chandras authored
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: -
Markos Chandras authored
MIPS R6 added the following four instructions which share the BGTZ and BGTZL opcode: BLTZALC: Compact branch-and-link if GPR rt is < to zero BGTZALC: Compact branch-and-link if GPR rt is > to zero BLTZL : Compact branch if GPR rt is < to zero BGTZL : Compact branch if GPR rt is > to zero BLTC : Compact branch if GPR rs is less than GPR rt BLTUC : Similar to BLTC but unsigned Signed-off-by: -
Markos Chandras authored
MIPS R6 added the following four instructions which share the BLEZ and BLEZL opcodes: BLEZALC: Compact branch-and-link if GPR rt is <= to zero BGEZALC: Compact branch-and-link if GPR rt is >= to zero BLEZC : Compact branch if GPR rt is <= to zero BGEZC : Compact branch if GPR rt is >= to zero BGEC : Compact branch if GPR rs is less than or equal to GPR rt BGEUC : Similar to BGEC but unsigned. Signed-off-by: -
Markos Chandras authored
MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by:
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