- 03 Dec, 2023 35 commits
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Luca Weiss authored
Use the qcom,domain property instead of the deprecated qcom,apr-domain, which in turn also fixes a bunch of dtbs_checks warnings. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-msm8953-misc-fixes-v2-2-df86655841d9@z3ntu.xyzSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Dmitry Baryshkov authored
The RB1 platform doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so existing board-2.bin files will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120,variant=Thundercomm_RB1' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc c800000.wifi: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 ath10k_snoc c800000.wifi: qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 ath10k_snoc c800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc c800000.wifi: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc c800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc c800000.wifi: htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Enable the Microchip mcp2518fd hosted on the SPI5 bus. Signed-off-by:
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Konrad Dybcio authored
Add the required nodes to support display output via the HDMI port. Reviewed-by:
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Konrad Dybcio authored
Add interconnect provider nodes and hook up interconnects to consumer devices, including bwmon. Reviewed-by:
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Konrad Dybcio authored
Add the required nodes to support display on QCM2290. Reviewed-by:
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Konrad Dybcio authored
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one. Failing to provide it may result in register accesses failing and that's never good. Add the missing path. Signed-off-by:
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Konrad Dybcio authored
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one. Failing to provide it may result in register accesses failing and that's never good. Add the missing path. Signed-off-by:
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Konrad Dybcio authored
When a handle to QMP is accessible, we can query even more internal power management stats. Add it. Signed-off-by:
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Jianhua Lu authored
Add type-c node to feature otg function and set usb-role-switch property for usb_1_dwc3 to enable usb otg. Reviewed-by:
Jianhua Lu <lujianhua000@gmail.com> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231126022849.14273-2-lujianhua000@gmail.comSigned-off-by:
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Jianhua Lu authored
There are two typos in this dtsi, so fix it. classis -> chassis. 80700000 -> 80600000 Reviewed-by:
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André Apitzsch authored
Consider an object near to the sensor when their distance is about 4 cm or below. Reviewed-by:
André Apitzsch <git@apitzsch.eu> Link: https://lore.kernel.org/r/20231126-bqm5_prox-v2-1-b7defc3979ac@apitzsch.euSigned-off-by:
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Konrad Dybcio authored
Enable the QCA bluetooth on RB2. It identifies like the following: Bluetooth: hci0: QCA Product ID :0x0000000a Bluetooth: hci0: QCA SOC Version :0x40020150 Bluetooth: hci0: QCA ROM Version :0x00000201 Bluetooth: hci0: QCA Patch Version:0x00000001 Bluetooth: hci0: QCA controller version 0x01500201 Signed-off-by:
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Konrad Dybcio authored
Hook up UART3, usually used for communicating with a Bluetooth module. Signed-off-by:
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Luca Weiss authored
Configure and enable the WCNSS which provides WiFi and Bluetooth on this device using the WCN3680B chip. Signed-off-by:
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Stephen Boyd authored
This link got broken by commit e790a4ce ("arm: docs: Move Arm documentation to Documentation/arch/") when the doc moved from arm/ to arch/arm/. Fix the link so that it can continue to be followed. Fixes: e790a4ce ("arm: docs: Move Arm documentation to Documentation/arch/") Cc: Alexandre TORGUE <alexandre.torgue@foss.st.com> Cc: Yanteng Si <siyanteng@loongson.cn> Cc: Jonathan Corbet <corbet@lwn.net> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20231129030443.2753833-1-swboyd@chromium.orgSigned-off-by:
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Komal Bajaj authored
Add DTS for Qualcomm qcs6490-rb3gen2 board which uses QCS6490 SoC. This adds debug uart and usb support along with regulators found on this board. Co-developed-by:
Naina Mehta <quic_nainmeht@quicinc.com> Signed-off-by:
Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by:
Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20231129065816.26409-4-quic_kbajaj@quicinc.comSigned-off-by:
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Komal Bajaj authored
Add DTS for Qualcomm IDP platform using QCM6490 SoC. This adds debug uart, eMMC and usb support along with regulators found on this board. Signed-off-by:
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Komal Bajaj authored
Document the qcom,qcm6490-idp and qcs6490-rb3gen2 boards. qcm6490-idp based off qcm6490 SoC derived from sc7280 meant for various form factor including IoT and qcs6490-rb3gen2 based off qcs6490 SoC derivative of qcm6490 without internal modem. Co-developed by: Naina Mehta <quic_nainmeht@quicinc.com> Signed-off by: Naina Mehta <quic_nainmeht@quicinc.com> Signed-off-by:
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Tengfei Fan authored
Some gpios are reserved for other subsystems, so mark these reserved gpios. Suggested-by:
Can Guo <quic_cang@quicinc.com> Signed-off-by:
Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by:
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Tengfei Fan authored
Add uart support for QRD4450 for enable uart console. Reviewed-by:
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Tengfei Fan authored
Add base description of UART and TLMM nodes which helps SM4450 boot to shell with console on boards with this SoC. Reviewed-by:
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Tengfei Fan authored
Add device node for RPMH and Global clock controller on Qualcomm SM4450 platform. Reviewed-by:
Ajit Pandey <quic_ajipan@quicinc.com> Signed-off-by:
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Ajit Pandey authored
Add apps_rsc node and cmd_db memory region for sm4450. Reviewed-by:
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Robert Marko authored
Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to find them by matching globaly by name. If not passed directly, driver maintains backwards compatibility by then falling back to global lookup. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Robert Marko authored
QMP PCI PHY PIPE clocks are inputs for the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC. This has a benefit that it avoids doing a global matching by name. Signed-off-by:
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Gianluca Boiano authored
This change add spi_3, spi_5 and spi_6 interfaces to MSM8953 devices. Signed-off-by:
Gianluca Boiano <morf3089@gmail.com> Acked-by:
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Luca Weiss authored
Configure the thermals for the QUIET_THERM, CAM_FLASH_THERM, MSM_THERM and RFC_CAM_THERM thermistors connected to PM7325. With this PMIC the software communication to the ADC is going through PMK7325 (= PMK8350). Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231013-fp5-thermals-v1-4-f14df01922e6@fairphone.comSigned-off-by:
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Luca Weiss authored
Configure the thermals for the XO_THERM line connected to PMK7325 (named in software PMK8350). Signed-off-by:
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Luca Weiss authored
Configure the thermals for the CHARGER_SKIN_THERM and USB_CONN_THERM thermistors connected to PM7250B. Signed-off-by:
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Luca Weiss authored
Add the defines for the ADC channels found on the PM7325. The list is taken from downstream msm-5.4 and adjusted for mainline. Signed-off-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20231013-fp5-thermals-v1-1-f14df01922e6@fairphone.comSigned-off-by:
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Manivannan Sadhasivam authored
UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231012172129.65172-6-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Reviewed-by:
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Sridharan S N authored
IPQ bootloaders do not need these information to select the the DTB blob. So dropping the board names from board section. Signed-off-by:
Sridharan S N <quic_sridsn@quicinc.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230927093130.4098385-1-quic_sridsn@quicinc.comSigned-off-by:
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Gokul Sriram Palanisamy authored
Add the APCS, A53 PLL, cpu-opp-table nodes to set the CPU frequency at 800MHz (idle) or 1.008GHz. Co-developed-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Reviewed-by:
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- 14 Nov, 2023 5 commits
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Dmitry Baryshkov authored
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by:
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Dmitry Baryshkov authored
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by:
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Dmitry Baryshkov authored
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by:
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Dmitry Baryshkov authored
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by:
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Dmitry Baryshkov authored
Change the USB QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by:
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